Major CPU Design Steps 1 Using independent RTN, write the microoperations required for all target ISA instructions. 2 Construct the datapath required by the microoperations identified in step 1. 3 Identify and define the function of all control signals needed by the datapath.
3 Control unit design, based on micro-operation timing and control signals identified: - Hard-Wired: Finite-state machine implementation. - Microprogrammed. EECC550 - Shaaban #1 Lec # 4
Winter 2000
12-13-2000
Datapath Design Steps • Write the micro-operation sequences required for a number of representative instructions using independent RTN. • From the above, create an initial datapath by determining possible destinations for each data source (i.e registers, ALU). – This establishes the connectivity requirements (data paths, or connections) for datapath components. – Whenever multiple sources are connected to a single input, a multiplexer of appropriate size is added.
• Find the worst-time propagation delay in the datapath to determine the datapath clock cycle. • Complete the micro-operation sequences for all remaining instructions adding connections/multiplexers as needed. EECC550 - Shaaban #2 Lec # 4
Winter 2000
12-13-2000
MIPS Instruction Formats 31
R-Type
26 op
rs
6 bits
I-Type: ALU
31
26
31
J-Type: Jumps
5 bits
11
6
0
rd
shamt
funct
5 bits
5 bits
6 bits
16
0 immediate
rt 5 bits
16 bits
26 op 6 bits
• • • • • •
5 bits 21
rs
6 bits
16 rt
5 bits
op
Load/Store, Branch
21
0 target address 26 bits
op: Opcode, operation of the instruction. rs, rt, rd: The source and destination register specifiers. shamt: Shift amount. funct: selects the variant of the operation in the “op” field. address / immediate: Address offset or immediate value. target address: Target address of the jump instruction.
EECC550 - Shaaban #3 Lec # 4
Winter 2000
12-13-2000
MIPS R-Type (ALU) Instruction Fields R-Type: All ALU instructions that use three registers OP
rs
6 bits
5 bits
rt 5 bits
rd
shamt
funct
5 bits
5 bits
6 bits
• op: Opcode, basic operation of the instruction. – For R-Type op = 0 • rs: The first register source operand. • rt: The second register source operand. • rd: The register destination operand. • shamt: Shift amount used in constant shift operations. • funct: Function, selects the specific variant of operation in the op field. Operand register in rs Destination register in rd
Examples:
add $1,$2,$3 sub $1,$2,$3
Operand register in rt
and $1,$2,$3 or $1,$2,$3
EECC550 - Shaaban #4 Lec # 4
Winter 2000
12-13-2000
MIPS ALU I-Type Instruction Fields I-Type ALU instructions that use two registers and an immediate value Loads/stores, conditional branches.
• • • •
OP
rs
rt
6 bits
5 bits
5 bits
immediate 16 bits
op: Opcode, operation of the instruction. rs: The register source operand. rt: The result destination register. immediate: Constant second operand for ALU instruction. Source operand register in rs Result register in rt
Examples:
add immediate:
addi $1,$2,100
and immediate
andi $1,$2,10
Constant operand in immediate
EECC550 - Shaaban #5 Lec # 4
Winter 2000
12-13-2000
MIPS Load/Store I-Type Instruction Fields OP
rs
rt
6 bits
5 bits
5 bits
address 16 bits
• op: Opcode, operation of the instruction. – For load op = 35, for store op = 43. • rs: The register containing memory base address. • rt: For loads, the destination register. For stores, the source register of value to be stored. • address: 16-bit memory address offset in bytes added to base register. base register in rs
Offset
Examples:
source register in rt
Store word:
sw 500($4), $3
Load word:
lw $1, 30($2)
Destination register in rt
base register in rs Offset
EECC550 - Shaaban #6 Lec # 4
Winter 2000
12-13-2000
MIPS Branch I-Type Instruction Fields
• • • •
OP
rs
rt
6 bits
5 bits
5 bits
address 16 bits
op: Opcode, operation of the instruction. rs: The first register being compared rt: The second register being compared. address: 16-bit memory address branch target offset in words added to PC to form branch address. Register in rt Register in rs
Examples:
Branch on equal
beq $1,$2,100
Branch on not equal
bne $1,$2,100
offset in bytes equal to instruction field address x 4
EECC550 - Shaaban #7 Lec # 4
Winter 2000
12-13-2000
MIPS J-Type Instruction Fields J-Type: Include jump j, jump and link jal OP
jump target
6 bits
26 bits
• op: Opcode, operation of the instruction. – Jump j op = 2 – Jump and link jal op = 3 • jump target: jump memory address in words. Jump memory address in bytes equal to instruction field jump target x 4
Examples:
Branch on equal
j 10000
Branch on not equal jal 10000
EECC550 - Shaaban #8 Lec # 4
Winter 2000
12-13-2000
A Subset of MIPS Instructions ADD and SUB: addU rd, rs, rt subU rd, rs, rt
31
OR Immediate: ori rt, rs, imm16
31
26 op
rs
6 bits
op
6 bits
31
6 bits
5 bits
rd
shamt
funct
5 bits
5 bits
6 bits 0
16 bits
0 immediate
5 bits
21 rs
0
16 rt
5 bits
6
immediate
5 bits
21 rs
11
16 rt
5 bits
26 op
5 bits
21 rs
LOAD and STORE Word lw rt, rs, imm16 31 26 sw rt, rs, imm16 op
16 rt
5 bits
26 6 bits
BRANCH: beq rs, rt, imm16
21
16 bits
16 rt 5 bits
0 immediate 16 bits
EECC550 - Shaaban #9 Lec # 4
Winter 2000
12-13-2000
Instruction Processing Steps Instruction Fetch Next
Obtain instruction from program storage
Update program counter to address
Instruction
of next instruction
Instruction
Determine instruction type
Decode
Obtain operands from registers
Execute
Compute result value or status
Result Store
}
Common steps for all instructions
Store result in register/memory if needed (usually called Write Back).
EECC550 - Shaaban #10 Lec # 4
Winter 2000 12-13-2000
Overview of MIPS Instruction Micro-operations •
•
•
All instructions go through these two steps: – Send program counter to instruction memory and fetch the instruction. (fetch) – Read one or two registers, using instruction fields. (decode) • Load reads one register only. Additional instruction execution actions (execution) depend on the instruction in question, but similarities exist: – All instruction classes use the ALU after reading the registers: • Memory reference instructions use it for address calculation. • Arithmetic and logic instructions (R-Type), use it for the specified operation. • Branches use it for comparison. Additional execution steps where instruction classes differ: – Memory reference instructions: Access memory for a load or store. – Arithmetic and logic instructions: Write ALU result back in register. – Branch instructions: Change next instruction address based on comparison.
EECC550 - Shaaban #11 Lec # 4
Winter 2000 12-13-2000
A Single Cycle Implementation Design target : A single-cycle instruction implementation All micro-operations of an instruction are to be carried out in a single system clock cycle.
EECC550 - Shaaban #12 Lec # 4
Winter 2000 12-13-2000
Datapath Components Instruction Word
Two state elements needed to store and access instructions: 1 Instruction memory: • Only read access. • No read control signal. 2 Program counter: 32-bit register. • Written at end of every clock cycle: No write control signal. • 32-bit Adder: To compute the the next instruction address.
EECC550 - Shaaban #13 Lec # 4
Winter 2000 12-13-2000
More Datapath Components Register File
Main ALU
Register File: • Contains all registers. • Two read ports and one write port. • Register writes by asserting write control signal • Writes are edge-triggered. • Can read and write to the same register in the same clock cycle.
EECC550 - Shaaban #14 Lec # 4
Winter 2000 12-13-2000
Register File Details
RW RA RB
Write Enable 5
5
5
• Register File consists of 32 registers: busA – Two 32-bit output busses: busW 32 32 32-bit busA and busB 32 Registers busB Clk – One 32-bit input bus: busW 32 • Register is selected by: – RA (number) selects the register to put on busA (data): busA = R[RA] – RB (number) selects the register to put on busB (data): busB = R[RB] – RW (number) selects the register to be written via busW (data) when Write Enable is 1 Write Enable: R[RW] ← busW • Clock input (CLK) – The CLK input is a factor ONLY during write operations. – During read operation, it behaves as a combinational logic block: • RA or RB valid => busA or busB valid after “access time.”
EECC550 - Shaaban #15 Lec # 4
Winter 2000 12-13-2000
Idealized Memory
Write Enable
Address
Data In DataOut • Memory (idealized) 32 32 – One input bus: Data In. Clk – One output bus: Data Out. • Memory word is selected by: – Address selects the word to put on Data Out bus. – Write Enable = 1: address selects the memory word to be written via the Data In bus. • Clock input (CLK): – The CLK input is a factor ONLY during write operation, – During read operation, this memory behaves as a combinational logic block: • Address valid => Data Out valid after “access time.”
EECC550 - Shaaban #16 Lec # 4
Winter 2000 12-13-2000
R-Type Example: Micro-Operation Sequence For ADDU addU rd, rs, rt OP
rs
6 bits
5 bits
rt 5 bits
rd
shamt
funct
5 bits
5 bits
6 bits
Instruction Word ← Mem[PC]
Fetch the instruction
PC ← PC + 4
Increment PC
R[rd] ← R[rs] + R[rt]
Add register rs to register rt result in register rd
EECC550 - Shaaban #17 Lec # 4
Winter 2000 12-13-2000
Building The Datapath Instruction Fetch & PC Update:
Portion of the datapath used for fetching instructions and incrementing the program counter.
EECC550 - Shaaban #18 Lec # 4
Winter 2000 12-13-2000
Simplified Datapath For R-Type Instructions
EECC550 - Shaaban #19 Lec # 4
Winter 2000 12-13-2000
More Detailed Datapath For R-Type Instructions With Control Points Identified Rd Rs RegWr
5 Rw
32 Clk
Ra Rb
32 32-bit Registers
ALUctr
5 busA 32 busB
ALU
busW
5
Rt
Result 32
32
EECC550 - Shaaban #20 Lec # 4
Winter 2000 12-13-2000
R-Type Register-Register Timing Clk Old Value Rs, Rt, Rd, Op, Func
PC
Clk-to-Q New Value Old Value
ALUctr
Old Value
RegWr
Old Value
busA, B
Old Value
busW
Old Value
Instruction Memory Access Time New Value Delay through Control Logic New Value New Value Register File Access Time New Value ALU Delay New Value
Rd Rs Rt RegWr 5 5 5 busA 32 busB 32
ALU
busW 32 Clk
Rw Ra Rb 32 32-bit Registers
Register Write Occurs Here
ALUct r Result 32
EECC550 - Shaaban #21 Lec # 4
Winter 2000 12-13-2000
Logical Operations with Immediate Example:
Micro-Operation Sequence For ORI ori rt, rs, imm16 31
26 op 6 bits
21
16
rs 5 bits
rt 5 bits
0 immediate 16 bits
Instruction Word ← Mem[PC]
Fetch the instruction
PC ← PC + 4
Increment PC
R[rt] ← R[rs] OR ZeroExt[imm16]
OR register rs with immediate field zero extended to 32 bits, result in register rt
EECC550 - Shaaban #22 Lec # 4
Winter 2000 12-13-2000
Datapath For Logical Instructions With Immediate Rd RegDst
Rt
Mux RegWr
5 Rw
busW
Rs 5 5
ALUctr busA
Ra Rb
32 Clk
ALU
32
32 32-bit Registers busB
16
ZeroExt
imm16
32
Mux
32
Result
32 ALUSrc
EECC550 - Shaaban #23 Lec # 4
Winter 2000 12-13-2000
Load Operations Example:
Micro-Operation Sequence For LW lw rt, rs, imm16 31
26 op 6 bits
21 rs 5 bits
16 rt 5 bits
0 immediate 16 bits
Instruction Word ← Mem[PC]
Fetch the instruction
PC ← PC + 4
Increment PC
R[rt] ← Mem[R[rs] + SignExt[imm16]]
Immediate field sign extended to 32 bits and added to register rs to form memory load address, word at load address to register rt
EECC550 - Shaaban #24 Lec # 4
Winter 2000 12-13-2000
Additional Datapath Components For Loads & Stores
Inputs for address and write (store) data Output for read (load) result
16-bit input sign-extended into a 32-bit value at the output
EECC550 - Shaaban #25 Lec # 4
Winter 2000 12-13-2000
Datapath For Loads Rd RegDst
Mux RegWr 5
32 Clk
Rs 5 5
ALUctr busA
Rw Ra Rb 32 32-bit Registers
32
32 ALUSrc
Mux
Extender
16
32 MemWr
Mux
busB 32
imm16
W_Src ALU
busW
Rt
WrEn Adr Data In 32 Clk
Data Memory
32
ExtOp
EECC550 - Shaaban #26 Lec # 4
Winter 2000 12-13-2000
Store Operations Example:
Micro-Operation Sequence For SW sw rt, rs, imm16 31
26 op 6 bits
21 rs 5 bits
16 rt 5 bits
0 immediate 16 bits
Instruction Word ← Mem[PC]
Fetch the instruction
PC ← PC + 4
Increment PC
Mem[R[rs] + SignExt[imm16]] ← R[rt]
Immediate field sign extended to 32 bits and added to register rs to form memory store address, register rt written to memory at store address.
EECC550 - Shaaban #27 Lec # 4
Winter 2000 12-13-2000
Datapath For Stores Rd RegDst
Rt
ALUctr
MemWr
W_Src
Mux RegWr 5
32 Clk
5
Rt 5 busA
Rw Ra Rb 32 32-bit Registers
32
WrEn Adr Data In 32
32
ExtOp
Mux
16
Extender
imm16
32
Mux
busB 32
ALU
busW
Rs
Clk
Data Memory
32
ALUSrc
EECC550 - Shaaban #28 Lec # 4
Winter 2000 12-13-2000
Conditional Branch Example:
Micro-Operation Sequence For BEQ beq rs, rt, imm16 31
26 op 6 bits
21 rs 5 bits
16 rt 5 bits
0 immediate 16 bits
Instruction Word ← Mem[PC]
Fetch the instruction
PC ← PC + 4
Increment PC
Equal ← R[rs] == R[rt]
Calculate the branch condition
if (COND eq 0) PC ← PC + 4 + ( SignExt(imm16) x 4 ) else PC ← PC + 4
Calculate the next instruction’s PC address
EECC550 - Shaaban #29 Lec # 4
Winter 2000 12-13-2000
ALU to evaluate branch condition Adder to compute branch target: • Sum of incremented PC and the sign-extended lower 16-bits on the instruction.
Datapath For Branch Instructions
EECC550 - Shaaban #30 Lec # 4
Winter 2000 12-13-2000
More Detailed Datapath For Branch Operations Cond
Instruction Address 32
4 Adder
00
32
PC
Mux Adder
PC Ext
imm16
RegWr 5 busW Clk
Rs 5
Rt 5
Rw Ra Rb 32 32-bit Registers
busA 32 busB 32
Equal?
nPC_sel
Clk
EECC550 - Shaaban #31 Lec # 4
Winter 2000 12-13-2000
Combining The Datapaths For Memory Instructions and R-Type Instructions
Highlighted muliplexors and connections added to combine the datapaths of memory and R-Type instructions into one datapath
EECC550 - Shaaban #32 Lec # 4
Winter 2000 12-13-2000
Instruction Fetch Datapath Added to ALU R-Type and Memory Instructions Datapath
EECC550 - Shaaban #33 Lec # 4
Winter 2000 12-13-2000
A Simple Datapath For The MIPS Architecture Datapath of branches and a program counter multiplexor are added. Resulting datapath can execute in a single cycle the basic MIPS instruction: - load/store word - ALU operations - Branches
EECC550 - Shaaban #34 Lec # 4
Winter 2000 12-13-2000
Single Cycle MIPS Datapath Necessary multiplexors and control lines are identified here:
EECC550 - Shaaban #35 Lec # 4
Winter 2000 12-13-2000
Putting It All Together: A Single Cycle Datapath
nPC_sel
RegDst
00
MemtoReg
Rs Rt 5 busA Rw Ra Rb 32 32-bit Registers busB 32 5
imm16
16
0
1
32 Data In
32
ExtOp
Clk
0
32
Mux
Clk
Extender
Clk
=
32 Mux
PC
Mux Adder
PC Ext
imm16
ALUctr MemWr
Equal
ALU
Adder
32
Imm16
0
RegWr 5 busW
Rd
Rd Rt
1 4
Rt
Instruction
Rs
Adr
Inst Memory
WrEn Adr
1
Data Memory
ALUSrc
EECC550 - Shaaban #36 Lec # 4
Winter 2000 12-13-2000
Adding Support For Jump:
Micro-Operation Sequence For Jump: J j jump_target OP
Jump_target
6 bits
26 bits
Instruction Word ← Mem[PC]
Fetch the instruction
PC ← PC + 4
Increment PC
PC ← PC(31-28),jump_target,00
Update PC with jump address
EECC550 - Shaaban #37 Lec # 4
Winter 2000 12-13-2000
Datapath For Jump Next Instruction Address 32
nPC_sel
4
JUMP
Adder
00
32
PC
Mux
Mux
Adder
imm16
PC Ext
Instruction(15-0)
32
4
Clk PC+4(31-28)
Instruction(25-0) jump_target
26
Shift left 2
28
32
EECC550 - Shaaban #38 Lec # 4
Winter 2000 12-13-2000
Rd
Rs
Rt
Op Fun
Adr
Instruction
Instruction Memory
Imm16 Jump_target
Control Unit nPC_sel RegWr RegDst ExtOp ALUSrc ALUctr MemWr MemtoReg Jump
Equal
DATA PATH EECC550 - Shaaban #39 Lec # 4
Winter 2000 12-13-2000
Single Cycle MIPS Datapath Extended To Handle Jump with Control Unit Added
EECC550 - Shaaban #40 Lec # 4
Winter 2000 12-13-2000
Control Signal Generation See Appendix A
func 10 0000 10 0010
Don’t Care
op 00 0000 00 0000 00 1101 10 0011 10 1011 00 0100 00 0010 add
sub
ori
lw
sw
beq
jump
RegDst
1
1
0
0
x
x
x
ALUSrc
0
0
1
1
1
0
x
MemtoReg
0
0
0
1
x
x
x
RegWrite
1
1
1
1
0
0
0
MemWrite
0
0
0
0
1
0
0
nPCsel
0
0
0
0
0
1
0
Jump
0
0
0
0
0
0
1
ExtOp
x
x
0
1
1
x
x
Add
Subtract
Or
Add
Add
Subtract
xxx
ALUctr
EECC550 - Shaaban #41 Lec # 4
Winter 2000 12-13-2000
The Concept of Local Decoding op
00 0000
00 1101 10 0011 10 1011 00 0100 00 0010
R-type
ori
lw
sw
beq
jump
RegDst
1
0
0
x
x
x
ALUSrc
0
1
1
1
0
x
MemtoReg
0
0
1
x
x
x
RegWrite
1
1
1
0
0
0
MemWrite
0
0
0
1
0
0
Branch
0
0
0
0
1
0
Jump
0
0
0
0
0
1
ExtOp
x
0
1
1
x
x
“R-type”
Or
Add
Add
Subtract
xxx
ALUop
func op 6
Main Control
6 ALUop
ALUctr 3 ALU
N
ALU Control (Local)
EECC550 - Shaaban #42 Lec # 4
Winter 2000 12-13-2000
Local Decoding of “func” Field func op
Main Control
6
ALU Control (Local)
6 ALUop N
ALUop (Symbolic) ALUop funct
ALUctr 3
R-type
ori
lw
sw
“R-type”
Or
Add
0 10
0 00
1 00
Instruction Operation add
10 0010
subtract
10 0100
and
10 0101
or
10 1010
set-on-less-than
ALU
10 0000
ALUctr
beq
jump
Add
Subtract
xxx
0 00
0 01
xxx
ALUctr
ALU Operation
000
Add
001
Subtract
010
And
110
Or
111
Set-on-less-than
EECC550 - Shaaban #43 Lec # 4
Winter 2000 12-13-2000
The Truth Table for ALUctr funct
ALUop (Symbolic) ALUop
Instruction Op.
0000
add
beq
0010
subtract
R-type
ori
lw
sw
“R-type”
Or
Add
Add
Subtract
0100
and
0 10
0 00
0 00
0 01
0101
or
1010
set-on-less-than
1 00
ALUop
func
bit bit bit
bit bit bit bit
ALU Operation
ALUctr bit bit bit
0
0
0
x
x
x
x
Add
0
1
0
0
x
1
x
x
x
x
Subtract
1
1
0
0
1
x
x
x
x
x
Or
0
0
1
1
x
x
0
0
0
0
Add
0
1
0
1
x
x
0
0
1
0
Subtract
1
1
0
1
x
x
0
1
0
0
And
0
0
0
1
x
x
0
1
0
1
Or
0
0
1
1
x
x
1
0
1
0
Set on