CPU Testing & Testable Design • Problems in CPU Testing • Test Strategies for CPU • Testable CPU Architectures • Testable Design Flow
CPU testing & testable Design .1
Problems in CPU Testing ! ! ! ! ! ! ! ! !
Large number of registers Large number of small buffers or queues Different sizes of memories Complex random logic (control path & data path) Cell library Board level testing Test control Test integration & Scheduling CAD tool supporting CPU testing & testable Design .2
Test Strategies ! ! ! ! ! !
Design hierarchy & Circuit partitioning BIST for large memories / arrays Special BIST for small buffers Scan for random logic Shadow registers where necessary Boundary Scan for test control and board level testing ! Functional testing ! Testable design rules ! CAD tool usage CPU testing & testable Design .3
Design Hierarchy & Circuit Partitioning ! Represent the design in a hierarchy fashion ! Try to identify all the bottom components ! Identify test strategy for each bottom component ! Go up the hierarchy from the bottom component, determine test strategy for the circuitry between components
CPU testing & testable Design .4
Example: a simple pipelined CPU ! 4-level hierarchy ! 5 functional units
- IFU: instruction fetch unit - CU: control unit - BU: bus unit - RFU: register file unit - EU: execution unit
CPU testing & testable Design .5
Example: a simple pipelined CPU (cont.) CHIP
IFU
PC
ROM
CU
IR
BU
RFU
OIR
BYPASS
LOGIC
EU
ALU
PSR
SHIFT
ARITHMETIC
CPU testing & testable Design .6
BIST for Large Memories / Arrays ! ! ! !
Use BIST for all large memories Test all memories in parallel Deal with memories with different sizes Deal with memories with different widths of cells ! Use one test controller
CPU testing & testable Design .7
Memory BIST Architecture with a Compressor Before
After
di
addr
wen
Memory Module
data
sys_di data sys_addr sys_wen clk q hold_l Memory rst_l Module test_h si se
so
CPU testing & testable Design .8
rst_l clk hold_l test_h
di addr Memory wen
data
Module
compress_h clk rst si se
Compressor
sys_addr sys_di sys_wen
Algorithm-Based Pattern Generator
Memory BIST Architecture with a Compressor (cont.)
q so
BIST Circuitry CPU testing & testable Design .9
sys_addr1 sys_addr2 sys_di2 sys_wen2 sys_addr3 sys_di3 sys_wen3 rst_ l clk hold_l test_h
Algorithm-Based Pattern Generator
Three Memories and One Compressor addr1 di2 addr2 wen2 di3 addr3 wen3
ROM4KX4 Module
4
data
RAM8KX8 Module
8
data
RAM8KX8 Module
data
8
compress_h BIST Circuitry se si
q Compressor
so
CPU testing & testable Design .10
Small Buffer Testing ! Several FIFOs reside in a superscalar CPU − Instruction queue − Reorder buffer − Reservation station ! Memory cells as well as the control logic for these cells must be tested ! Need a special test architecture to test these buffers
CPU testing & testable Design .11
Parallel Test Architecture for Small Buffers done
BIST circuit
bist
Control
Data
FIFO1
FIFO2
FIFO3
Serial
Serial
Serial
Address
Multiple Input Signature Register CPU testing & testable Design .12
Scan for random logic ! ! ! !
Scan cell design Full scan v.s. partial scan Single scan chain v.s. multiple scan chain Test control and scheduling
CPU testing & testable Design .13
Scan Cell Design D
Q
Q
DI
MUX
DI
SI CK
N/T (SE)
Q
DI
D
Q
Q,SO
CK
Q,SO
DI
Φ
Φ SI
Φ
ΦT
Φ + ΦT
CPU testing & testable Design .14
A possible method to drive multiple scan chains using a data input Scan_In
TDI
CKT_C CKT_C
CKT_B CKT_B
CKT_A CKT_A
TAP TDO
MISR
CPU testing & testable Design .15
Boundary scan for test control and board level testing ! Must provide test control signals and test data for - Scan testing (including shadow registers) - BIST - Small buffer testing - Any ad hoc techniques ! Must define some new Boundary Scan instructions ! Must determine required TMS signals CPU testing & testable Design .16
Functional testing ! Several circuitry, especially some interconnections are not tested by component testing - interconnections network - Interface between register file and ALU or other logic - Bus Interface unit - Cache control logic - Global chip function ! Functional testing is carried out by executing a sequence of instructions CPU testing & testable Design .17
An example of functional testing for cache control For functional fault - Cache always miss
Processor
0
1
Tag=A
Tag=A
Tag=A
Tag=A
Tag=A
Tag=A
0
0
0
1
0
1
Cache (enable)
Main Memory
Initial state
Cache (disable)
Main Memory
(write 1 of tag A )
Fault activation
Cache (enable)
Main Memory
( read different data into processor)
Fault detection
CPU testing & testable Design .18
Testable design rules and requirements ! Important for full-custom design ! All custom design must have a corresponding Verilog RTL code ! If DFT circuitry is added by tools, then usually the rules are satisfied
CPU testing & testable Design .19
Some design rules (1) Synchronous design ONLY except reset (2) Avoid gated clocks (3) Must be able to break global feedback loop (4) SET/RESET must not be driven by other FF/s (5) ROM and RAM must be isolatable during testing
CPU testing & testable Design .20
CAD Tools Usage ! Should try to use tools wherever possible ! Comparison between - Syntest - Mentor Graphics - Synopsys ! Usually tools are not turn-key solutions, much human work has to be done to generate - Data files - Control files - Interface between tools CPU testing & testable Design .21
Testable CPU architecture ! A generic global CPU test architecture ! A simple pipelined CPU ! Test control architecture for the pipelined CPU
CPU testing & testable Design .22
A Global Test Control Architecture Data Scan Register
Data Scan Chain
Boundary Scan Register
Combinational
PRPG
BIST Core
MISR
S1
PRPG
BIST setup Register
BIST Core
MISR
S2
S4
PRPG BIST Core PRPG/Signature Analyzer
S5
PRPG/Signature Analyzer
S3
Compressor Register
BIST Core
Shadow Register Bypass Register
TDI
TDO
TCK TMS
IR
Decoder
TAP Controller
CPU testing & testable Design .23
Boundary Scan Instruction Set ! 2 classes, 9 instructions Class IE E E
Group
Instruction
Opcod e
T a rget re gister
M a nd atory
B YP AS S
000 0
By pass r egister
S AM ./P R EL O AD
000 1
Boundary sca n register
EXTES T
111 1
Boundary sca n register
C LA M P
001 0
By pass r egister
HI G H Z
001 1
By pass r egister
S H AD O W
S HA S C A N
010 0
Sh adow re giste r
SCAN
IN SCA N
010 1
D ata sca n chain
BI S T
S E T BI S T
0110
S etup scan chain
R U N BI S T
0111
Compressor register
1 1 4 9.1 Instruction O ption al
User defin ed instruction
CPU testing & testable Design .24
A Simple Pipelined CPU ! Input pins: CLK, RESET, INIT, SWITCH ! Output pins: HALT, STORE, MEM_ADDR, MEM_OUT IFU OIR CLK
BU HALT
IR
RESET INIT
FRU ROM CU
SWITCH PC
STORE MEM_ADDR[3:0]
EU ALU
MEM_OUT[31:0]
PSR
CPU testing & testable Design .25
Instruction Set Class
Inst.
Opcod Format
Description
CTL
NOP
0000
HALT
1111
HALT
Halt system
LOAD
0010
LOAD DST, #n
Load constant to register
0010
LOAD DST,[mem] Load mem data to register
STORE 0011
STORE mem, #n Store constant tomemory
e
LD/ST
0011
LOGIC
NOP
No operation
STORE mem,
Store register data to
SRC
memory
AND
1100
AND DST, SRC
SRC & DST to DST
OR
1101
OR DST, SRC
SRC | DST to DST
XOR
1110
XOR DST, SRC
SRC ^ DST to DST
LSF
1000
LSF DST, SRC
SRC > DST to DST
BRA
0001
BRA LABEL
Branch to label always
BRN
0001
BRN LABEL
Branch to label if negative
BRANCH
ARITH.
BRZ
0001
BRZ LABEL
Branch to label if zero
BRP
0001
BRP LABEL
Branch to label if parity
BRE
0001
BRE LABEL
Branch to label if even
BRC
0001
BRC LABEL
Branch to label if carry
ADD
0100
ADD DST, SRC
SRC + DST to DST
SUB
0101
SUB DST, SRC
SRC - DST to DST
MUL
0110
MUL DST,SRC
SRC * DST to DST
CPU testing & testable Design .26
Test Strategy Blocks
C om ponent
Architecture
T est strategy
PC
R andom logic gates
Scan
ROM
M emory elem ents
BIS T
IR
R egister
Scan
O IR
R egister
S can
ALU
C om binational gates
Scan
PSR
R egister
S can
FRU
R _F ILE
M emory elem ents
BIS T
CU
CU
C om binational gates
Scan
BU
BU
R andom logic gates
Scan
Shadow R egister
Shadow R egister
R egister
Shadow Sampling
C H IP
CPU
C om plex circuit design
IF U
EU
Scan Boundary Scan F unctional testing
CPU testing & testable Design .27
CPU Test Control Architecture PC
IR
OIR PSR BU
CU and ALU PRPG
ROM
MISR
PRPG
Register File
MISR
Shadow Register Bypass Register
TDI TCK TMS
IR
TDO
Decoder TAP Controller
CPU testing & testable Design .28
Boundary Scan Instruction Set ! 2 classes, 8 instructions Class
Group
Instruction
Opcode
Target register
IEEE 1149.1 Instruction
Mandatory
BYPASS
0000
Bypass register
SAM./PRELOAD
0001
Boundary scan register
EXTEST
1111
Boundary scan register
CLAMP
0010
Bypass register
HIGHZ
0011
Bypass register
SHADOW
SHASCAN
0100
Shadow register
SCAN
INSCAN
0101
Data scan chain
BIST
RUNBIST
0110
Compressor register
Optional User defined instruction
CPU testing & testable Design .29
Testable Design Flow ! Traditional design flow ! Testable design flow at gate-level ! DFT instruction phases ! Testable design flow at RTL/gate level ! Automatic DFT insertion ! Test Scheduling
CPU testing & testable Design .30
Traditional Design Flow (cell-based) Requirement
Internal Spec. Architecture
External Spec. Instruction set Golden Device Behavioral Level
RTL Model Synthesis to Gate Gate Level Simulation DFT Insertion Synthesis to Layout Post-Layout Simulation Production of chip System at Work
CPU testing & testable Design .31
Testable Design Flow (gate-level)
Test Programs and Test Patterns
Requirement
Internal Spec. Architecture
External Spec. Instruction set Golden Device Behavioral Level
Choose Test Strategies Insert/Verify BIST Circuit
MBISTArchitect
Synthesize/ Optimize Design
Design Compiler
Testability Analysis
Test Compiler
Insert Shadow Register
Shell Script
RTL Model Synthesize/ Optimize Design Synthesis to Gate Gate Level Simulation
DFT Insertion
Insert Internal Scan Circuit
DFTadvisor
Insert/Verify Boundary Scan
BSDArchitect
Integrate DFT Circuits Synthesis to Layout Post-Layout Simulation
Design Compiler
Synthesize/ Optimize Design
Shell Script Design Compiler
Production of chip
Functional Testing
Verilog XL
System at Work
Generate/Verify Test Patterns
FastScan
CPU testing & testable Design .32
DFT Insertion Phase ! ! ! ! ! ! ! ! ! ! ! !
Choose test strategy Insert/Verify BIST circuit Synthesize/optimize design Testability analysis Insert shadow register Insert internal scan circuit Synthesize/optimize design Insert/Verify Boundary Scan Integrate DFT components Synthesize/optimize design Functional testing Generate/verify test patterns CPU testing & testable Design .33
Memory BIST Insertion ! Automatic RTL BIST insertion ! MBISTArchitect and batch program Library
MBIST rom_mbist.do
rom.v
rom_tb.v
rom_con.v
rom_bist.v
rom_comp.v
mod_con.awk
mod_tv.awk test_rom.v
top.v
RTL Simulation
rom_gate.v
Compass Library
Gate Level Simulation
Synthesis Process Design Compiler dc_script top_gate.v
Compare
Section Over
CPU testing & testable Design .34
Shadow Register Insertion ! Test points selection " Testability analysis - Gate level - Test Compiler Circuit characteristic ! Automatic shadow register insertion ! Shadow register generator C-shell script ! RT-level insertion CPU testing & testable Design .35
Scan Chain Insertion ! Automatic scan chain insertion Gate level Scan cell identification Scan cell connection ! DFTAdvisor or Test Compiler 328 scan cells
CPU testing & testable Design .36
Choose Test Strategies
Internal Spec. Architecture
External Spec. Instruction set Golden Device Behavioral Level
RTL Model
DFT Insertion
Insert/Verify BIST Circuit Insert/Verify Boundary Scan
BSDArchitect
Synthesize/ Optimize Design Design Compiler Testability Analysis Insert Shadow Register Synthesize/ Optimize Design Insert Internal Scan Circuit
Synthesis to Layout Post-Layout Simulation
Integrate DFT Circuits Synthesize/ Optimize Design
Production of chip
Functional Testing Generate/Verify Test Patterns
System at Work
MBIST
Test Compiler Shell Script Design Compiler DFTAdvisor Shell Script
Gate Level
Test Programs and Test Patterns
Requirement
RTL Model
Testable Design Flow (RTL/Gate)
Design Compiler Verilog XL FastScan
CPU testing & testable Design .37
Automatic DFT Insertion ! Programs list
Step
Programs
Functions
Test Program
program_gen
Batch Files
Code translation NOP insertion Synthesis/Optimization Batch execution
MBISTArchitect
BIST synthesis
mon_tn.awk
Test fixture modification
mon_con.awk
Top module modification
Design Compiler
Synthesis/Optimization
Batch files
Batch execution
Testability analysis
Test Compiler
Testability analysis
Shadow Register
shadow_gen
Shadow Register
Pipelined CPU Synthesis Design Compiler
BIST Insertion
Insertion Scan Chain Insertion
synthesis DFTAdvisor
Scan chain synthesis
Batch file
Batch execution
Boundary Scan Insertion BSDArchitect
DFT Integration
Boundary Scan synthesis
Batch file
Batch execution
dft_gen
DFT integration
Test Fixture Generation fixture_gen
Test fixture generation
Test Patterns Generation FastScan
Test patterns generation
Tutorial Demo Program
Batch file
Batch execution
dft_tutorial
Tutorial demo program
CPU testing & testable Design .38
Test Scheduling Start P BS Components
F
P F N
BS Public Instructions P
Diagnostics
BIST Testing
Y
F Diagnostics
P F N
Diagnostics
Scan Testing
P F
Y
P Shadow Sampling
Y
N
Normal Testing
F Diagnostics
N
Y
P END
CPU testing & testable Design .39
Conclusions Most important tasks in CPU testing ! Design partition - RTL codes ! Test training course ! Design rules / constrains ! Test architecture decision ! Close link between design team and test team ! Good management for coordination ! Test integration ! Functional testing CPU testing & testable Design .40
