ICSE2004 Proc. 2004, Kuala Lumpur, Malaysia

DESIGN AND CHARACTERIZATION OF INPUT AND OUTPUT (10) PADS Yuzman Yusoff, Ahmad Sabirin Zoolfakar, Shahrul Aman and Dr. Mohd Rais Ahmad MIMOS BERHAD Technology Park Malaysia, 57000 Kuala Lumpur, Malaysia Email: [email protected]

Abstract - The design of reliable input and output (110) pads require thorough understanding of process technology, especially for electrostatic discharge (ESD) and latch up protection. This paper describes the design methodology and characterization of 1/0 pads. This methodology includes SPICE simulation, layout drawing and silicon characterization. The ItO pads have been experimentally evaluated under test devices fabricated using MIMOS's 3.3V 0.35um CMOS process technology. The comparison between the measured performance and simulation is presented in this paper.

circuitry protection to prevent ESD and latch up[ 1]. This paper provides a simple and practical design methodology for 110 pads. A simplified flow chart of 1/0 design is shown in Figure 1. This conceptual method has been used by MIMOS in developing I/O library for 3.3V 0.35um CMOS technology and has been experimental verified by silicon test.

I. INTRODUCTION

The rapid advancement of semiconductor process technology to sub-micron dimension has led to the development of broad spectrum of integrated circuit (IC) system components. These complex system components are being further integrated on silicon to form ever larger System-on-aChip (SoC). However, this same process technology is defined by smaller and more delicate structures that must interface and communicate with the harsh external world with voltages and currents that will easily damage and destroy the IC. The only thing that stands between the harsh external environment and the protected internal environment is a specialized library of 110 pads that handle the buffering, translating and interfacing of external signals from the bonding pad to the internal signals of the core of the IC. Therefore, the requirement of 1/0 pads in IC design is also providing the

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Fig. I Flow diagram for designing I/O pad

ICSE2004 Proc. 2004, Kuala Lumpur, Malaysia

II. 1/0 SPECIFICATIONS

The design of 1/0 pad proceeds first by identifying the characteristics of the target [/0. Generally, this specification consists of DC and AC characteristics that were defined in a level of voltage, current and speed timing. The DC characteristics for MIMOS 0.35um 1/0 pad are shown in Table 1. The I10 circuits were designed based on those specifications and verified through accurate simulation using HSpice simulator. Parameter

VDD

VDDO

Tp

Max

Lnit

2.97

3.3

3.63

V

0

25 0.8

125

°C

Input Low

Input Low

2.0

supply

3.3

3.63

voltage

Temperature

T)

VIL

Voltage

VIH VOL

VOH IOL

Voltage Output Low

Voltage Output High Voltage Output Low Current

Current Input Low

lt, In{

Leakage

V

Input High

4 8

mA

4 8

mA nA

_

10

Leakage

_ _ _ __ __

V V

2.4

-10

V

V

0.4

Output High

IOH

_

Mm 2.97

Description

Power supplY voltage IOIESD

10

nA nA

Table 1. DC characteristics of 0.35um 1/O pad

III. CIRCUIT DESIGN An input pad, which is connected directly to external circuitry, is often triggered by the external overshooting or undershooting of voltage and current signals[2]. Therefore the gate of p/n transistors may experience voltages and currents beyond the normal operating range for CMOS process. Typically a combination of a resistance and clamp diodes are used to limit this potentially destructive voltage. When there is a large overshoot or undershoot, these clamp diodes must turn on and provide clamping. Resistor is used to limit the peak current that flows in the diodes in the event of an unusual voltage excursion. The value for this resistor is in range of 200 ohm to 3k ohm. For logic circuitry, it is usually

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formed by two CMOS inverters that act as a buffer which provide sufficient drive for internal load. The circuit of input pad is shown in Figure 2(a). Besides ESD circuitry, an output pad also consists of predriver and driver. The predriver is that stage of logic between the core circuits and the final output driver that adjusts the timing and the drive capability to the final 1/0 output stage such that it meets the required I/O specification. Fast predriver reduce the propagation time for the data to flow from the chip core to the output driver. In Figure 2(b), the NAND and NOR gates constitute the predriver in the output Tristate pad. Meanwhile, the driver is one big inverter that have sufficient drive capability to achieve adequate rise and fall times into a given capacity load. When protecting the pad, the output NMOS is the weakest link. Usually, if the NMOS can be protected, then other devices will also be safe. Thus, a pair of diodes is added in parallel with the output transistor. The design of bidirectional 1/0 pad is very straightforward. It is just a combination of input and output pad. The protection scheme is also identical to those used in the input and output pads. This bidirectional 1/0 circuit is illustrated in Figure 2(c). Unlike other pads, layout of VDD and Vss supply pads are easily designed. Basically, these pads consist of several stripes of metal layers with one of them is connected to the bonding pad through multiple of vias.

PAD

Dl

Figure 2(a) Input circuit

ICSE2004 Proc. 2004, Kuala Lumpur, Malaysia

OE PAD

-DO

Fig 2(b) Output tristate circuit

Fig 2(c). Bidirectional I/O circuit

IV. CIRCUIT SIMULATION In order to perform simulation, an accurate and detail transistor model is required, especially for sizing the drivers and predrivers. The functionality of I/O circuits has been verified through HSpice simulation by using Bsim3v3 level 49 transistor model of our 0.35um process. In verifying the performance of L/O circuit, there are three types of simulation that need to be completed. They are functional, DC and AC simulation. 1.I 1: 4

pad is constructed with buffer circuitry, the output signals should be similar to the input signal. The functional simulation waveform of input pad is shown in Fig 3. For DC parameters simulation, the following setup conditions were applied: VOH - Precondition the output to logic ' 1' - Pump current sink to the output node and measure the output voltage Precondition the output to VOL logic '0' - Pump current source to the output node and measure the output voltage IOH - Precondition the output to logic ' 1' - Apply voltage to the output node and measure the output current IOL - Precondition the output to logic '0' - Apply voltage to the output node and measure the output current IIL - Precondition input to logic '0' - Measure the current input IIH - Precondition input to logic '1 ' - Measure the current input current leakage 'leak - Static measured from Vdd to Vss at standby bias condition In this I/O design, the AC timing information was extracted based on stimulus of input signal having 20MHz with rising and falling edge of 0. lns. All data were checked with 1OMHz and 40MHz for the typical model.

-I

...Z.

,Ne.;~.

'..

....

I.

-

Fig 3. The functional simulation waveform of an input pad, XCTIBOO Applying a pulse of voltage with high and low signal through the input pin can validate the functional of [/0 pad. As most of the [/0

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Fig 4. Propagation delay waveform The propagation delay through a cell is the sum of the intrinsic delay, the load

ICSE2004 Proc. 2004, Kuala Lumpur, Malaysia dependent delay, and the input slew delay. This waveform is illustrated in Fig 4. Delays are defined as the time interval between the input stimulus crossing 10% of Vdd and the output crossing 90% of Vdd

N-well 1 3aiia

P+

V. LAYOUT DESIGN

Fig 6. Layout of Nwell-diode

In the development of 1/0 pad, the most eminent and crucial part is the layout design. It has been observed repetitively that an incorrect layout can jeopardize ESD and latch up protection. This un-wanted circumstance may cause the damage to the I/O peripheral devices as well to the weak internal core devices. As the most sensitive device to ESD, the NMOS transistors need to be properly layout to prevent them from experience a second breakdown. This is because of the NPN snapback getting initiated at low voltages. An example of the layout design for this device is shown in Fig 5. In this layout, the spacing between the drain diffusion and poly gate is important as well as the number and placement of contacts. A similar layout can also be used for the PMOS transistor.

Latchup in CMOS design is formed by the parasitic of p-n-p-n structure between VDD and Vss[3]. Thus, the double guard rings is used to block the latchup path between the output PMOS and NMOS in the I/O pad as shown in Fig 7.

FKt

I- I_r

I __- I I- Source

I 1 I Figure 5. NMOS output transistor layout Diodes are very important in handling ESD whether they exist in a specific junction diode or MOS diode. The application of reverse biased diode helps ESD protection by avoiding high voltages pass through into the internal logic. There are several methods in designing layout for diode and one of them is shown in Fig 6.

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Fig 7. PMOS output transistor layout with double guard rings

To implement a proper and successful layout for I/O pad, the following guidelines are useful: ESD rules for NMOS and PMOS protection . All protection devices should follow finger types * Contact number of both drain and source should be equal - The contact to contact spacing should follow minimum design rule * Double columns of contact should be used if possible * The NMOS source should be placed outwards facing P+ guard ring and PMOS drains should place outward facing the N+ guard ring * The ESD protection devices should be surrounded by the appropriate guard ring Latchup prevention * Any diffusion connecting to IO pads is considered hot diffusion area and should be surrounded by double guard ring

ICSE2004 Proc. 2004, Kuala Lumpur, Malaysia

* Provide a P+ guard ring around the NMOS and N+ guard ring around PMOS devices . The pickups should be close to the active sources. * All the guard rings and pickups should be connected to Vdd or Vss with very low series resistance. * For special device such as diode or resistor, double guard ring should be inserted surrounding and between them The final layout of MIMOS 0.35um 1/0 is shown in Fig 8.

re-simulating the circuit design. The difference to the previous simulation is the parasitics capacitance values that were extracted from final layout included in the circuit netlist that was used for simulation. Therefore this post layout simulation will give more precise and more accurate timing reports.

X. 1/0 LIBRARY CHARACTERIZATION

An ASIC design required a detail information on rise and fall time of the 1/0. Thus a library of I/O should be prepared and provided to designer. XI. SILICON TEST

On-silicon tests were executed on standalone I/O structures. There were three types of I/O test structures characterized; input pad (XCTIBOO), output pad with 4mA (XCTOB04) and bidirectional pad with 4mA and 50kohm pull-up resistor (XCTBU54). Fig 8. The final layout of 0.35um IO

Fig 9(a), (b) and (c) show actual snapshots of the input, output and bidirectional 110, respectively.

VII. PHYSICAL LAYOUT VERIFICATION Once a layout has been constructed, it is necessary to verify that the layout conforms to the geometric design rules and match to the circuit netlist, which was created at previous stage. These verifications can be achieved by running DRC and LVS check and they should clean from errors. VIII. LAYOUT EXTRACTION The layout extraction is done to create a data for the post layout simulation that described in the next section. Besides transistor connectivity, all parasitics capacitances and resistances are reported in the extracted netlist. IX. POST LAYOUT SIMULATION

In order to verify 1/0 performance, an accurate timing analysis can be achieved by

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rig 9b) AL I UBU4 paa test structure

ICSE2004 Proc. 2004, Kuala Lumpur, Malaysia

INPUT PAD VIL For Lot X441 1.00E-03

I~~~~~~~~~~~~~~~~~~~~~

5.00E-04 -1

5:

The tests were conducted on the Agilent Technology 4073 Ultra Advanced DC Automatic Tester (automatic), Keithley 236 Source Measuring Units (manual) and HP4145B Semiconductor Parameter Analyzer (manual).

Input Pad The input pads portray acceptable IIL, IIH, VL and VI as all these parameters lie within specification as reported previously. The specification values are valid for all the I/O DC parameters (i.e. input, output and bidirectional pad). FigIO(a), (b), (c) and (d) shows the DC electrical characteristic of the Input Pad. INPUT PAD IIL For Lot X441

3.00E-12

-

2.OOE-12

1.OOE-12 O.ooE+00

-2.OOE- 12

'Ilr.qlmm.

20

-5.00E-04

-

-1.OOE-03

-

.-

40

-9

-.-

60

80

*Wi *W2'W3+W4aW6

site

Fig lO(c ) VIL characteristic of XCTIBOO INPUT PAD VIH For Lot X441

3.40E+00 1-1

3

5:

3.35E+00 3.30E+00 -..

3.25E+00

3.20E+o0

.

W1IW2 W3xW4 X W6

If

20

0

40

80

60

Site

Fig 10(d) VmI characteristic of XCTIBOO

Output Pad Fig 11(a) and (b) show results for Low Level Output Voltage and High Level Output Voltage, respectively. Both of the values also project acceptable range within specifications. OUTPUT PAD VOL For Lot X441

1-Wl

W2

,W3 .W4 *W61

8.OOE-01 7.OOE-01 6.OOE-01 -i 5.00E-01 0 > 4.OOE-01 3.OOE-01 2.00E-01 0

-3.OOE-1 2 Site

1-

Fig 10(a) IIL characteristic of XCTIBOO INPUT PAD IIH For Lot X441 5.OOE-12 4.OOE-12 3.00E-12 2.OOE-12 . 1.OOE-12 : 0.OOE+-00 R,`,7AW 'f .1 OoE-12 ( I 0 *2.OOE-12 -3.OOE-12 -4.OOE- 12 -5ooE- 12

.Amftkllll a pi-Noi

flL, &AAAO*AL..4'1

_j o.0oE+oo

* W1 A

aW2 AW3 .W4 .W61

.

n 9

n

20

40

SITE

A -I

.Wi *.W2

40

I MI.

-

60'

-'

60

Fig 11 (a) VOL characteristic of XCTOB04

-I

.W3 A W4 -W6 Site

Fig 10(b) IIH characteristic of XCTIBOO

0-7803-8658-2/04/$20.00(c)2004 IEEE

-Moft

a

---

532

80

ICSE2004 Proc. 2004, Kuala Lumpur, Malaysia

The results indicate that the I/O pads behave well on silicon. All DC parameters characterized were within expectations and meet design specifications.

OUTPUT PAD VOH For Lot X441 3.1 OE+00

-

3.OOE+00

-

2.90E+00 > 2.80E+002.70E+000 2.60E+00 2.50E+00 2.40E+00

A

.

I

,3

XII. CONCLUSION

WI *W2 AW3 .W4 .W61

Amie|{l nn C.%VLcTVV

rin f r-

;J

f nn

20

0

40

80

60

SITE Fig 11 (b) VOH ch aracteristic of XCTOB04

Both of the input and output pad have low leakage currents, ILK. The readings are within specifications of -10nA to +10nA as shown on Table 1. These small currents are due to the transistor leakages. INPUT and OUPUT PAD ILK For Lot X441

4.50E-09

3.50E-09

9

-

1

0

f * OutpUt Input

2.50E-09 1 .50E-09

5.0OE-1O 5nCJOAFA-1n u_--

s.

&6

a

W_&

,_i,_l k-

--w-

I

.r

tQn u a

-.M.

A1 n

Site

Fig 12. ILK characteristics of XCTIBOO and XCTOBO4

Bidirectional Pad

The IIL for the bidirectional I/O shows high current around 83uA flowing into the PAD. However, this is expected because of the 50k ohm pull up circuitry that contributes to the uA current (about 73uA). The ILK, IIL, VOL and VOH are within specifications. Table 2 illustrates a summary of the parameters tested. SITE

ILK

I____ (nA) 14.40 S2 S1O 8.700 11.40 S20 14.10 S30

IIL

(uA) 83.91 84.94 84.27 83.63

IIH

(nA)

(mV)

VOL

VOH

11.37 10.55 10.48 10.74

186 186 149 184

3.265 3.260 3.252 3.251

(V)

Table 2. DC Parameters result of XCTBU54

0-7803-8658-2/04/$20.00(c)2004 IEEE

ACKNOWLEDGEMENT A task of this magnitude would not be possible without the support, guidance, advice and valuable time and efforts of many individuals. A special gratitude to all process and test engineers who were involved directly or indirectly in the fabrication and test of the 10 pad test vehicles. REFERENCES

'

a

.

A simplified and practical methodology of I/O pad has been presented in this paper. The design simulation closely correlates to the actual tested values on silicon. Hence the methodology is n successful and the 1/0 is ready to be implemented in the IC design.

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[1] Duvvury C and Amerasekera A "State-of-the-art issues for technology and circuit design of ESD protection in CMOS ICs" Semicond. Sci. Technol. pp 833-850 1996 [2] Ker M D, Lo W Y and Wu C Y "New experimental methodology to extract compact layout rules for latch up prevention in bulk CMOS IC's" IEEE Int. Conf on Custom Integrated Circuits, pp. 143-146 1999 [3] Dabral S and Maloney T J " Basic ESD and V/O Design" Wiley Interscience publication 1998 [4] M.J Hargrove, S. Voldman, R. Gauthier, J. Brown, K Duncan and w Craig, "Latchup in CMOS Technology," IEEE Int. Reliability Physics Symp., pp.269-278,1998