Capacitance of Forward Biased Diode •
When a diode changes from reverse biased (with little current through it) to forward biased (with significant current across it) the charge being stored near and across the junction changes
•
Part of the change in charges is due to the change in the width of the depletion region and therefore the amount of immobile charge stored in it ( Cj)
•
An additional change in the charge storage is necessary to account for the excess of minority carriers close to the depletion region edges required for the diffusion current to exists. This component is modeled by another capacitance, called the diffusion capacitance ( Cd)
•
As a diode is turned off (changes from forward biased to reverse biased) for a short period of time a current will flow in the negative direction until the minority charge is removed
Charge of Forward Biased Diode Direction of positive current immobile charge
electron diffusion
- - - - - -
P
hole diffusion
In the P region we have a lot of holes that will diffuse toward the N region
+ + +
+ + +
+ + +
+ + +
N
In the N region we have a lot of electrons that will diffuse toward the P region
Depletion Region
Total Capacitance of Forward Biased Diode •
It is the sum of the diffusion capacitance Cd and the depletion capacitance Cj C total C d C j
•
For a forward biased diode the junction capacitance is roughly approximated by: C j2C j0 C j 2C j0
•
for V D0.75 0
The approximation is not critical since the diffusion capacitance is typically much larger than than the depletion capacitance C d C j
Diffusion Capacitance •
To find the diffusion capacitance we first find the minority charge “close” the depletion edges Qd and then differentiate it with respect to the voltage applied Vd. Small signal diffusion capacitance
C d
d Qd dVd
VD
I d @ V D T VT
The diffusion capacitance of a forward biased diode is proportional to the diode current
excess of minority charge (holes) stored in the N region
Diffusion Charge Q d Q p Q n
Q p q A n p x ' dx ' q A n p 0 e 0
x' Lp
excess of minority charge (electrons) stored in the P region
dx '
0
Vd VT
q A n p0 e 1 e
x' Lp
2
dx '
0
Vd VT
q A n p0 e 1 e 2 i
x' Lp
n q A e 1 L p e ND n p x ' n p x ' 0e x' np0
T
dx '
0
Vd VT
Vd
q A n i Ln V Q n e 1 NA
x' Lp 0
Vd
q A n 2i L p V e 1 ND T
pn(=0)
p n p n 0e
x' Lp
Ln
np(x'=0)
0 -xp
n p0 e 0
Vd VT
p n0 e
Vd VT
0 pn0 xn
x
Diffusion Charge •
The excess hole charge stored in the N region is given by: p n x n p n0 e V Q p A q pn x n p n0 L p
1 A q L p p n0 e L 2p L 2p A J p I p I p p Dp Dp V d V T
qDp J p p n0 e V Lp
d
V T
p n0 eV V 1 J p d
•
T
1
Lp qDp
L p D p p
Similarly, the excess electron charge stored in the P region is: Q n I n n
d
V T
1
Total Diffusion Charge •
Thus, the total excess minority carrier charge is: Q d Q p Q n I p p I n n
•
Since the diode current is I d I p I n it is more convenient to express the excess charge as: Q d TI d
(where T is called mean transit time )
Diffusion Capacitance
dQ d C d dV d
dI d 1 r d dV d
VD
VD
d T I d dV d
Vd VT
d I se 1 dV d
T
VD
dI d dV d
Vd VT
VD
Id C d T VT
I se VT
VD
VD
VD
T rd
I d I s VT
VD
Id VT
VD
Transition Time •
The general expression for T is quite cumbersome: T C dr d
where
dI d 1 rd dV d
C d
d Qd dVd
with
VD
VD
with
2 i
2 i
Vd VT
q A Dp n q A Dn n I d e 1 Ln N A Lp ND
2 i
2 i
Vd VT
q A n L p q A n Ln Qd e 1 ND NA
Transition Time •
In practice, since usually diodes are single sided (i.e. one side will be much more heavily doped than the other side) the minority charge storage in the heavily doped side can be ignored 2 i
Vd VT
q An Lp Q p e 1 ND
•
2
Vd
q A n i Ln V Q n e 1 NA T
Assuming the P side is more heavily doped than the N side: N A N D Q p Q n Q d Q p I d I p
2
Lp T p Dp
NOTE: •Holes (Qp) are minority carriers on the N side • Electrons (Qn) are minority carriers on the P side
Single Sided Diodes •
One side of the diode is more heavily doped than the other
•
Many of the junctions encountered in integrated circuits are onesided junctions with the lightly doped side being the substrate or the well.
•
Foe single sided diodes the depletion region will extend mostly on the lightly doped side.
•
The depletion capacitance is almost independent of the doping concentration on the heavily doped side
Single Sided Diodes •
The PN junctions inside CMOS ICs are single-sided
•
NMOS transistors have parasitic diodes with the N side more heavily doped than the P side: N D N A
•
PMOS transistors have parasitic diodes with the P side more heavily doped than the N side: N A N D
•
NOTE: in general within an MOS transistor, it is undesirable to have a forward biased junction, it usually means there is a problem.
Schottky Diodes •
A different type of diode, can be realized by contacting a metal to a lightly doped semiconductor region.
•
The use of a lightly doped semiconductor, causes a depletion region to form at the interface between the aluminum anode and the n+ silicon region
Schottky Diodes •
The voltage drop of a forward biased Schottky diode is smaller. The value depends on the metal used. For aluminum is approx 0.5 V
•
When the diode is forward biased there is no minority charge storage in the lightly doped n+ region. Thus Cd = 0
•
The absence of diffusion capacitance makes the diode much faster.
Diodes realized in CMOS technology
NOTE: For the case of Fig 14.54(a) the anode is inevitably grounded
Diode SPICE model
Diode SPICE Modeling
Vd I d I s exp 1 GMINV d nV T
BV V d BV I d I s exp 1 VT VT
Convergence Aid
IS (BV/VT)
I d I s GMINV d
MOS physical structure
Thermal Equilibrium •
Absence of any stimulus to the device
•
The populations of electrons and holes are each in equilibrium and, therefore must have zero current densities d 0 dn 0 0n 0 n D n dx dx
Dn 0 0q n 0 n E 0 q D n dx dp0 0q n 0 p E 0 q D p dx D n dn 0 d 0 n n 0
dn0 d 0 V T n0
n 0 x 0 x0 x R V T ln n0 x R
x
x
dn0 d 0V T n 0 x x R
R
Thermal Equilibrium
n 0 x 0 x0 x R V T ln n0 x R
By convention the reference for the potential is chosen to be the point where the carrier concentration is the intrinsic concentration
n 0 x 0 xV T ln ni
0 x R 0
n 0 xn i e
when n 0 x R ni
0 x VT
NOTE: for N type silicon since n0 > ni the electrostatic potential at equilibrium is positive
Thermal Equilibrium A similar derivation for the hole concentration leads to the following result:
p0 x 0 xV T ln ni
p 0 xn i e
0 x VT
NOTE: for P type silicon since p0 > ni the electrostatic potential at equilibrium is negative
MOS Capacitor in Thermal Equilibrium At equilibrium the psubstrate and the n+ source and drain form a pn junction. Therefore a depletion region exists between the n+ source and drain and the p- substrate
Since source and drain are separated by back-toback junctions, the resistance between the source and the drain is very high (> 1012 ohm) gate
source/drain/bulk
Figure. Using the MOSFET as a capacitor
The gate and the substrate of the MOS transistor form a parallel plate capacitor with the SiO2 as dielectric
MOS structure in Thermal Equilibrium VGB = 0
n+ p
equilibrium potential in the polysilicon (gate)
NA equilibrium potential in pV T ln ni the silicon (bulk=substrate) 17
N A10 cm
-3
19
-3
N D 310 cm
10
n i 10 cm
-3
E0
n + V T ln
ND ni
n+ p550 mV 420 mV 970 mV
MOS in Thermal Equilibrium VGB = 0
n+ p970 mV
E0
•
From the sign of the potential drop across the MOS structure it follows that the electric field points from gate to bulk.
•
Therefore, a positive charge must be present on the polysilicon gate and there must be a balancing negative charge in the p-type silicon substrate (the oxide will be considered a charge-free perfect insulator)
Charge on the MOS in TE • Since the gate is highly conductive n+ polysilicon the gate charge QG0 can be thought as a sheet charge located at the bottom surface of the polysilicon gate • The charge on the p-type silicon substrate QB0 is formed by the immobile negatively charged acceptor ions (to a depletion depth of Xd0 ) left behind by the mobile holes repelled by the positive charge on the gate. VGB = 0 0 0
M O
S
Charge on the MOS in TE VGB = 0
G0 B0q N A X d0 units : C cm2
Potential across the MOS in TE Surface Potential Potential at the SiO2-silicon interface (x=0)
Voltage drop across the oxide
M
Built in Voltage across the MOS structure
O
S
BUILT-IN n+ p
Voltage drop across the depletion region In the silicon
V ox , 0 V B , 0
Potential across the MOS in TE •
The equilibrium potential of a given material is commonly referred as its Fermi potential n+
•
ND F-gate V T ln ni
NA p F-bulk V T ln ni
The Built in voltage across the MOS structure is often expressed in term of the work function between the gate material and the bulk silicon MS F-gateF-bulk n+ p BUILT-IN V T ln
NDNA n 2i
NOTE: This term is referred as the metal-to-silicon work function even though the gate terminal is something other than metal (i.e. polysilicon)
MOS in TE: “fixing” KVL VGB = 0
mn+ V ox ,0 V B0 pm 0
V ox ,0 V B0 mn+ pm
n+ p BUILT-IN
MOS in TE
NOTE: for the case of TE the gate and the bulk metal contacts are at the same potential
n+ p mn+ pm
MOS in TE: Quantitative Analysis The total excess charge in the region tox x Xd0 is zero (neutrality of charge) The electric field is confined in the region tox < x < Xd0
E ox +
E 0
In the oxide (tox < x < 0) the charge density is zero thus the field is constant (Eox): 0
Gauss ' s Law :
dE dx
Boundary condition at the oxide/silicon interface (0 x 0+):
oxE ox sE 0+ E 0 +
ox E ox E ox E 0 + s s ox
3
MOS in TE: Quantitative Analysis E ox Within the same material the electric field will not jump !
In the charged region of the silicon oxide/silicon interface (0+ x < Xd0) the charge density is constant:
dE x
q N A dx s
E X do
X do
dE x
E 0+
0
s E X d0 s E 0 q N A X d0 +
E ox E 0 - E 0 +
q N A dx s 0+ q NA E 0 X d0 s
s q N A X d0 ox ox
+
MOS in TE: Quantitative Analysis E ox Within the same material the electric field will not jump !
•
Just for the sake of double-checking the correctness of the previous result let's also apply the boundary condition at the interface between gate and oxide and see if we get the same result G B q N A X d0 GE t ox G ox E t E t ox ox ox -
+ ox
+ ox
E ox
MOS Potential in TE E ox
d 0 x E 0 x dx s0 0 0
MOS in TE: Potential in the oxide M
O
S
d 0 x E 0 x dx
s0 0 0
t ox x0 : x
0 x n+
q N A X d0 x q N A X d0 E ox dx dx xt ox ox t ox t ox
ox
Potential in the oxide
for t ox x0 :
0 x n+
q N A X d0 xt ox ox
MOS in TE: Potential in the oxide M O
S
Potential in the oxide
s0 0 0
for t ox x0 : 0 x n+
q N A X d0 xt ox ox
Surface Potential (Potential at the oxide/silicon interface)
s0 0 0 n+
q N A X d0 q N A X d0 t ox n+ ox ox
with
ox ox t ox
Voltage drop across the oxide
V ox ,0 0 t ox 0 0 n+ s0
q N A X d0 G0 ox ox
with : G0 B0q N A X do
NOTE: VOX,0 is proportional to the charge stored on each side of the oxide
MOS in TE: potential in the depletion region in the silicon substrate M O
S
x dE 0 x dx s
depletion region
0x X d0 : E 0 x
q N A x qN A E 0 xE 0 0 dx s s 0+ x
x
x dE 0 x s E 0+ 0+
+
0
qN A x q N A X d0 qN A x qN A E 0 xE 0 0 X do x s s s s +
+
E 0 0
q N A X d0 s
MOS in TE: potential in the depletion region in the silicon substrate M O
Electric Field in the Depletion region
S
for 0x X d0 : qNA E 0 x X d0 x s
d 0 x E 0 x dx charged region
0x X d0 : 0 x
x
x
qN A 0 x0 0 X do x dx d 0 x E 0 x dx s 0 0 0 x qN A qN A x qN A x2 0 x0 0 X do dx x dx X do x 2 s s 0 s 0 2 qN A x 0 x0 0 X do x s 2 0
MOS in TE: potential in the depletion region in the silicon substrate M O
S Surface Potential
s0 0 0 n+
charged region
0x X d0 :
q N A X d0 ox
2 qN A x 0 x0 0 X do x s 2
Potential in the depletion region in the substrate
for
0 x X d0 :
q N A X d0 0 x n+ ox
qN A x2 X do x 2 s
MOS in TE: potential in the depletion region in the silicon substrate M O
S
Potential in the depletion region in the substrate
for
0 x X d0 : q N A X d0 qN A x2 0 x n+ X do x ox s 2
charged region
q N A X d0 qN A 2 0 X d0 p n+ X do ox 2 s
Voltage drop across the MOS structure
n+ p
q N A X d0 qN A 2 X do ox 2 s
Since this is the voltage drop across the oxide
V ox , 0
This must be the voltage drop across the charged region of the silicon substrate
V B 0
MOS in TE: Width of the Depletion region M O
S
Voltage drop across the MOS structure
n+ p V ox ,0 V B0
q N A X d0 qN A 2 X do ox 2 s
Voltage drop across the oxide depletion region
q N A X d0 G B V ox ,0 ox ox ox Voltage drop across the charged region of the silicon substrate
qNA 2 V B0 X do 2 s
q N A X d0 qNA 2 X do n+ p 0 2 s ox
q N A 2 s 2 s X X d0 n+ p 0 qNA ox q N A 2 do
2 s 2 s X X d0 n+ p 0 q NA ox 2 do
MOS in TE: Width of the Depletion region 2 s 2 s X X d0 n+ p 0 q N ox A 2 do
b b2 4ac x 2a
ax bxc0 2
NOTE: Xd0 can be only positive
2 s ox 4 2s 2ox 8 s q N An+ p X do 2 2
s 2 2 s ox s ox 2 s q N A n+ p ox
Depletion Width:
s X do ox
2 s 2ox 1 1 n+ p q N A 2s
2 2ox 1 n+ p 1 q N A s
MOS under Bias VGB 0
(FLATBAND) – ACCUMULATION – DEPLETION – (THRESHOLD) INVERSION
Flatband •
We apply a gate to bulk voltage that is opposite to the built-in potential. This special voltage bias is called flat-band voltage V FB BUILT_IN n+.0 p.0 Flat-band Voltage
NOTICE: For an MOS structure with n+ poly-silicon gate and p-type substrate this voltage is negative
mn+
V GB mn+ pmV MOS
V MOS
V GB BUILT-IN V MOS
pm
V GB V FB V MOS
The bulk metal contact is considered fixed n+ n+,0 V GB n+ p n+,0V GB p n+,0p,0 V GB V FB V GB
pp,0
if V GB V FB V MOS 0
Flatband •
In flat-band condition (VGB=VFB) there is no internal voltage drop across the MOS capacitor. n+,0 V GB
The bulk metal contact is considered fixed p = 420 mV
(n+,o = 550 mV) Thermal Equilibrium
Applying VGB = VFB shifts the gate metal contact lower by – 970 mV (=VFB)
Flatband • Since in flat-band condition (VGB=VFB) there is no internal voltage drop across the MOS capacitor, as a result the electric field is zero and the gate charge density is zero Q G V GB V FB 0
