AOZ8006

Ultra-Low Capacitance TVS Diode Array

General Description

Features

The AOZ8006 is a transient voltage suppressor array designed to protect high speed data lines such as HDMI and Gigabit Ethernet from damaging ESD events.

●

ESD protection for high-speed data lines: – IEC 61000-4-2, level 4 (ESD) immunity test – ±15kV (air discharge) and ±8kV (contact discharge) – Human Body Model (HBM) ±15kV

●

Array of surge rated diodes with internal TVS diode

●

Small package saves board space

●

Protects four I/O lines

●

Low capacitance between I/O lines: 0.47pF

●

Low clamping voltage

●

Low operating voltage: 5.0V

This device incorporates eight surge rated, low capacitance steering diodes and a TVS in a single package. During transient conditions, the steering diodes direct the transient to either the positive side of the power supply line or to ground. The AOZ8006 provides a typical line to line capacitance of 0.47pF and low insertion loss up to 2GHz providing greater signal integrity making it ideally suited for HDMI 1.3 applications, such as Digital TVs, DVD players, set-top boxes and mobile computing devices. The AOZ8006 comes in a MSOP-10 package and is rated -40°C to +85°C junction temperature range. The MSOP package features a flow through layout design.

Applications ●

HDMI ports

●

Monitors and flat panel displays

●

Set-top box

●

USB 2.0 power and data line protection

●

Video graphics cards

●

Digital Video Interface (DVI)

●

10/100/1000 Ethernet

●

Notebook computers

Typical Application AOZ8006

AOZ8006

TX2+ TX2-

RX2+ RX2-

TX1+

RX1+ RX1-

TX1HDMI Transmitter TX0+ TX0-

RX0+ RX0-

CLK+ CLK-

CLK+ CLKConnector

HDMI Receiver

Connector

AOZ8006

AOZ8006

Figure 1. HDMI Ports Rev. 2.5 April 2010

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AOZ8006 Ordering Information Part Number

Ambient Temperature Range

Package

Environmental

AOZ8006FIL

-40°C to +85°C

MSOP-10

RoHS Compliant Green Product

AOS Green Products use reduced levels of Halogens, and are also RoHS compliant. Please visit www.aosmd.com/web/quality/rohs_compliant.jsp for additional information.

Pin Configuration CH1

1

10

NC

NC

2

9

CH2

VP

3

8

GND

CH3

4

7

NC

NC

5

6

CH4

MSOP-10 (Top View)

Absolute Maximum Ratings Exceeding the Absolute Maximum ratings may damage the device.

Parameter

Rating

Storage Temperature (TS)

-65°C to +150°C

ESD Rating per IEC61000-4-2, contact(1)

±8kV

ESD Rating per IEC61000-4-2, air(1)

±15kV

ESD Rating per Human Body Model

(2)

±15kV

Notes: 1. IEC 61000-4-2 discharge with CDischarge = 150pF, RDischarge = 330Ω. 2. Human Body Discharge per MIL-STD-883, Method 3015 CDischarge = 100pF, RDischarge = 1.5kΩ.

Maximum Operating Ratings Parameter

Rating

Junction Temperature (TJ)

Rev. 2.5 April 2010

-40°C to +125°C

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AOZ8006 Electrical Characteristics TA = 25°C unless otherwise specified. Specifications in BOLD indicate a temperature range of -40°C to +85°C.

Symbol VRWM

Parameter Reverse Working Voltage

Conditions Between VP and GND

Min. (4)

VBR

Reverse Breakdown Voltage

IT = 1mA, between VP and GND

IR

Reverse Leakage Current

VRWM = 5V, between VP and GND

VF

Diode Forward Voltage

IF = 15mA

VCL

Cj

Units

5.5

V

6.6

V µA

1

V

10.50 -2.00

V V

12.50 -3.50

V V

16.00 -5.50

V V

1.0

1.05

pF

0.47

0.50

pF

VP = 3.3V, VR = 1.65V, f = 1MHz, any I/O pin to Ground

0.75

0.85

pF

VP = 5.0V, VR = 2.5V, f = 1MHz, any I/O pins to ground

0.75

0.85

pF

0.03

pF

0.70

0.85

(5)(6)

Channel Clamp Voltage Positive Transients Negative Transient

IPP = 1A, tp = 100ns, any I/O pin to Ground

Channel Clamp Voltage Positive Transients Negative Transient

IPP = 5A, tp = 100ns, any I/O pin to Ground(5)(6)

Channel Clamp Voltage Positive Transients Negative Transient

IPP = 12A, tp = 100ns, any I/O pin to Ground(5)(6)

Channel Input Capacitance

VR = 0V, f = 1MHz, any I/O pin to Ground(5)

Channel Input Capacitance Matching

Max.

1

VR = 0V, f = 1MHz, between I/O

ΔCj

Typ.

(3)

pins(5)

VR = 0V, f = 1MHz, between I/O pins(5)

Notes: 3. The working peak reverse voltage, VRWM, should be equal to or greater than the DC or continuous peak operating voltage level. 4. VBR is measured at the pulse test current IT. 5. Measurements performed with no external capacitor on VP (pin 3 floating). 6. Measurements performed using a 100ns Transmission Line Pulse (TLP) system.

Rev. 2.5 April 2010

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AOZ8006 Typical Operating Characteristics Clamping Voltage vs. Peak Pulse Current

Forward Voltage vs. Forward Current

(tperiod = 100ns, tr = 1ns)

(tperiod = 100ns, tr = 1ns) 7

14

6

13

Forward Voltage (V)

Clamping Voltage, Vcl (V)

15

12 11 10 9 8 7

5 4 3 2 1

6

0

5 0

2

4 6 8 Peak Pulse Current (A)

10

0

12

2

6 8 10 Forward Current (A)

12

14

Insertion Loss vs. Frequency

Capacitance vs. Reverse Voltage 3

1.5

0 VP = Floating 1

S21 (dB)

Capacitance (pF)

4

VP = 3.3V

VP = Floating -3dB 2,565MHz

-3 -6

0.5 -9 0

-12 0

0.5

1

1.5 2.5 3.5 2 3 Reverse Volts, Vr (V)

4

4.5

5

1

10

100

1,000

10,000

Frequency (MHz)

ESD Clamping 8kV Contact per IEC61000-4-2

Note: Data was taken with a 10X attenuator

Rev. 2.5 April 2010

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AOZ8006 Application Information The AOZ8006 TVS is design to protect four high speed data lines from ESD and transient over-voltage by clamping them to a fixed voltage. When the voltages on the protected lines exceed the limit, the internal steering diode are forward bias will conduct the harmful transient away from the sensitive circuitry. As system frequency increase, printed circuit board layout becomes more complex. A successful high speed board must integrate the device and traces while avoiding signal transmission problems associated with HDMI data speed.

High Speed HDMI PCB Layout Guidelines Printed circuit board layout is the key to achieving the highest level of surge immunity on power and data lines. The location of the protection devices on the PCB is the simplest and most important design rule to follow. The AOZ8006 devices should be located as close as possible to the noise source. The placement of the AOZ8006 devices should be used on all data and power lines that enter or exit the PCB at the I/O connector. In most systems, surge pulses occur on data and power lines that enter the PCB through the I/O connector. Placing the AOZ8006 devices as close as possible to the noise source ensures that a surge voltage will be clamped before the pulse can be coupled into adjacent PCB traces. In addition, the PCB should use the shortest possible traces. A short trace length equates to low impedance, which ensures that the surge energy will be dissipated by the AOZ8006 device. Long signal traces will act as antennas to receive energy from fields that are produced by the ESD pulse. By keeping line lengths as short as possible, the efficiency of the line to act as an antenna for ESD related fields is reduced. Minimize interconnecting line lengths by placing devices with the most interconnect as close together as possible. The protection circuits should shunt the surge voltage to either the reference or chassis ground. Shunting the surge voltage directly to the IC’s signal ground can cause ground bounce. The clamping performance of TVS diodes on a single ground PCB can be improved by minimizing the impedance with relatively short and wide ground traces. The PCB layout and IC package parasitic inductances can cause significant overshoot to the TVS’s clamping voltage. The inductance of the PCB can be reduced by using short trace lengths and multiple layers with separate ground and power planes. One effective method to minimize loop problems is to incorporate a ground plane in the PCB design. The AOZ8006 ultra-low capacitance TVS is designed to protect four high speed data transmission lines from transient over-voltages by clamping them to a fixed refer-

Rev. 2.5 April 2010

ence. The low inductance and construction minimizes voltage overshoot during high current surges. When the voltage on the protected line exceeds the reference voltage the internal steering diodes are forward biased, conducting the transient current away from the sensitive circuitry. The AOZ8006 is designed for the ease of PCB layout by allowing the traces to run underneath the device. The pinout of the AOZ8006 is design to simply drop onto the IO lines of a High Definition Multimedia Interface (HDMI) design without having to divert the signal lines that may add more parasitic inductance. Pins 1, 2, 4 and 5 are connected to the internal TVS devices and pins 6, 7, 9 and 10 are no connects. The no connects was done so the package can be securely soldered onto the PCB surface. See Figure 2. CH 1

CH 1

CH 2

CH 2

VP

GND

CH 3

CH 3

CH 4

CH 4

Figure 2. Flow through Layout for two Line Pair

It is crucial that the layout is successful for a HDMI design PCB board. Some of the problems associated with high speed design are matching impedance of the traces and to minimize the crosstalk between parallel traces. This application note is to provide you as much information to successfully design a high speed PCB using Alpha & Omega devices. The HDMI video signals are transmitted on a very high speed pair of traces and any amount of capacitance, inductance or even bends in a trace can cause the impedance of a differential pair to drop as much as 40Ω. This is not desirable because HDMI ports must maintain a 100Ω ±15% on each of the four pairs of its differential lines per HDMI Compliance Test Specifications. The HDMI CTS specifies that the impedance on the differential pair of a receiver must be measured using a Time Domain Reflectometry method with a pulse rise time of ≤200pS. The TDR measurements of the PCB traces allows to locate and model discontinuities cause by the geometrical features of a bend and by the frequencydependant losses of the trace itself. These fast edge rates can contribute to noise and crosstalk, depending on the traces and PCB dielectric construction material. Material selection is another aspect that determines good characteristic impedance in the lines. Different material will give you different results. The dielectric material will

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AOZ8006 have the dielectric constant (εr). Where Q1, Q2 = charges, r = distance between charges (m), F = force(N), ε = permittivity of dielectric (F/m).

Q1 Q2 F = --------------2 4πεr

(1)

By solving for Zo you can calculate the differential impedance with the equation below. D

– 0.96 ----⎞ ⎛ h Zdiff = 2 × Zo ⎜ 1 – 0.48e ⎟ ⎝ ⎠

(4)

Zdiff = 100.77

Each PCB substrate has a different relative dielectric constant. The dielectric constant is the permittivity of a relative that of empty space. Where εr = dielectric constant, ε = permittivity, and εo = permittivity of empty space.

ε ε r = ----εo

(2)

The dielectric constant affects the impedance of a transmission line and can propagate faster in materials that have a lower εr . The frequency in your design will depend on the material being used. With equation 1 you can determine the type of material to use. If higher frequency is required other board material maybe considered. GETEK is another material that can be used in high speed boards. They have a typical εr between 3.6 to 4.0. The most common type of dielectric material used for PCB is FR-4. Typical dielectric constant for FR-4 is between 4.0 to 4.5. Most PCB manufacture will be able to give you the exact value of the FR-4 dielectric constant. Once you determined the dielectric constant of the board material you can start to calculate the impedance of each trace. Below are the formulas for a microstrip layout. This impedance is dependant on the width of the microstrip (W) the thickness (t) of the trace and the height (h) of the FR4 material, and (D) trace edge to edge spacing. W

D

W

Adjust the trace width, height, distance between the traces and FR4 thickness to obtain the desired 100Ω differential impedance. The general rule of thumb is to route the traces as short as possible, use differential routing strategies whenever feasible and match the length and bends to each of the differential traces. The graphs below show the differential impedance with varying trace width without the AOZ8006 MSOP-10 package part on it. Each of the graphs and board layout represent changing trace width from 50Ω to 80Ω in increment of 10Ω.

Figure 4. 100Ω Differential Impedance Max 103Ω, Min 97Ω

t

Trace

εr

Dielectric Material

H

Ground

Figure 3.

Typical value of W = 12.6 mil, h = 10mils, D = 10mils, t = 1.4mils and εr = 4.0 with the equation below for a microstrip impedance yields:

87 5.98 × h Zo = -------------------------- = ln ⎛ ----------------------⎞ ⎝ 0.8W + t⎠ ε r + 1.41

(3)

Figure 5. 120Ω Differential Impedance Max 110Ω, Min 102Ω

Zo = 61.73Ω

Rev. 2.5 April 2010

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AOZ8006 X

Zo = 61Ω

Zo = 61Ω C(TVS)

Z1

Figure 7.

Figure 6. 140Ω Differential Impedance Max 102Ω, Min 92Ω

Z1 K = -----Z0

(5)

Z 0 C TVS K X = ⎛ ---------------------⎞ ⎛ ----------------⎞ ⎠ ⎝ ⎠⎝ 2 τ K –1

(6)

Z0 is the normal 61Ω differential impedance on the trace. Z1 is the needed impedance to compensate for the added C(TVS) K is defined as the unloaded impedance of the adjusted trace. X is the length of the trace needed for the compensation. τ is the propagation delay time required for a signal to travel from one point to another. This value should be less than 200pS.

Figure 7. 160Ω Differential Impedance Max 123Ω, Min 109Ω

Differentail Impedance (Ω)

140 120

From the above method the designer should layout the boards with a 50Ω common mode trace. The result should give you approximately 100Ω differential impedance. Z1 is the impedance that you choose in order to compensate the TVS capacitance. Based on Z1 value, we can get the length of the segment from the above equations. With the value of Z1 = 80Ω, Zo = 61Ω, C(TVS) = 0.94 and τ = 180. The X(mils) equates to 580 mils.

Max.

100 Min.

80 60 40 20 0 50

55

60

65

70

75

80

Common Mode Impedance (Ω)

Figure 8. Differential Impedance

By adding a TVS onto the traces it can have a large effect on the impedance of the line. This addition of a capacitance added to a 100Ω differential transmission line without any compensation may decrease the impedance as much as 20Ω or more. Below is a formula to calculate the length for the compensation of C(TVS).

Rev. 2.5 April 2010

Page 8 has a series of graph that represent changing width and length of the trace from 50Ω to 80Ω in increment of 10Ω with a MSOP-10 package solder onto the board. As you can observe from the graphs, a small incremental capacitance that is added to the differential lines can significantly decrease the differential impedance. Thus violated the HDMI specification of 100Ω±15%.

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AOZ8006

Figure 10. 100Ω Differential Impedance with AOZ8006 MSOP-10 Package on it Max. 97Ω, Min. 80Ω

Figure 12. 140Ω Differential Impedance with AOZ8006 MSOP-10 Package on it Max. 102Ω, Min. 92Ω

Figure 11. 120Ω Differential Impedance with AOZ8006 MSOP-10 Package on it Max. 99Ω, Min. 86Ω

Figure 13. 160Ω Differential Impedance with AOZ8006 MSOP-10 Package on it Max. 101Ω, Min. 95Ω

From Figure 13 we are able to get the best result from using all of the equation above. With the value of Z1 = 80Ω, Z0 = 61Ω, C(TVS) = 0.94, τ = 180 and from Table 1. The X(mils) equates to 580mils to give the best compensated differential impedance on the traces for the added capacitance from the AOZ8006.

Rev. 2.5 April 2010

Table 1. AOZ8006 MSOP-10 HDMI Evaluation Board Specification Number of layers

4

Copper Trace Thickness

1.4 mils

Dielectric Constant εr

4

Overall Board Thickness

62 mils

Dielectric thickness between top and ground layer

10 mils

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AOZ8006 Conclusion This application section discusses ESD protection while maintaining the differential impedance of a HMDI sink device. Since the TVS add capacitance we must design the board to meet the HDMI requirements. This application note is a guideline to calculate and layout the PCB. Different board manufacture and process will fluctuate and will cause the final board to vary slightly. You must carefully plan out a successful high speed HDMI PCB. Factor such as PCB stack up, ground bounce, crosstalk and signal reflection can interfere with a signal. The layout, trace routing, board materials and impedance calculation discussed in this application note can help you design a more effective PCB using the AOZ8006 devices.

100Ω Differential

132Ω Differential

580 mils

Figure 14. Recommend Layout for MSOP-10 Package

Rev. 2.5 April 2010

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AOZ8006 Package Dimensions, MSOP-10L Gauge Plane

Seating Plane 0.25

C L

E1

E

D

12°(4x)

A2 A

b

e

RECOMMENDED LAND PATTERN

0.76

0.30

4.37

0.50

UNIT: mm

A1

Dimensions in millimeters

Dimensions in inches

Symbols A

Min. 0.81

Nom. 1.02

Max. 1.12

Symbols A

A1 A2 b C D E E1 e L y

0.05 0.76 0.15 0.13 2.90 4.70 2.90 — 0.40 —

— 0.86 0.20 0.15 3.00 4.90 3.00 0.50 0.53 —

0.15 0.97 0.30 0.23 3.10 5.10 3.10 — 0.66 0.10

A1 A2 b C D E E1 e L y

θ

0°

—

6°

θ

Min. 0.032

Nom. 0.040

Max. 0.044

0.002 — 0.006 0.030 0.034 0.038 0.006 0.008 0.012 0.005 0.006 0.009 0.114 0.118 0.122 0.185 0.193 0.201 0.114 0.118 0.122 — 0.0197 — 0.016 0.021 0.026 — — 0.004 0°

—

6°

Notes: 1. All dimensions are in millimeters. 2. Tolerance 0.10mm unless otherwise specified. 3. Package body sizes exclude mold flash and gate burrs. Mold flash at the non-lead sides should be less than 5 mils each. 4. Dimension L is measured in gauge plane. 5. Controlling dimension is millimeter, converted inch dimensions are not necessarily exact.

Rev. 2.5 April 2010

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AOZ8006 Part Marking AOZ8006FIL (MSOP-10)

Product Name Extension Character

8006 I0YW P11

Part Number Code Week Code Year Code Assembly Lot Code

Option Code

Assembly Location Code

This datasheet contains preliminary data; supplementary data may be published at a later date. Alpha & Omega Semiconductor reserves the right to make changes at any time without notice. LIFE SUPPORT POLICY ALPHA & OMEGA SEMICONDUCTOR PRODUCTS ARE NOT AUTHORIZED FOR USE AS CRITICAL COMPONENTS IN LIFE SUPPORT DEVICES OR SYSTEMS. As used herein: 1. Life support devices or systems are devices or systems which, (a) are intended for surgical implant into the body or (b) support or sustain life, and (c) whose failure to perform when properly used in accordance with instructions for use provided in the labeling, can be reasonably expected to result in a significant injury of the user.

Rev. 2.5 April 2010

2. A critical component in any component of a life support, device, or system whose failure to perform can be reasonably expected to cause the failure of the life support device or system, or to affect its safety or effectiveness.

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