ASE Material Company Profile
June 2005
Overview ASE Material
• Operation began in July 1995
Vision
• To be the best semiconductor packaging material (Lead Frame & BGA substrate) manufacturer in the world
Products
• Buildup FC substrate • BGA series substrate • Etched Lead Frames
Plant floor
• Kaohsiung：29,000 m2 • Chung Li： 94,000 m2 (under re-installation) • Shanghai:
Manpower
84,500 m2 (Ready )
• Kaohsiung, Taiwan：1,400 • Chung-Li, Taiwan ： 100 • Shanghai, China
：1,700 (2,300 in Q4/05)
Development Milestones 1995
Started Etched Leadframe Production
1998
Started BGA/LBGA/TFBGA substrate Production
1999
ISO-9002 Certified
2000
ISO-14001 Certified
2002
QS-9000 Certified
2002
Started GPP (Gold Pattern Plating) Production
2003
Started Flip-Chip Build Up substrate Production
2003
TS 16949 Certified
2004
ASESH ISO-9002 Certified
2005 Transfer 450 technical persons from CL to SH.
ASEMTL 2004 Market Share
Source: Prismark Feb. 2005
Plant Location 1 K9 (First ASE material manufacturing facility)
Taipei Chung-Li K11– Assembly, Test and Material
Hsin-Chu
T A I W A N
Address: 73, Kai-Fa Road, Nantze Export Processing Zone, Kaohsiung, Taiwan, ROC Close to Kaohsiung International Airport (30 minutes to drive)
Kaohsiung Kaohsiung International Airport
Plant Location 2 A-building destroyed in a fire incidence on 2005/05/01 Recovery in B-Building, will start running in Nov. 2005
CKS International Airport Taipei
Chung-Li Hsin-Chu Science Park
T A I W A N Kaohsiung
Address: 550, Chung-Hwa Rd Section 1, Chung-Li, Taiwan, ROC Close to Hsin-Chu Science Park (1Hour) and CKS International Airport (30 minutes to drive)
Plant Location 3
ASE Shanghai
Address: 599 Li Shi Zhen Rd, Zhang Jiang HiTech Park, Pudong New Area, Shanghai 201203, P.R.C. Close to Pu Dong International Airport (30 minutes to drive)
Business Area Business Area : Organic substrate and etched leadframe for IC packaging and module assembly. Product Offerings : a. 1,2,4 & 6 layers substrate for BOC/BGA/CSP/Modules b. Up to 4+N+4 buildup flip chip substrate c. High Density Interconnection solution with laser via and fine pitch capability d. High electrical performance solution with buildup and stubless solution
Laminate Expansion Plan
Unit: M Pcs/Month 50% 2L and 50% 4L, equivalent to 27x27mm.
Substrate Technology & Product introduction
Stone Shih 07/14/2005
Introduction - Illustration of Flip Chip Packages Die Solder Bump Underfill Substrate Solder Ball
Introduction-Cross section of PBGA
Overall Thickness
Cap Thickness
Substrate Thickness ball height ball diameter
Ball pitch
PBGA Process Flow(I) Wafer Substrate Wafer Grinding Wafer Mount Wafer Saw 2nd Optical Gate
Die (chip)
Die Attach
Epoxy Cure
Conductive epoxy Die
Substrate
Plasma Clean Gold Wire Wire Bond Die 3rd Optical Gate
PBGA Process Flow(II) Plasma Clean II
Molding
Post Mold Care
Marking Solder Ball Ball Mount
Singulation
Scan & Final Visual
Packing Raw Substrate
After Die Attached After Molding
After Ball Attached
ASE Package Offerings in Sweet-spot 4C Products
IC Shipments By Package Category
Source: Prismark 2004
ASE Packaging Technologies Keep Pace With IC Miniaturization IC
0.13
Feature Size (nm)
0.09 0.065
Packaging
250
F/C
200 150
Pitch (µm)
# of Interconnects
Substrate L/S (µm/ µm)
45
W/B
2000
Bump Count
1500
Ball Count
30+/30+
40
3000 2000
25/25
35 5000 3000
20-/208+
Layer Count
Green Technology
6
2
Pb-Free
Halogen-Free
ASE BU Substrate Technology Ahead of Industry Line Width/Space 35 µm
ITRS* 30 µm
25 µm
20 µm
ASE Capability Top Width
15 µm
Space
Pitch
2002 * 2003 ITRS Roadmap
2003
2004
2005
One-Stop Shopping @ ASE Module, Board Assembly & Test (DMS) Final Test IC Assembly
Foundry
Circuit Design
Engineering Test
Wafer Bumping/Probing
Substrates
ASEmtl KH CL SH
Concurrent Engineering of Mixed Technologies: Design Optimization Customer
Tape Out
Wafer Out
Wafer Fab
ASE Bumping
ASE Assy.
ASE Mtl.
ASE Test
Bump Mask Design
Package Customer Design Approval
Review
Program Engineering
Bumping/Probing
Tooling/Kit Preparation
Package Assembly
Substrate Fabrication
Probe Card, Load & Burn-in Board Mfg.
F/T
Product introduction
Stone Shih 07/14/2005
Technology Deployment Market Requirement
Product
Substrate Technology Solution Flip Chip substrate
Build up 4+N+4
E/P R,L,C
RF/PA Cavity Down BGA
Normal
PBGA /LFBGA
Build up BT/NX,E679FG
Material
Design / New process
Green Material
High Density
AUS308 Micro Via Fine Pitch OSP
Metal finish
Electroless Ni/Au Electrical Ni/Au Pre-Solder
Pattern Plating SAP Etch Back GPP/Selective gold
FC Substrate product
Small size – Smaller IC footprint, reduced height and weight. Improved performance – Short interconnect delivers low inductance, resistance and capacitance, small electrical delays, good high frequency characteristics. Increased functionality – The use fo flip chips allow an increase in the number of I/O. An area array pad layout enables more signal, power and ground connections in less space.
W/B Substrate product
PBGA substrate provides the interconnection platform with the circuit board for assembly package. It could protect and support the ICs with thermal enhancement.
W/B Cavity down Substrate product
Heat Sink
Heat Sink
Cavity-down BGA enhance thermal performance by about 15~20% when compared to 4-layer PBGA and by 35% when compared to the 2-layer PBGA.
Embedded Substrate product
Capping Full via copper
Embedded Capacitor
Spec. Electrode Dielectric
A. Preprint Thickness 5+/-2um. B. Dielectric 1
16.5+/-3.5um.
C. Middle Electrode D. Dielectric 2 E. Top Electrode
5+/-2um.
16.5+/-3.5um. 5+/-2um.
Technology Deployment Market Requirement
Product
Substrate Technology Solution Flip Chip substrate
Build up 4+N+4
E/P R,L,C
RF/PA Cavity Down BGA
Normal
PBGA /LFBGA
Build up BT/NX,E679FG
Material
Design / New process
Green Material
High Density
AUS308 Micro Via Fine Pitch OSP
Metal finish
Electroless Ni/Au Electrical Ni/Au Pre-Solder
Pattern Plating SAP Etch Back GPP/Selective gold
FC FCSubstrate SubstrateProcess ProcessFlow Flow(2+2+2) (2+2+2)
•Inner Layer [ 3rd & 4th Layers] •1st Build-up [2nd & 5th Layers] •2nd Build-up [1st & 6th Layers] •SR create [Solder Resist] •Backend [Pre-solder / SOP]
Inner Layer [3
rd
& 4th layers]
Issue IssueofofMaterial Material
Utilize Utilizethe thevertical verticalbaking bakingmethod methodtoto release the mechanical stress release the mechanical stressand and increase increasethe thepanel paneldimension dimension
Thin ThinCu CuEtching EtchingI I
Reduce Reducethe thethickness thicknessofofcopper copperby by etching etchingline. line.
Mechanical MechanicalDrilling Drilling
Create Createconnecting connectingchannels channelsbetween between mental mentallayers layersby byusing usingmechanical mechanical drilling drillingmachine. machine.
Plating PlatingThrough ThroughHole Hole(PTH) (PTH)
Enabling Enablinghole holewall walltotoconnect connect conducting metal between conducting metal betweenlayers. layers. [sub-process: [sub-process:Desmear, Desmear,E’less E’lessCu Cu&& Cu Plating] Cu Plating]
Plugging PluggingPretreatment Pretreatment
Roughening Rougheningthe thecopper coppersurface surface inorder inordertotoincrease increasethe theadhesions adhesionsininbetween ink fluid and hole wall. between ink fluid and hole wall.
Ink InkPlugging Plugging
Fulfill Fulfillthe thePTH PTHvacancy vacancytotoavoid avoidthe the shape shapedistortion, distortion,collapsing collapsingand and oxidation. oxidation.[sub-process: [sub-process:plugging pluggingand and baking] baking]
Grinding GrindingI I
Grind Grindoff offthe theprotrusion protrusionofofink inkfluid fluidby by non-woven buff. non-woven buff.
Thin ThinCu CuEtching EtchingIIII
Reduce Reducethe thethickness thicknessofofcopper copperby by etching etchingline. line.
Grinding GrindingIIII
Grind Grindoff offthe theprotrusion protrusionofofink inkfluid fluidby by non-woven buff again non-woven buff again
Etch EtchResist ResistLamination Lamination
Treat Treatlaminate laminatewith withsome somepre-treating pre-treatingchemical chemicaltoto make makethe thecopper coppersurface surfaceready readyfor forresist resistcoating. coating. [sub-process: pretreatment and lamination] [sub-process: pretreatment and lamination]
Lid LidPlating Plating
Enhance Enhancethe thereliability reliabilityofofthe thesubstrate substrateby byadding adding copper cap, also it is designed for the stagger copper cap, also it is designed for the staggervia via and andstacked stackedvia viaon onPTH PTHstructure. structure.[sub-process: [sub-process: Desmear, Desmear,E’less E’lessCu Cu&&Cu CuPlating] Plating]
Exposure Exposure
Using Usingplotted plottedartwork artworkfilm filmand andUV UVexposure exposuremachine machine tototransfer the pattern image from artwork to boards. transfer the pattern image from artwork to boards.
Developing Developing
The Thepattern patternshape shaperesist resistwill willform formfirst firstafter after developing, developing,leaving leavingcopper coppertotobe beremoved removedexposed exposed on non-exposure areas. on non-exposure areas.
Pattern PatternEtching Etching
Acid Acidchemistry chemistryused usedtotoetch etchthe thecopper copperininareas areas where the photoresist has been developed. where the photoresist has been developed. Removal Removalofofbase basecopper copperfrom fromthe theinnerlayer. innerlayer.
1st Build-up [2
nd
& 5th layers]
Lamination LaminationPretreatment Pretreatment
Cleaning Cleaningand androughening rougheningthe thecopper coppersurface surface used usedby byacid/alkaline acid/alkalinechemistry chemistryagent agentfor forvacuum vacuum lamination preparation. lamination preparation.
Vacuum VacuumLamination Lamination
The Theapplication applicationofofABF ABFtotoaaprinted printedcircuit circuit pattern through the use of heat, pressure pattern through the use of heat, pressureand and time.[sub-process: time.[sub-process:lamination laminationand andbaking] baking]
Laser LaserDrilling Drilling
Drill Drillmicrovias microviasbarrel barrelon onthe theABF ABFsurface surfaceby by the theLaser Laserradiation radiationdrilling drillingtechnique techniquetotocreate create connecting connectingchannels channelsinbetween inbetweenthe thedielectric dielectric with withcopper copperarea. area.
Desmear Desmear
The Theremoval removalofofsmeared smearedepoxy-resin epoxy-resinfrom from copper coppersurfaces surfaceswithin withinthe themicrovia microviabarrel barrel totofacilitate facilitateaaconnection connectionwith withplated plated copper. copper.
Electro-less Electro-lessCu Cu
The Thechemistry chemistryused usedtotodeposit deposit copper onto the flat areas copper onto the flat areasand and inside insidethe thedrilled drilledholes holesoften often outlayer outlayerpanel. panel.
Dry-film Dry-filmLamination Lamination
The Theprocess processofofcovering coveringaacircuit circuitpattern pattern with withaathin thinlayer layerofofdry dryfilm filmphotoresist. photoresist. [sub-process: [sub-process:pretreatment pretreatmentand and lamination] lamination]
Exposure Exposure
Using Usingplotted plottedartwork artworkfilm filmand andUV UV exposure machine to transfer the exposure machine to transfer thepattern pattern image imagefrom fromartwork artworktotoboards. boards.
Developing Developing
The Theprocess processininwhich whichthe theunpolymerized unpolymerized phtoresist phtoresistisisremoved removedfrom fromthe thecopper copper surface. surface.
Electrolytic ElectrolyticCu CuPlating Plating
The Thecopper copperand andtin tinplating platingmethod methodusing using an electrical current. an electrical current.
Dry-film Dry-filmStripping Stripping
Strip Stripoff offallallofofthe theetching etchingresist resist remaining (ie. dry film) and remaining (ie. dry film) andleave leavethe the copper coppercircuit circuitpattern patternonly. only.
Etching Etching
Removal Removalofofbase basecopper copperthrough throughthe the etching line. etching line.
2nd Build-up [1
st
& 6th layers]
Lamination LaminationPretreatment Pretreatment
Cleaning Cleaningand androughening rougheningthe thecopper coppersurface surface used by acid/alkaline chemistry agent for used by acid/alkaline chemistry agent forvacuum vacuumlamination lamination preparation. preparation.
Vacuum VacuumLamination Lamination
The Theapplication applicationofofABF ABFtotoaaprinted printedcircuit circuitpattern patternthrough throughthe the use useofofheat, heat,pressure pressureand andtime. time. [sub-process: [sub-process:lamination laminationand andbaking] baking]
Laser LaserDrilling Drilling
Drill Drillmicrovias microviasbarrel barrelon onthe theABF ABFsurface surfaceby bythe theLaser Laser radiation radiationdrilling drillingtechnique techniquetotocreate createconnecting connectingchannels channels inbetween inbetweenthe thedielectric dielectricwith withcopper copperarea. area.
Desmear Desmear
The Theremoval removalofofsmeared smearedepoxy-resin epoxy-resinfrom fromcopper coppersurfaces surfaces within the microvia barrel to facilitate a connection with within the microvia barrel to facilitate a connection withplated plated copper. copper.
Electro-less Electro-lessCu Cu
The Thechemistry chemistryused usedtotodeposit depositcopper copperonto onto the flat areas and inside the drilled holes the flat areas and inside the drilled holes often oftenoutlayer outlayerpanel. panel.
Dry-film Dry-filmLamination Lamination
The Theprocess processofofcovering coveringaacircuit circuitpattern patternwith withaa thin layer of dry film photoresist. thin layer of dry film photoresist. [sub-process: [sub-process:pretreatment pretreatmentand andlamination] lamination]
Exposure Exposure
Using Usingplotted plottedartwork artworkfilm filmand andUV UVexposure exposure machine machinetototransfer transferthe thepattern patternimage imagefrom from artwork to boards. artwork to boards.
Developing Developing
The Theprocess processininwhich whichthe theunpolymerized unpolymerized phtoresist phtoresistisisremoved removedfrom fromthe thecopper coppersurface. surface.
Electrolytic ElectrolyticCu CuPlating Plating
The Thecopper copperand andtin tinplating platingmethod methodusing usingan an electrical electricalcurrent. current.
Dry-film Dry-filmStripping Stripping
Strip Stripoff offallallofofthe theetching etchingresist resistremaining remaining(ie. (ie. dry film) and leave the copper circuit pattern dry film) and leave the copper circuit pattern only. only.
Etching Etching
Removal Removalofofbase basecopper copperthrough throughthe theetching etching line. line.
SR Create Solder SolderMask MaskPrinting Printing
AApolymeric polymericnon-conductive non-conductivecoating coatingapplied appliedtotothe thesurface surfaceofofaacircuit circuitboard board totoprotect the circuit traces and laminate surface. protect the circuit traces and laminate surface.
Exposure Exposure
Using Usingplotted plottedartwork artworkfilm film[ie. [ie.dry dryfilm] film]and andUV UVexposure exposuremachine machinetototransfer transfer the solder mask opening image from artwork to boards. the solder mask opening image from artwork to boards.
Developing Developing
Create Createthe theopenings openingson onsolder soldermask masksurface. surface.
Post-baking Post-baking
The Thefinal finalstep stepininthe theapplication applicationofofsolder soldermask maskisiscuring, curing, whether whetherby byhear hearororby byultraviolet ultravioletlight. light.[sub-process: [sub-process:postpostbaking, baking, UV UVcuring, curing,Plasma] Plasma]
Backend
De-panel De-panel
Cutting Cuttingaapenal penalinto into1/4 1/4multipack. multipack. [sub-process: routing and [sub-process: routing andpost-cleaning] post-cleaning]
OSP OSP
Deposit Depositthe theorganic organicsolderability solderabilitypreservative preservativeon onthe thecopper copper surface surfaceofofsolder soldermask maskopenings openingsininorder ordertotoprevent prevent oxidation oxidationoccuring. occuring.[sub-process: [sub-process:Preclean, Preclean,Cu Cuetching, etching, OSP] OSP]
Bump BumpPrinting Printing
Print Printthe theeutectic eutecticsolder solderbump bumpcream creaminto intoeach eachsolder soldermask mask openings. openings.
Solder SolderReflow Reflow
Utilize solder reflow chamber with temperature profiles to Utilize solder reflow chamber with temperature profiles to consolidate consolidatethe theeutectic eutecticsolder solderbump bumpcream creaminto intosolder solderballs. balls.
Deflux Deflux
Remove the residues of flux the remained on the solder mask Remove the residues of flux the remained on the solder mask after aftersolder solderreflow. reflow.
Singulation Singulation
Saw Saweach eachmulti-pack multi-packinto intoaasingle singleunit. unit.
Coining Coining
Create Createco-planarity co-planarityofofsolder solderbump bumpby bythe thebump bumpcoining coiningmachine. machine.
O/S O/Stest test
Test Testthe theelectric electriccurrent currenttotofind findwhether whetheraacircuit circuittrace tracehas hasaa blockage blockageororlose losean anelectrical electricalsignal signalacross acrossthe theentire entirewidth widthofof the circuit the circuit
Process Process::Micro Microvia/ via/Build Buildup up Laser drill and Mechanical drill 30~100um 50~100um
Process SAP(Semi Additive Process::Fine Finepitch pitch––SAP(Semi AdditiveProcess) Process) Top Width
Space
Tenting process: Line/Space = 35um/35um
Pitch
SAP :Line/Space = 15um/15um
Process -less (Etching Process::Stub Stub-less (EtchingBack/GPP/SG) Back/GPP/SG) Plating Bar - Less Design Routable - Cross-Talk (RF Concern) - O/S can’t be applied
Etching Back
- Plating Buss Still Need in Design - Still Stub Residual - O/S can be applied
GPP( Gold Pattern Plating) - Really Stubless, Design Routable - Good Electrical Performance - O/S can be applied
Process Process::GPP(Gold GPP(GoldPattern Patternplating) plating) /SG /SG(Selective (SelectiveGold GoldProcess) Process) Characteristic 1.Stub-less Design (Reduce noise scattering from platting trace) 2.High IO Density 3.High Reliability (Reduce adhesion problem between SM with Au surface )
Etching Back
GPP
Selective Gold
Process Process::Metal Metalfinish finish ENIG ENIG/ /ENAG ENAG • What is ENIG: Electroless Nickel Immersion Gold
• What is ENAG: Electroless Nickel Autocatalytic Gold
• Advantage: (+) No need plating bar. (+) Can match the wire bonding requirement. (+) Equipment cost is inexpensive.
• Shortcoming: (-) Poor solder joint strength. (Sn/Ag/Cu) (-) Few suppliers for supporting. (-) Difficult control for autocatalytic gold tank. (-) Chemical cost is expensive.
Process -solder Process::Pre Pre-solder
150um Bump Pitch
OSP coating
Process Process::Metal Metalfinish finish OSP/AFOP OSP/AFOP OSP: Organic Solderability Preservatives AFOP substrate: Au on Finger, OSP on
Pad.
Structure Normal PBGA
AFOP Substrate Ni/Au on Finger
Ni/Au on Finger/Pad
OSP on ball pad
S/M
Normal Substrate (+) Normal process flow (+) Not ball pad oxidation concern (-) Poor solder joint strength (SnAgCu) (-) Missing ball (SnAgCu)
AFOP Substrate (+) High solder joint strength (+) Longer fatigue life for solder join (-) Unable to measure OSP THK (-) Tighten control of WIP
Thank you !! Q&A
