Analog to Digital conversion and Pulse Code Modulation

Milwaukee Area Technical College Digital Communications ELCTEC 158-200S

Submitted by: Jody Decker Submitted on: 05/07/09 Performed on: 04/28/09

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INTRODUCTION In this lab several devices are used to create a circuit to convert an analog signal into a serial stream of bits. The process of is carried out in a series of steps that are coordinated by a counter, (two) one shot triggers, and some digital logic. The main steps are (see Fig. 1 to 4): sampling of the analog signal (at the switch), converting that sample to an 8-bit binary number (Analog to Digital Converter), and serializing that 8-bit number to a timed stream of bits (multiplexer).

Fig. 1 – input signal

Fig.2 – sampled input signal

Fig. 3 – Analog to Digital conversion

Fig. 4 – serializing data

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Fig. 5 - schematic for PCM encoder

+5VDC Master Clock RA 1kOhm

U1

5 4 6 2 8 C1 .1uF +5VDC

DSCHG

OUT

3

CV RST THR TRG VCC LM555

GND

7

1

RB ~38kOhm

Fig 5.1 - LM555 Master Clock Circuit

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EXPLANATION OF OPERATION First, the analog signal is applied to the input of the 4066 switch (U1) and is sampled at regular intervals in order to measure the magnitude of the waveform at discrete points in time. The process is called Pulse Amplitude Modulation (PAM) and the resulting signal can be seen at the top of the scope capture in Fig. 8, (pg. 6). The switch is activated for a 5mS window during each 50mS cycle and during this time the sample voltage is present at the input to the analog to digital converter U2 (ADC0804). The ADC conversion is initiated by a low to high transition on the ADC’s WR pin, which takes the magnitude of the sample’s voltage and converts it to an 8 bit binary number. Then when the R D pin is brought low the 8 bit binary number can be read on the output pins of the ADC. The ADC clock speed is around 77kHz, which makes the conversion happen very quickly relative to the timing in the rest of the circuit. (One ADC clock cycle equals 12.99uS. It takes 64 ADC clock cycles to finish one conversion, which comes to about .83mS conversion time. See Fig. 10, pg.7) The sequence of events in the circuit is controlled mainly by the counter U7 (74193), which is clocked by a 555 master clock. The counter controls the order and timing of the bits that are output from the multiplexer. The count sequence also controls when the one shots are triggered, and the length of the entire sequence. The same count that the resets the counter (1010), triggers the one shots. In order for that count to stay on long enough to trigger the one shots, the resetting of the counter is delayed slightly by the four inverter gates U5 (see Fig. 9, pg.6). Once the ADC output is enabled, the data from the ADC is available to the multiplexer U6 (74150). Each count from 0-7 selects one of the multiplexers input pins, which will then be seen at the output (also, the outputs from the multiplexer are inverted relative to the inputs [0=1]). This places the individual bits 0 through 7 in a particular place in time for each cycle (See Fig. 7, multiplexer out, pg.5). For counts 8 and 9, the one shot control signals produce a 1,0 bit pattern at the beginning/end of each cycle. These extra bits are the framing bits and are used to transfer the clock information to the device receiving the data. The sequence of events and control timing is shown in Fig. 6.

Fig.6 – Timing Diagram

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PROCEDURE SETTING UP AND RUNNING THE CIRCUIT The Master clock for the circuit is a 555 timer (Fig. 5.1) set up for astable operation and a duty cycle near 50 percent. A 1k Ohm resistor (RA) and .1uF capacitor were chosen for the circuit based information found in the datasheet. 1k Ohm was used for RA because that is the minimum recommended resistance, and is necessary to get as close as possible to a 50 percent duty cycle. RB was calculated to be near 36kOhms as shown…. 1 1 = = 5mS f 200 Hz D ( Duty cycle) = .51, t1 = D × T = .51× 5mS = 2.55mS f = 200 Hz , T =

RB =

t1 2.55mS − RA = − 1kΩ = 35.8kΩ (.693 × C ) (.693 × .1µF )

These values are estimates only; the timer frequency is adjusted to 200Hz by using a variable resistance for RB. Once the master clock is set, the one shot triggers U4 and U3 can be set up (in that order). The one shots need to be set so that when triggered, they stay on for 45mS. On is when the state of the Q pins are opposite of what they are labeled (when Q is high). U1 and U2 (the switch and ADC) were originally set up during a previous lab assignment and when tested, there was a lot of noise on the input to the ADC (Fig. 11 pg. 8). The source of the noise was found to be the clock of the ADC, which is around 77kHz. In order to filter out this noise, a capacitor was placed from the ADC input to ground to create a simple low pass filter. The size of the capacitor was determined as follows…. f C = 10kHz, RT = 5kΩ (the (2) 10kΩ resistors in parallel ) C=

1 1 = = 3.18nF 2π ⋅ f C ⋅ RT 2π ⋅10kHz ⋅ 5kΩ

This value was rounded to the nearest standard capacitor available. 10 kHz was chosen to be well below the 77kHz in so that the roll off of the filter did not allow any significant amount of the 77kHz signal noise to remain on the input. Since the sample rate was 20 Hz, it was necessary to keep the input signal below 10 Hz because of the Nyquist limit. The input signal used for the screen capture Fig. 8 (pg.6), was a 5Hz sine wave.

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SCOPE CAPTURES

Master clock 3

2

10/0 1

4

5

8

7

6

9

10/0 One shot U4 Pin1 One shot U3 Pin6

0

0

0

0

0

1

0

Multiplexor out Pin10

MSB

LSB

1

Fig. 7 No input signal, 2.5VDC at input to ADC How to read the above output… 2.5volts is equal to ½ of the reference voltage of 5 volts. (2.5V is from R3,R4 voltage divider) The 8 bit binary equivalent of ½ is 100000002. The multiplexer output above (left) is read as 100000012. The one on the right side is 100000002. An 8 bit ADC divides the reference voltage into 256 possible voltage values or steps. V REF

5V = 19.5mV 256 2 ADC Binary output (number of steps) = 100000012 = 12910

Each individual step is equal to

n

=

V measured = Vstepsize × number of steps = 19.5mV × 129 = 2.52V measured

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PAM input to ADC, pin6

One shot U4 Pin1 One shot U3 Pin6 Multiplexor out Pin10

Fig. 8 5vpp, 5 Hz input signal

Fig. 9 – Delay for Counter Reset Ch1 - Master Clock Ch2 - 7408 pin3 that triggers one shot U4 Ch3 - 4049 pin10 delay to clear count

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Fig. 10 – ADC0804 Timing Ch1 ADC pin2 /rd – output result when low Ch2 ADC pin5 /intr – conversion complete when low Ch4 ADC pin3 /wr – start conversion on low to high transition Ch3 ADC clock pin19 – ADC internal clock

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Fig. 11 – Noise before filtering PAM output from switch, showing noise generated by ADC internal clock.