AMBA Smart Card Interface Data Sheet
Copyright © 1997 ARM Limited. All rights reserved. DDI 0095A
AMBA Smart Card Interface Data Sheet Copyright © 1997 ARM Limited. All rights reserved. Release Information The following changes have been made to this book. Change History Date
Issue
Confidentiality
Change
November 1997
A
Non confidential
First release
Proprietary Notice Words and logos marked with ® or ™ are registered trademarks or trademarks of ARM Limited in the EU and other countries, except as otherwise stated below in this proprietary notice. Other brands and names mentioned herein may be the trademarks of their respective owners. Neither the whole nor any part of the information contained in, or the product described in, this document may be adapted or reproduced in any material form except with the prior written permission of the copyright holder. The product described in this document is subject to continuous developments and improvements. All particulars of the product and its use contained in this document are given by ARM in good faith. However, all warranties implied or expressed, including but not limited to implied warranties of merchantability, or fitness for purpose, are excluded. This document is intended only to assist the reader in the use of the product. ARM Limited shall not be liable for any loss or damage arising from the use of any information in this document, or any error or omission in such information, or any incorrect use of the product. Where the term ARM is used it means “ARM or any of its subsidiaries as appropriate”. Confidentiality Status This document is Non-Confidential. The right to use, copy and disclose this document may be subject to license restrictions in accordance with the terms of the agreement entered into by ARM and the party that ARM delivered this document to. Product Status The information in this document is final, that is for a developed product. Web Address http://www.arm.com
ii
Copyright © 1997 ARM Limited. All rights reserved.
DDI 0095A
Contents AMBA Smart Card Interface Data Sheet
Chapter 1
Introduction 1.1 1.2 1.3
Chapter 2
Signal Description 2.1 2.2 2.3
Chapter 3
Block Diagram ............................................................................................. 3-2 Overview of Smart Card Operation ............................................................. 3-3 Character Framing .................................................................................... 3-16
Programmer’s Model 4.1 4.2 4.3 4.4
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ASB Signals ................................................................................................ 2-2 Internal Signals ........................................................................................... 2-3 External Signals .......................................................................................... 2-5
Functional Description 3.1 3.2 3.3
Chapter 4
Conformance .............................................................................................. 1-2 Smart Card Overview .................................................................................. 1-3 Features ...................................................................................................... 1-4
Introduction ................................................................................................. 4-2 Summary of Smart Card Interface Registers .............................................. 4-3 Register Descriptions .................................................................................. 4-5 Interrupts ................................................................................................... 4-18
Copyright © 1997 ARM Limited. All rights reserved.
iii
Appendix A
Test Registers A.1
iv
Test Registers ............................................................................................ A-2
Copyright © 1997 ARM Limited. All rights reserved.
DDI 0095A
Chapter 1 Introduction
The Smart Card Interface is an AMBA slave module which connects to the Advanced System Bus (ASB). For more information about AMBA, please refer to the AMBA Specification (ARM IHI 0001). • Conformance on page 1-2 • Smart Card Overview on page 1-3 • Features on page 1-4
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1-1
Introduction
1.1
Conformance The Smart Card Interface conforms to part 1 of the Integrated Circuit Specifications for Payment Systems entitled Electromechanical Characteristics, Logical Interface, and Transmission Protocols (Version 3.0 June 1996). This standard is published jointly by Europay International S.A., Mastercard International Incorporated, and Visa International Service association and is subsequently referred to as the EMV standard. This standard refers to, and is based upon, the ISO 7816 series of standards. This datasheet assumes the reader is familiar with both the EMV standard and ISO 7816-3.
1-2
Copyright © 1997 ARM Limited. All rights reserved.
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Introduction
1.2
Smart Card Overview The Smart Card Interface is an AMBA ASB peripheral that allows an ASB Master to interface to an external Smart Card reader. The Smart Card Interface can autonomously control data transfer to and from the smart card. Transmit and receive data FIFOs are provided to reduce the required interaction between the ASB Master and the peripheral.
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1-3
Introduction
1.3
Features The following features are provided by the Smart Card Interface: •
supports asynchronous T0 and T1 transmission protocols
•
supports clock rate conversion factor F = 372, with bit rate adjustment factors D = 1, 2 or 4 supported
•
eight character deep buffered TX and RX paths
•
direct interrupts for TX and RX FIFO level monitoring
•
interrupt status register
•
hardware initiated card deactivation sequence on detection of card removal
•
software initiated card deactivation sequence on transaction complete
•
limited support for synchronous smart cards via registered I/O.
The following key parameters are programmable:
1-4
•
Smart Card clock frequency
•
communication baud rate
•
protocol convention
•
card activation time
•
card deactivation time
•
check for maximum time for first character of Answer-To-Reset (ATR) reception
•
check for maximum duration of ATR character stream
•
check for maximum time for receipt of first character of data stream
•
check for maximum time allowed between characters
•
character guard time
•
block guard time
•
TX character retry
•
RX character retry
•
TX FIFO tide level
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Introduction
•
RX FIFO tide level
Additional test registers and modes are implemented to provide efficient testing.
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1-5
Introduction
1-6
Copyright © 1997 ARM Limited. All rights reserved.
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Chapter 2 Signal Description
• • •
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ASB Signals on page 2-2 Internal Signals on page 2-3 External Signals on page 2-5
Copyright © 1997 ARM Limited. All rights reserved.
2-1
Signal Description
2.1
ASB Signals The Smart Card Interface module is connected to the ASB as a slave. Table 2-1 describes the ASB signals used. Table 2-1 ASB signal descriptions
2-2
Name
Type
Source/ Destination
Description
BnRES
In
Reset Controller
Initiates a cold reset.
BCLK
In
ASB Bus
The ASB clock, which times all bus transfers.
BA[7:2]
In
ASB bus
ASB address.
BD[21:0]
InOut
ASB bus
Is part of the bidirectional system data bus.
BERROR
Out
ASB bus
ASB error signal
BLAST
Out
ASB bus
ASB break burst signal
BTRAN[1:0]
In
ASB bus
ASB transaction signal
BWAIT
Out
ASB bus
ASB wait transfer signal
BWRITE
In
ASB bus
ASB transfer direction signal
DSEL
In
Decoder
Register select signal
Copyright © 1997 ARM Limited. All rights reserved.
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Signal Description
2.2
Internal Signals A free-running reference clock, RCLK, synchronous to, and an integer multiple (x1, x2) of BCLK, must be provided. This ensures that the synchronous FIFOs within the design remain active even when BCLK is static. There are 11 possible interrupt sources. These are arranged in a cascaded structure so that three types of interrupt are presented to the interrupt controller. •
Two of these interrupts are the high priority RXREAD and TXTIDE interrupts.
•
The third interrupt indicates one or more of the other nine possible sources for which status information is accessed by reading the SMINTSTAT register.
The internal signals required in addition to the ASB signals are shown in Table 2-2. Table 2-2 Internal signal descriptions Name
Type
Source/ Destination
SMRESTIRQ
Out
ASB Master
General-purpose interrupt The interrupt source is determined by reading the SMINTSTAT register
SMTXTIDEIRQ
Out
ASB Master
TxTide Interrupt Generated when the TxFIFO’s tide mark is reached.
SMRXREADIRQ
Out
ASB Master
RxRead Interrupt. Generated when a read from the RxFIFO is required.
RCLK
In
Reference Clock
Free running clock, must be synchronous to, and an integer multiple (x1, x2) of BCLK. Used to provide the actual Smart Card clock frequency and directly used for some of the timeouts.
nSmdataOutEn
Out
SMDATA PAD
Data output enable (typically drives an open-drain configuration).
SMDataIn
In
SMDATA PAD
Data input from PAD.
nSmDataEn
Out
SMnDEN PAD
Tristate control for external off-chip buffer.
SMClkOut
Out
SMCLOCK PAD
Clock output.
nSmClkOutEn
Out
SMCLOCK PAD
Tristate output buffer control.
SMClkIn
In
SMCLOCK PAD
Clock input.
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Description
Copyright © 1997 ARM Limited. All rights reserved.
2-3
Signal Description
Table 2-2 Internal signal descriptions (continued)
2-4
Name
Type
Source/ Destination
Description
nSmClkEn
Out
SMnCLKEN PAD
Tristate control for external off-chip buffer.
SMnRESET
Out
SMnRESET PAD
nReset output.
SMVCCEN
Out
SMVCC PAD
Supply voltage control.
SmDetect
In
SMDETECT
Card detect signal from card interface device.
Copyright © 1997 ARM Limited. All rights reserved.
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Signal Description
2.3
External Signals Table 2-3 describes a typical configuration of external pins that could be used to support a Smart Card Interface. It is the responsibility of the user to make proper use of the peripheral pins to meet the exact interface requirements. Table 2-3 External signal descriptions
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Name
Type
PAD Type
Description
SMVCC
O
PULLDOWN
Controls the smart card supply voltage (VCC).
SMCLOCK
I/O
TRISTATE
Card CLK (pulldown only for synchronous card interface).
SMnCLKEN
O
PULLDOWN
Card CLK output enable (active LOW) This signal is not required if synchronous cards are not used, or if external buffering of the smart card clock is unnecessary.
SMnRESET
O
PULLDOWN
Card RST (active LOW).
SMDATA
I/O
PULLDOWN
Bidirectional data line.
SMnDEN
O
PULLDOWN
Data output enable (active LOW) SMDEN is only required if the smart card data needs to be buffered externally.
SMDETECT
I
SCHMITT
Card detect signal from card interface device.
Copyright © 1997 ARM Limited. All rights reserved.
2-5
Signal Description
2-6
Copyright © 1997 ARM Limited. All rights reserved.
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Chapter 3 Functional Description
• • •
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Block Diagram on page 3-2 Overview of Smart Card Operation on page 3-3 Character Framing on page 3-16
Copyright © 1997 ARM Limited. All rights reserved.
3-1
Functional Description
3.1
Block Diagram The major functional blocks in the Smart Card Interface are shown in Figure 1-1. 7[),)2
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Figure 3-1 Smart Card Interface block diagram
3-2
Copyright © 1997 ARM Limited. All rights reserved.
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Functional Description
3.2
Overview of Smart Card Operation After reset, the Smart Card Interface is disabled. When the Smart Card Interface is enabled, it generates a CARDIN interrupt if it detects that a card has been inserted. Before a card is activated, the interface must be configured to the correct settings for processing the Answer To Reset (ATR) and switched to receive mode. The card activation sequence is initiated by writing to the STARTUP bit of the SMICTRL register. After the contact activation sequence is complete, the card issues its ATR. When the first characters of the ATR stream arrive, the interface generates an RXREAD interrupt. The initial character is then read from the interface and used to configure the convention of the interface (direct or inverse) by setting the SMCONV register. The rest of the ATR sequence is read in and used to configure: • the clock frequency • baud rate • guard times • protocol type to be used in subsequent communication. In normal operation, the interface reads and writes blocks of characters to the card. The direction of the data flow is determined by the MODE bit in the SMITCTRL (Integrated Circuit Card Control) register. When the transaction is complete, the card is deactivated by writing to the FINISH bit of the SMICTRL register. If the card is removed prematurely, this is detected by the interface, and the card deactivates automatically.
3.2.1
ASB Interface In response to a read request, the ASB is stalled for 4 cycles while the data from the addressed register is synchronised with BCLK and transferred onto the ASB bus. In response to a write request, the address and data are internally latched and the ASB Master is allowed to continue. The write operation is then performed synchronously to the reference clock. If an ASB access is attempted before a write operation has been completed, the Smart Card Interface replies with a Retract command to the ASB master.
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3-3
Functional Description
3.2.2
Interface Reset The Smart Card Interface is reset through the global reset signal BnRES. The BnRES signal is taken LOW for a period long enough to reset the slowest block in the overall system, and is then taken HIGH again. The values of the registers after reset are detailed in Table 4-1 on page 4-3.
3.2.3
Interface Configuration After the reset sequence is complete, the interface must be configured by writing to the registers with the values shown in Table 3-1. Note The SMDTIME register controls the timing of the card deactivation sequence and must be initialized before the activation sequence takes place. This is mandatory. Failure to do so may result in damage to the card if it is removed prematurely.
Table 3-1 Initial register settings prior to ATR reception
3-4
Register
Value
Comments
SMCONV
0x0
The convention register is set to direct convention for reading the initial character (TS) of the ATR. There are only two valid TS values, 0x3B for direct or 0x3F for inverse convention. The software will read the TS value and program the SMCONV accordingly.
SMPARITY
0x0
Even parity, character receive/transmit handshaking disabled. Note: Character retry does not apply during the ATR sequence.
SMTCTRL
0x01
The interface must be put into receive mode. Interrupts must be enabled as the card recognition, activation sequences etc. are interrupt driven.
SMSTABLE
0x64
For a 48MHz (21ns) reference clock, the stable (debounce) time is in terms of multiples of 1.38ms (0xFFFF x 21ns). An initial value of 138ms is proposed.
SMATIME
0xAFC8
The SMATIME register must be programmed to between 40000 and 45000 (0xAFC8) Smart Card clock cycles to satisfy the minimum cold and warm reset RST low time requirements.
Copyright © 1997 ARM Limited. All rights reserved.
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Functional Description
Table 3-1 Initial register settings prior to ATR reception (continued)
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Register
Value
Comments
SMDTIME
0x2710
The SMDTIME is in terms of reference clock periods. It times the three stages of the deactivation sequence. The total time of the deactivation sequence must not take longer than 1ms to complete. An initial value of 10000 (0x2710) periods is suggested which is equivalent to an SMDTIME of approximately 0.21ms for a 48MHz (21ns) reference clock. This gives a total deactivation time of approximately 0.65ms.
SMATRSTIME
0x9C40
The SMATRSTIME is in terms of Smart Card clock cycles. After de-assertion of the reset RST signal, the start of ATR sequence must occur within 40,000 (0x9C40) Smart Card clock cycles.
SMATRDTIME
0x4B00
The SMATRDTIME is in terms of etus (elementary time units, see Data Transfer on page 3-10). The complete ATR character sequence must be received within 19200 (0x4B00) etus.
SMCHTIME
0x2580
The SMCHTIME is in terms of etus and is the maximum interval between the leading edges of two consecutive characters. In the case of the ATR sequence, this is 9600 (0x2580) etus. It also is applicable to characters in the transaction data stream and is T=0 or T=1 mode dependent.
SMRXTIDE
0x0
This is the receive FIFO tide level. Although a value of zero is proposed, any value between 0x0 and 0x7 can be used. With a value of zero, the RXREAD interrupt is generated when the initial TS character is loaded into the receive FIFO.
SMCLKICC
0x17
The SMCLKICC value is used to divide down the reference clock to provide the Smart Card clock. The final Smart Card clock frequency should be within the range 1–5MHz. For a 48MHz reference clock, SMCLKICC should be programmed with a value of 23 (0x17) to provide an initial 1MHz Smart Card clock frequency.
SMNBAUD
0x174
An SMNBAUD value of 372 (0x174) is required for a 1MHz Smart Card clock frequency, which is the initial proposed frequency prior to ATR reception. Refer to Data Transfer on page 3-10.
SMNVALUE
0x10
Please refer to Data Transfer on page 3-10. An SMNVALUE value of 16 (0x10) is required for a 1 MHz Smart Card clock frequency, which is the initial proposed frequency prior to ATR reception.
Copyright © 1997 ARM Limited. All rights reserved.
3-5
Functional Description
3.2.4
Card Detection A Smart Card must remain in the interface for the debounce period, which is initially defined within Table 3-1 on page 3-4. The debounce time is programmable and may be varied, if required, by writing to the SMSTABLE register. If the debounce time is satisfied, then both an internal interrupt status register bit CARDIN and an external interrupt signal SMRESTIRQ are set HIGH to signify that a card is present. The software will always read the SMINTSTAT register to establish the source of the interrupt. At this point, there are no power or clocks applied to the Smart Card, such as VCC, RST, or CLK, and the I/O signals are maintained in a LOW state by the interface. These signals are then applied in a controlled manner by the activation sequence. The software responds to the SMRESTIRQ interrupt by writing a “1” to the START bit at the SMICTRL location to initiate the card activation sequence.
3.2.5
Card Activation Sequence The activation sequence controls the supply of the power, the clock and ensures that the data line is in high impedance (receive mode) prior to starting any communication with the Smart Card. For ease of implementation, the delay between each stage within the activation sequence has been made equal and this time is programmable in Smart Card clock cycles via the SMATIME register. In normal operation, the SMATIME register should be programmed with a value between 40,000 and 45,000 Smart Card clock cycles. The activation sequence is as follows: • wait for SMATIME Smart Card clock cycles • enable VCC, configure SMDATA signal as high impedance • wait for SMATIME Smart Card clock cycles • enable Smart Card clock • wait for SMATIME Smart Card clock cycles • set the reset signal RST HIGH (part of cold reset sequence) The activation sequence listed above includes the cold reset sequence and is completed when the power is stable, the clock active, the bi-directional I/O data line is in its high impedance state and the RST signal has been set HIGH. When the cold reset stage is complete, an internal status register interrupt bit CARDUP in the SMISTAT register and an external interrupt signal SMRESTIRQ are set HIGH to signify that the card is ready to receive.
3-6
Copyright © 1997 ARM Limited. All rights reserved.
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Functional Description
The software responds to the SMRESTIRQ interrupt, enabling the block and ATR duration timers by writing a “1” to the BLKEN and ATRDEN bits within the SMTCTRL terminal control register. The interface now expects an ATR from the Smart Card and the maximum time allowed from reset deassertion to the leading edge of the first ATR character is 40,000 Smart Card clock cycles. For flexibility and possible future extensions, this maximum value is programmable via the SMATRSTIME register. The interface also expects the complete ATR stream, from its first to last character received to occur within a maximum time of 19200 etus. For flexibility and possible future extensions, this maximum value is programmable via the SMATRDTIME register. If no ATR is received within SMATRSTIME cycles, then an internal status register interrupt bit ATRSTOUT and an external interrupt signal SMRESTIRQ are set HIGH to signify that the card interface has not received the expected ATR. The associated software interrupt routine will respond to the SMRESTIRQ interrupt by writing a “1” to the FINISH bit at the SMICTRL location, to initiate the card deactivation sequence. If, during reception of the ATR, the time between the leading edges of two successive characters exceeds the SMCHTIME value, then an internal status register interrupt bit CHTOUT and an external interrupt signal SMRESTIRQ are set HIGH. The associated software interrupt routine will respond to the SMRESTIRQ interrupt by writing a “1” to the WRESET bit at the SMICTRL location, to initiate a “warm” reset sequence. If the ATR is received, its data stream structure is read and checked by software, and if any errors such as parity failure are detected, the software responds by writing a “1” to the WRESET bit at the SMICTRL location to initiate a “warm” reset sequence. If the duration of the ATR character stream exceeds the SMATRDTIME value, then an internal status register interrupt bit ATRDTOUT and an external interrupt signal SMRESTIRQ are set HIGH.The associated software interrupt routine responds to the SMRESTIRQ by writing a “1” to the WRESET bit at the SMICTRL location to initiate a “warm” reset sequence. If the ATR has no errors and is returned within SMATRDTIME initial etus, the interface proceeds with the card session, using the parameters returned by the card. If the Smart Card is removed during any stage of the activation sequence, the interface will respond to the SMDETECT signal going LOW by immediately entering the deactivation sequence through a hardware mechanism, safely removing the signals and power from the interface within a maximum time of 1 millisecond.
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Copyright © 1997 ARM Limited. All rights reserved.
3-7
Functional Description
The deactivation time is based on the reference clock frequency and should be programmed to meet the performance of the interface supply, clock and data removal times, in other words, it can be less than 1 millisecond. 3.2.6
Warm Reset Sequence The warm reset sequence is as follows:
3.2.7
•
set RST signal LOW, set I/O into high impedance, but maintain VCC and clock.
•
wait for SMATIME Smart Card clock cycles.
•
set RST signal HIGH.
•
if no ATR is received after a maximum of SMATRTIME cycles, then enter the deactivation sequence.
(ATR) Answer-To-Reset Sequence The card responds to the cold or warm resets by transmitting the ATR character sequence. An RXREAD interrupt is generated when the number of characters received exceeds the RXTIDE FIFO level. The initial character (TS) is read from the interface, interpreted by the associated software and is then used to configure the convention, direct or inverse, that the interface will use to interpret the succeeding characters of the ATR and subsequent communication. If the value of the TS character specifies that inverse convention is to be used, the convention register SMCONV is written with the hexadecimal “3” before reading the rest of the ATR. In brief, the ATR character sequence contains configuration values for: • the clock frequency • baud rate • guard times • protocol type The remainder of the ATR stream is read from the FIFO in the selected convention, interpreted by the software and the interface configured with the extracted values. The interface requires this information from the card so that subsequent communication will be performed in a manner and rate that the Smart Card can accept.
3-8
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Functional Description
3.2.8
Data Transaction After the interface has been configured by extracting the parameters from the ATR stream and writing to the appropriate interface registers, bi-directional communication between the card and interface can proceed. Data now flows between interface and card, with the direction of flow being controlled by the MODE bit in the SMTCTRL register. The character streams must meet the timimg requirements for the T0 and T1 protocols. These are covered in EMV Character Timing For T=0 (Character Protocol) on page 3-17 and EMV Character Timing For T=1 (Block Protocol) on page 3-18. When the transaction has completed, the card can be deactivated by writing a “1” to the FINISH bit at the SMICTRL location.
3.2.9
Card Deactivation Sequence Card deactivation takes precedence over any other operation and can be initiated by software, by writing a “1” to the FINISH bit at the SMICTRL location, or by hardware recognition of the SMDETECT going LOW signifying card removal is in progress. During deactivation, any writes to the SMICTRL register have no effect, while the three bits of the SMISTAT register reflect the status of the card control signals. &RQWDFW'HDFWLYDWLRQ6HTXHQFH 5()&/. &/. 9&& 567 ,2 60'7,0(
60'7,0(
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Figure 3-2 Deactivation
The interface performs the following actions during the card deactivation sequence: • drives the reset signal RST LOW • waits for SMDTIME reference clock cycles
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Copyright © 1997 ARM Limited. All rights reserved.
3-9
Functional Description
• • • • •
drives the smart clock LOW waits for SMDTIME reference clock cycles drives the SMDATA I/O line LOW waits for SMDTIME reference clock cycles drive VCC LOW
The SMDTIME is in terms of reference clock cycles, and the total time for completion of the deactivation sequence should be less than 1 milliseconds, that is, the SMDTIME is approximately one third of the total deactivation time. The maximum deactivation time is based on the card being withdrawn from the interface at a speed of 1 metre per second. On completion of the deactivation sequence, the internal interrupt status bit CARDDN in the SMINTSTAT register and the external interrupt signal SMRESTIRQ are set HIGH to signify that the card is now deactivated. 3.2.10
Data Transfer
Data Rates The duration of a bit within a character is termed the elementary time unit (etu). The etu is set by programming the SMNBAUD and SMNVALUE registers. N X baud rate clock The value in the SMNBAUD register is used to define a clock which is a multiple of the baud rate. This is known as the N X baud rate clock. The N X baud rate clock is generated by dividing the reference clock by 1 + SMNBAUD. The SMNVALUE register defines the number of N X rate clock periods which make up an etu.The etu is programmable and has different values dependent upon the stage of card processing. During the ATR, the bit duration is known as the initial etu and is given by the following equation: LQLWLDOHWX
VHFRQGV I
where f is the Smart Card clock frequency in Hertz. Following the ATR (and establishment of the global parameters F and D), the bit duration is known as the current etu, and is given by the following equation:
3-10
Copyright © 1997 ARM Limited. All rights reserved.
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Functional Description
FXUUHQWHWX
) I
[
'
VHFRQGV
where F and D are the clock rate conversion and bit rate adjustment parameters returned by the card, and f is the clock frequency applied to the Smart Card. The etu is set by programming the SMNBAUD and SMNVALUE registers. The SMNVALUE defines the number of baud rate clock periods that define the etu. Therefore: HWX
601%$8' [ 6019$/8( 5HIHUHQFH&ORFN
Thus the following equation must always be satisfied: ) I
601%$8' [ 6019$/8( 5HIHUHQFH&ORFN
[
'
See ISO 7816-3 for the possible values of F and D that can be returned by the card. Note The EMV standard specifies that f must be in the range 1 – 5 MHz; ISO 7816-3 merely specifies a lower bound of 1 MHz.
3.2.11
Example Configurations It must be stressed that the following tables are examples only. The user may use different combinations that satisy the equation detailed in Data Transfer on page 3-10. For Smart Card Minimum Frequency of 1MHz, F = 372: • RefClk = 48MHz • CLKICC = 23 • resultant RCLK Divisor = 48 Table 3-2 Smart Card minimum frequency of 1MHz, F = 372
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RefClk Freq MHz
Smart Card Freq MHz
Clk Rate Conv F
Bit Rate Adj D
(1+SMNBAUD)
(SMNVALUE)
48
1
372
1
372
48
Copyright © 1997 ARM Limited. All rights reserved.
3-11
Functional Description
Table 3-2 Smart Card minimum frequency of 1MHz, F = 372 (continued) RefClk Freq MHz
Smart Card Freq MHz
Clk Rate Conv F
Bit Rate Adj D
(1+SMNBAUD)
(SMNVALUE)
48
1
372
2
372
24
48
1
372
4
372
12
48
1
372
8
372
6
48
1
372
16
372
3
48
1
372
1/2
5952 (372x16)
6
48
1
372
1/4
5952 (372x16)
12
48
1
372
1/8
5952 (372x16)
24
48
1
372
1/16
5952 (372x16)
48
48
1
372
1/32
5952 (372x16)
96
48
1
372
1/64
5952 (372x16)
192
For Smart Card Maximum Frequency of 4.8 (5.0) MHz, F = 372: • RefClk = 48MHz • CLKICC = 4 • resultant RCLK Divisor = 10 Table 3-3 Smart Card maximum frequency of 4.8 (5.0) MHz, F = 372
3-12
RefClk Freq MHz
Smart Card Freq MHz
Clk Rate Conv F
Bit Rate Adj D
(1+SMNBAUD)
(SMNVALUE)
48
4.8
372
1
78 (372/4.8=77.5)
48
48
4.8
372
2
78 (372/4.8=77.5)
24
48
4.8
372
4
78 (372/4.8=77.5)
12
48
4.8
372
8
78 (372/4.8=77.5)
6
48
4.8
372
16
78 (372/4.8=77.5)
3
48
4.8
372
1/2
1240 (77.5x16)
6
48
4.8
372
1/4
1240 (77.5x16)
12
48
4.8
372
1/8
1240 (77.5x16)
24
Copyright © 1997 ARM Limited. All rights reserved.
DDI 0095A
Functional Description
Table 3-3 Smart Card maximum frequency of 4.8 (5.0) MHz, F = 372 (continued) RefClk Freq MHz
Smart Card Freq MHz
Clk Rate Conv F
Bit Rate Adj D
(1+SMNBAUD)
(SMNVALUE)
48
4.8
372
1/16
1240 (77.5x16)
48
48
4.8
372
1/32
1240 (77.5x16)
96
48
4.8
372
1/64
1240 (77.5x16)
192
For Smart Card Minimum Frequency of 1MHz, F = 558: • RefClk = 48MHz • CLKICC = 23 • resultant RCLK Divisor = 48 Table 3-4 Smart Card minimum frequency of 1MHz, F = 558 RefClk Freq MHz
Smart Card Freq MHz
Clk Rate Conv F
Bit Rate Adj D
(1+SMNBAUD)
(SMNVALUE)
48
1
558
1
558
48
48
1
558
2
558
24
48
1
558
4
558
12
48
1
558
8
558
6
48
1
558
16
558
3
48
1
558
1/2
8928 (558x16)
6
48
1
558
1/4
8928 (558x16)
12
48
1
558
1/8
8928 (558x16)
24
48
1
558
1/16
8928 (558x16)
48
48
1
558
1/32
8928 (558x16)
96
48
1
558
1/64
8928 (558x16)
192
For Smart Card Maximum Frequency of 6.0 MHz, F = 558: • RefClk = 48MHz • CLKICC = 3
DDI 0095A
Copyright © 1997 ARM Limited. All rights reserved.
3-13
Functional Description
•
resultant RCLK Divisor = 8 Table 3-5 Smart Card maximum frequency of 6.0 MHz, F = 558
RefClk Freq MHz
Smart Card Freq MHz
Clk Rate Conv F
Bit Rate Adj D
(1+SMNBAUD)
(SMNVALUE)
48
6.0
558
1
93 (558/6)
48
48
6.0
558
2
93 (558/6)
24
48
6.0
558
4
93 (558/6)
12
48
6.0
558
8
93 (558/6)
6
48
6.0
558
16
93 (558/6)
3
48
6.0
558
1/2
1488 (93x16)
6
48
6.0
558
1/4
1488 (93x16)
12
48
6.0
558
1/8
1488 (93x16)
24
48
6.0
558
1/16
1488 (93x16)
48
48
6.0
558
1/32
1488 (93x16)
96
48
6.0
558
1/64
1488 (93x16)
192
For Smart Card Minimum Frequency of 1MHz, F = 2048: • RefClk = 48MHz • CLKICC = 23 • resultant RCLK Divisor = 48 Table 3-6 Smart Card minimum frequency of 1MHz, F = 2048
3-14
RefClk Freq MHz
Smart Card Freq MHz
Clk Rate Conv F
Bit Rate Adj D
(1+SMNBAUD)
(SMNVALUE)
48
1
2048
1
2048
48
48
1
2048
2
2048
24
48
1
2048
4
2048
12
48
1
2048
8
2048
6
48
1
2048
16
2048
3
48
1
2048
1/2
32768 (2048x16)
6
Copyright © 1997 ARM Limited. All rights reserved.
DDI 0095A
Functional Description
Table 3-6 Smart Card minimum frequency of 1MHz, F = 2048 (continued) RefClk Freq MHz
Smart Card Freq MHz
Clk Rate Conv F
Bit Rate Adj D
(1+SMNBAUD)
(SMNVALUE)
48
1
2048
1/4
32768 (2048x16)
12
48
1
2048
1/8
32768 (2048x16)
24
48
1
2048
1/16
32768 (2048x16)
48
48
1
2048
1/32
32768 (2048x16)
96
48
1
2048
1/64
32768 (2048x16)
192
For Smart Card Maximum Frequency of 20 MHz, F = 2048: • RefClk = 40MHz • CLKICC = 0 • resultant RCLK Divisor = 2 Table 3-7 Smart Card maximum frequency of 20 MHz, F = 2048 RefClk Freq MHz
Smart Card Freq MHz
Clk Rate Conv F
Bit Rate Adj D
(1+SMNBAUD)
(SMNVALUE)
40
20
2048
1
102 (2048/20=102.4)
40
40
20
2048
2
102 (2048/20=102.4)
20
40
20
2048
4
102 (2048/20=102.4)
10
40
20
2048
8
102 (2048/20=102.4)
5
40
20
2048
16
102 (2048/20=102.4)
3
40
20
2048
1/2
1638 (102.4x16)
5
40
20
2048
1/4
1638 (102.4x16)
10
40
20
2048
1/8
1638 (102.4x16)
20
40
20
2048
1/16
1638 (102.4x16)
40
40
20
2048
1/32
1638 (102.4x16)
80
40
20
2048
1/64
1638 (102.4x16)
160
DDI 0095A
Copyright © 1997 ARM Limited. All rights reserved.
3-15
Functional Description
3.3
Character Framing Figure 3-3 shows the structure of a character. Each character consists of: • a start bit • eight data bits • a parity bit • a number of bits making up the guardtime before the start bit of the next character The guardtime is the delay between the trailing edge of the parity bit of a character and the leading edge of the start bit of the next character. The guardtime for characters transmitted by the interface is controlled by the SMCHGUARD register.
&+$5$&7(5'85$7,21
6 3
6 3 *8$5'
(78
Figure 3-3 Character structure
Figure 3-4 shows how the interface interprets characters transmitted from the card. At time TS, the card pulls the bidirectional I/O line LOW to begin the start bit. 7$. 76 7 7 7 7 7 7 7 7 73 7*
6 3 * * 6 3
56 5 5 5 5 5 5 5 5 53
5$.
Figure 3-4 Character timings
The interface detects the leading edge of the start bit after four reference clock cycles. The I/O line is sampled at RS, approximately half an etu after the leading edge of the start bit. If the I/O line is not LOW, the start bit is deemed to be invalid and is ignored by the interface.
3-16
Copyright © 1997 ARM Limited. All rights reserved.
DDI 0095A
Functional Description
The delay between TS and RS is SMNVALUE div 2 (N X baud rate clock cycles). The smallest valid value for SMNVALUE is 3, in which case the sampling point is one sixth of an etu away from the ideal halfway point. The first data bit is sampled at 1 etu after RS, and subsequent data bits (including the parity bit) are sampled at 1 etu intervals. The T0 protocol defines a mechanism whereby the receiver can request retransmission of a character by pulling the I/O line LOW during the guardtime following the character. When a retransmission is requested, the interface starts to pull the I/O line LOW at RAK. The transmitter (the card in this case) samples the I/O line at TAK. The interface holds the I/O line for a total of 2 etus. This is shown in Figure 3-5.
7$. 76 7 7 7 7 7 7 7 7 73 7*
6 3
56 5 5 5 5 5 5 5 5 53
5$. HWXV
Figure 3-5 T0 retransmit request
3.3.1
EMV Character Timing For T=0 (Character Protocol) The minimum interval between the leading edges of the start bits of two consecutive characters sent by the interface to the Smart Card is between 12 and 266 etus as indicated by the value of TC1 returned within the ATR stream. The minimum interval between the leading edges of the start bits of two consecutive characters sent by the Smart Card to the interface is 12 etus. The maximum interval between the start leading edge of any character sent by the Smart Card and the start leading edge of the previous character sent either by the Smart Card or the interface (the work waiting time) will not exceed 960 x D x WI = 9600 etus. (The bit rate conversion factor, D, will have a default value of 1. WI will not have a default value of 10 as TC2, which would contain the value, is not returned in the ATR.) The minimum interval between the leading edges of the start bits of two consecutive characters sent in opposite directions will be 16 etus.
DDI 0095A
Copyright © 1997 ARM Limited. All rights reserved.
3-17
Functional Description
Note The minimum interval between the leading edges of the start bits of two characters sent by interface to the Smart Card is always governed by the value of TC1, and may be less than minimum interval of 16 etus allowed between two characters sent in opposite directions.
3.3.2
EMV Character Timing For T=1 (Block Protocol) The minimum interval between the leading edges of the start bits of two consecutive characters sent by the interface to the Smart Card will be between 11 and 266 etus as indicated by the value of TC1 returned within the ATR stream. The minimum interval between the leading edges of the start bits of two consecutive characters sent by the Smart Card to the interface will be 11 etus. The maximum interval between the leading edges of the start bits of to consecutive characters in the same block (the character waiting time, CWT, will not exceed (2*CWI + 11) etus. The character waiting integer, CWI, will have a value of 0 to 5, resulting in the CWT having the range 12 to 43 etus. The maximum interval between the leading edge of the start bit of the last character that gave the right to send to the Smart Card and the leading edge of the first character sent by the Smart Card (the Block Waiting Time, BWT) will not exceed ((2*BWI x 960) + 11) etus. The block waiting integer, BWI, will have a value in the range 0 to 4, resulting in the BWT having the range 971 to 15371 etus. The minimum interval between the leading edges of the start bits of two consecutive characters sent in opposite directions (the Block Guard Time, BGT) will be 22 etus.
3.3.3
Transmit Characters that are to be sent to the card are first written into the SMDATA FIFO and then automatically transmitted to the card at timed intervals. Direction of communication is controlled by the MODE bit of the SMTCTRL register. Changing from transmit to receive does not take place until the last character stored in the transmit FIFO has been sent. This enables the MODE bit to be written immediately after writing the last character in a block. This is necessary because the card can respond to the transmission almost immediately (minimum turnaround time measured from start bit to start bit is 16 etus for T0 and 22 etus for T1). If character-transmit handshaking is enabled (mandatory for T0), the I/O line is sampled at 1 etu after the parity bit. If the card indicates that it did not receive the character correctly, the character is retransmitted a maximum of SMTXRETRY times before the transmission is aborted and a TXERR interrupt generated. The interface waits for four
3-18
Copyright © 1997 ARM Limited. All rights reserved.
DDI 0095A
Functional Description
etus after an error is detected before the character is retransmitted. If a character fails to be transmitted and a TXERR interrupt is generated, the transmit/receive interlock mechanism must be reset by flushing the transmit FIFO before any subsequent transmit or receive operation. The interval between successive characters sent by the interface is governed by the SMCHGUARD register, which defines the character guard time. SMCHGUARD is only used to control the transmission of characters and is not used by the receive hardware. The minimum interval between the last character sent by the card and the next character sent by the interface is governed by the SMBKGUARD register, which defines the block guard time. When the number of characters held in the transmit FIFO falls below the level defined in the SMTXTIDE register, a TXTIDE interrupt is generated. The number of characters held in the transmit FIFO can be determined by reading the SMTXCOUNT register. Writing to the SMTXCOUNT register flushes the transmit FIFO. 3.3.4
Receive Characters are read from the interface by reading the SMDATA register. When read, SMDATA has 10 bits: • eight data bits • two status flags See Table 4-2: SMDATA register on page 4-5 for more information. Before characters can be read from the interface, the MODE bit of the SMTCTRL register must be set to 0. An interlock mechanism ensures that if the MODE bit is set to receive and there are still characters remaining in the transmit FIFO, these are transmitted before any characters are read from the card. The receive FIFO must be flushed prior to the first receive operation after system reset.
3.3.5
Block time and time between characters Two registers define an upper limit on the time waited for a character to be transmitted by the card. SMBLKTIME defines the timeout limit for the first character in a block. SMCHTIME defines the maximum allowed time between characters (excluding the first character in a block)
DDI 0095A
Copyright © 1997 ARM Limited. All rights reserved.
3-19
Functional Description
The SMCHTIME counter is linked to the SMBLKTIME counter and not start until the SMBLKTIME counter has stopped (That is, the first character in the block has arrived, or if the block timer has been disabled). The transmit/receive interlock mechanism prevents the SMCHTIME and SMBLKTIME counters from running while characters are still present in the transmit FIFO. 3.3.6
Parity error If character-transmit handshaking is enabled (RXNAK = 1) and the interface detects a parity error, it signals this to the card by pulling the I/O line down for 2 etus at 10.5 etus after the leading edge of the start bit. The maximum number of times the interface attempts to receive a character is governed by the SMRXRETRY register. If, after SMRXRETRY further attempts, the character has not be successfully received, a parity error for the character is flagged. When this character is read, bit 8 of SMDATA is set to 1 to indicate that a parity error has occurred.
3.3.7
RXREAD interrupt An RXREAD interrupt can be caused either: • by the receive FIFO exceeding its tide mark (defined by SMRXTIDE) • by a read access timeout (defined by SMRXTIME) The read access timeout limit can be reprogrammed dynamically, which provides a way of enabling the receive timeout mechanism only at the end of blocks. This is achieved by initially setting the receive timeout threshold to a high enough value to guarantee that an RXREAD interrupt can only have been caused by a tide mark condition (excluding an error condition where a card stops transmitting part way through a block). When the end of the block is reached, RXTIME is reprogrammed with the correct value to process the trailing characters in the block.
3-20
Copyright © 1997 ARM Limited. All rights reserved.
DDI 0095A
Chapter 4 Programmer’s Model
• • • •
DDI 0095A
Introduction on page 4-2 Summary of Smart Card Interface Registers on page 4-3 Register Descriptions on page 4-5 Interrupts on page 4-18
Copyright © 1997 ARM Limited. All rights reserved.
4-1
Programmer’s Model
4.1
Introduction The base address of the Smart Card Interface is not fixed and may be different for any particular system implementation. However, the offset of any particular register from the base address is fixed. Note The locations at offsets +0xB0 through +0xFC are reserved for test purposes and should not be used during normal operation.
4-2
Copyright © 1997 ARM Limited. All rights reserved.
DDI 0095A
Programmer’s Model
4.2
Summary of Smart Card Interface Registers All registers are read/write unless otherwise stated. None of the registers contains reserved bits (which would require read/modify/write to change the register contents). If an n-bit wide Smart Card register is read into an ARM register, bits 31 down to n of the ARM register are undefined. The following registers are provided: Table 4-1 Smart Card Interface register summary
Offset
Type
Width
Reset Value
Name
Description
0x00 – 0x3C
R/W
10/8
0x000
SMDATA
Data read or written from the interface.
0x40
R/W
2
0x0
SMCONV
Convention configuration register.
0x44
R/W
4
0x0
SMPARITY
Controls parity sense and handshaking.
0x48
R/W
3
0x0
SMTXRETRY
Number of retransmit attempts for T0 protocol.
0x4C
R/W
3
0x0
SMRXRETRY
Number of receive attempts for T0 protocol.
0x50
R/W
4
0x0
SMTXTIDE
Transmit FIFO tide level.
0x54
R/W
4
0x0
SMTXCOUNT
Transmit FIFO character count / flush Transmit FIFO.
0x58
R/W
4
0x0
SMRXTIDE
Receive FIFO tide level.
0x5C
R/W
4
0x0
SMRXCOUNT
Receive FIFO character count / flush Receive FIFO.
0x60
R/W
16
0x0000
SMRXTIME
Receive FIFO timeout value.
0x64
R/W
7
0x00
SMTCTRL
Terminal control register.
0x68
R/W
8
0x00
SMSTABLE
Debounce time value.
0x6C
W
3
0x0
SMICTRL
Activation, warm reset and deactivation card control register.
0x70
R/W
4/3
0x0
SMISTAT
Card detection, power and clock status.
0x74
R/W
16
x0000
SMATIME
Timer value for activation events (Smart Card clock cycles).
0x78
R/W
16
0x0000
SMDTIME
Timer value for deactivation events (etus).
DDI 0095A
Copyright © 1997 ARM Limited. All rights reserved.
4-3
Programmer’s Model
Table 4-1 Smart Card Interface register summary (continued) Offset
Type
Width
Reset Value
Name
Description
0x7C
R/W
16
0x0000
SMATRSTIME
Maximum time between reset de-assertion and Start of ATR reception.
0x80
R/W
16
0x0000
SMATRDTIME
Maximum time duration from start to completion of ATR reception.
0x84
R/W
16
0x0000
SMBLKTIME
Maximum time between blocks.
0x88
R/W
16
0x0000
SMCHTIME
Maximum time between characters.
0x8C
R/W
8
0x00
SMCLKICC
Reference clock divisor value to provide the Smart Card clock frequency.
0x90
R/W
16
0x0000
SMNBAUD
Reference clock divisor value to provide the baud rate clock frequency.
0x94
R/W
8
0x00
SMNVALUE
Number of baud rate clock cycles that constitute an elementary time unit (etu).
0x98
R/W
8
0x00
SMCHGUARD
Extra guard time to provide the minimum time between characters (etus).
0x9C
R/W
8
0x00
SMBKGUARD
Extra guard time to provide the minimum time between blocks (etus).
0xA0
R/W
2
0x0
SMSYNCTRL
Synchronous Smart Card control.
0xA4
R/W
4
0x0
SMSYNCDAT
Synchronous Smart Card data.
0xA8
R
2
0x0
SMRAWSTAT
Raw Smart Card I/O and clock status.
0xAC
R/W
11/9
0x200
SMINTSTAT
Interrupt status register
4-4
Copyright © 1997 ARM Limited. All rights reserved.
DDI 0095A
Programmer’s Model
4.3
Register Descriptions
4.3.1
SMDATA: Data register [10/8] (+0x00 – 0x3C) The SMDATA register is used for both transmitting and receiving characters. This register has multiple address mappings so it can write or read multiple characters using STM/LDM. Table 4-2 SMDATA register
4.3.2
Bits
Name
RD/WR
Function
7–0
DATA
RW
Eight data bits which correspond to the character being read or written.
8
PARITY
R
Parity error flag. Set to 1 if a parity error was detected when receiving the character corresponding to bits 7-0.
9
LAST
R
Set to 1 if this is the last character in the receive FIFO.
SMCONV: Convention configuration register [2] (+0x40) The SMCONV register configures the convention for interpreting characters.The convention is determined by the initial character returned by the card in the ATR sequence. There are two conventions: inverse
a low state on the I/O line is interpreted as a logic one and the msb (most significant bit) of the data byte is the first bit after the start bit.
direct
a low state on the I/O line is interpreted as a logic zero and the lsb (least significant bit) of the data byte is the first bit after the start bit.
Separate bits are used to control the logic sense and the bit ordering. This allows for non-standard conventions to be configured. This is illustrated in Table 4-3 on page 4-6. The SMCONV register should be set to 00 before reading the initial (TS) character from the ATR stream. The TS character determines the convention which the remainder of the ATR stream has been encoded with.
DDI 0095A
Copyright © 1997 ARM Limited. All rights reserved.
4-5
Programmer’s Model
Inverse convention is configured by writing 11 to SMCONV after reading the TS character and before reading any subsequent characters in the ATR. Table 4-3 Convention register
4.3.3
Bit
Name
Function
0
SENSE
Inverts sense of I/O line for data and parity bits: 0 = direct convention 1 = inverse convention
1
ORDER
Specifies ordering of the data bits: 0 = direct convention 1 = inverse convention
SMPARITY: Parity control [4] (+ 0x44) The SMPARITY register controls the parity convention used (odd/even) and enables the handshaking mechanism where the receiver pulls down the I/O line to indicate that a parity error has occurred. Separate controls exist for the transmit and receive paths. The maximum number of attempts made to either transmit or receive a character are specified in the SMTXRETRY and SMRXRETRY registers. Character retry is not applied during ATR reception, hence SMPARITY should be programmed initially with the value 0x0. It need only be programmed with 0xA if T = 0 protocol is requested by the contents of the initial (TS) character of the ATR stream. Table 4-4 Parity Control register
4-6
Bit
Name
Function
0
TXPARITY
Transmission parity setting: 1 = odd 0 = even
1
TXNAK
Enables character transmit handshaking If TXNAK = 0, the interface does not check to see if the receiver has pulled the I/O line low to indicate a parity error.
2
RXPARITY
Receive parity setting: 1 = odd 0 = even
Copyright © 1997 ARM Limited. All rights reserved.
DDI 0095A
Programmer’s Model
Table 4-4 Parity Control register (continued)
4.3.4
Bit
Name
Function
3
RXNAK
Enables character receipt transmit handshaking. If RXNAK = 0, the interface does not pulldown the I/O line if it detects a parity error.
SMTXRETRY: Transmit retry limit [3] (+0x48) If character-transmit handshaking is enabled (TXNAK = 1), the SMTXRETRY register contains a 3 bit value (0 – 7). This specifies the maximum number attempts that can be made to retransmit a character that has been incorrectly received by the card, before aborting the transmission and generating a TXERR interrupt.
4.3.5
•
For normal T0 operation, SMTXRETRY should be set to 011 for a maximum of 3 retries. A value of 000 causes a TXERR interrupt, generated immediately an error is detected.
•
For T1 operation, character-based handshaking should be turned off (TXNAK = 0), in which case SMTXRETRY is not used.
SMRXRETRY: Receive retry limit [3] (+0x4C) The SMRXRETRY register contains a 3 bit value (0 – 7). This specifies the maximum number of times the interface will request retransmission of a character after detection of a parity error. If the character has not been successfully received after SMXRETRY attempts, the parity error flag for that character is set. This appears as bit 8 of the SMDATA register when it is read. For normal T0 operation, SMRXRETRY should be set to 011 for a maximum of 3 retries. A value of 000 writes the received character to the receive FIFO with no request for retransmission in the event of an error. This has the same effect as setting RXNAK to 0.
4.3.6
SMTXTIDE: Transmit FIFO tide mark [4] (+0x50) The SMTXTIDE register contains the trigger point for the TXTIDE interrupt. When the number of characters in the transmit FIFO falls below this threshold, a TXTIDE interrupt is generated. Setting SMTXTIDE to 0 prevents TXTIDE interrupts. Only values between 0 and 8 (inclusive) are valid.
DDI 0095A
Copyright © 1997 ARM Limited. All rights reserved.
4-7
Programmer’s Model
A TXTIDE interrupt can only occur if the MODE bit of the SMTCTRL register is set to 1 (transmit). Note that a character is not removed from the transmit FIFO until it has been successfully transmitted. 4.3.7
SMTXCOUNT: Transmit FIFO count (R) / Flush (W) [4] (+0x54) The SMTXCOUNT register returns the number of characters present in the transmit FIFO when read (including any character currently being transmitted). Writing to this register with any value flushes the transmit FIFO. The transmit FIFO must be flushed before the first transmit operation after system reset. If there is an unsuccessful transmission when using the T0 protocol, the interface generates a TXERR interrupt and stops transmitting. Before any further characters can be transmitted or received, the error condition must be cleared by flushing the transmit FIFO.
4.3.8
SMRXTIDE: Receive FIFO tide mark [4] (+0x58) The SMRXTIDE register contains a trigger point for the receive FIFO. When the number of characters in the receive FIFO exceeds SMRXTIDE, an RXREAD interrupt is generated. Setting SMRXTIDE to 0 causes an interrupt as soon as the FIFO is non-empty. A value of 8 or more prevents any interrupt from occurring. An RXREAD interrupt can only occur when the MODE bit of the SMTCTRL register is set to 0 (receive).
4.3.9
SMRXCOUNT: Receive FIFO count (R) / flush (W) [4] (+0x5C) The SMRXCOUNT register returns the number of characters present in the receive FIFO when read. Writing to this register with any value flushes the receive FIFO. The receive FIFO must be flushed before the first receive operation after system reset.
4.3.10
SMRXTIME: Receive/Read timeout [16] (+0x60) An RXREAD interrupt is triggered if:
4-8
•
the receive FIFO contains at least one character, and
•
no characters have been read for a time corresponding to SMRXTIME Smart Card clock cycles
Copyright © 1997 ARM Limited. All rights reserved.
DDI 0095A
Programmer’s Model
Table 4-5 lists the range and resolution of the timeout value for various Smart Card clock frequencies: Table 4-5 RXTIME ranges/resolution
4.3.11
Frequency
Range (approx.)
Resolution
500 KHz
0 – 131 ms
2 us
1 MHz
0 – 65 ms
1 us
5 MHz
0 – 13 ms
0.2 us
10 MHz
0 – 6 ms
0.1 us
SMTCTRL: Terminal control [7] (+0x64) The SMTCTRL register contains seven bits: Table 4-6 Terminal Control register Bit
Name
Function
0
ENABLE
Interrupt enable. 0 = Disable the external SMRESTIRQ, SMTXTIDEIRQ and SMRXREADIRQ interrupts 1 = Enable the external SMRESTIRQ, SMTXTIDEIRQ and SMRXREADIRQ interrupts.
Note The SMSINSTAT register contains the actual interrupt status at all times
DDI 0095A
1
ATRDEN
ATR Duration timeout enable 0 = Disable 1 = Enable
2
BLKEN
Block timeout enable 0 = Disable 1 = Enable
3
MODE
Interface direction of communication control 0 = Receive 1 = Transmit
Copyright © 1997 ARM Limited. All rights reserved.
4-9
Programmer’s Model
Table 4-6 Terminal Control register (continued) Bit
Name
Function
4
CLKZ1
SMCLOCK output configuration. 0 = SMCLOCK configured as buffer output 1 = SMCLOCK configured as pull down (open drain)
5
BGTEN
Block guard timer enable: 0 = Disable 1 = enable
6
EXDBNCE
External debounce 0 = Utilize the whole of Internal debounce timer 1 = Bypass non-programmable section of internal debounce timer
CLKZ1
is used to configure the SMCLOCK output pad. If an external pullup resistor is connected to the Smart Card clock signal (as is the case for synchronous card systems where both the terminal and the card can pull the clock line low), the SMCLOCK output should be configured as pulldown only.
EXDBNCE is used to bypass the non-programmable portion of the debounce timer, allowing a zero-debounce time by setting the programmable portion of the timer to 0. 4.3.12
SMSTABLE: Debounce timer [8] (+0x68) The SMSTABLE register determines how long the SMDETECT signal must hold a stable high value before the interface registers the insertion of a card. This is notified by setting the CARDIN bit of the SMISTAT register to 1. A falling edge on the SMDETECT register immediately resets CARDIN to 0. The debounce timer is constructed as a 16 bit counter feeding a programmable 8 bit counter, the former being loaded with 0xFFFF and the latter with the value contained in the SMSTABLE register. When enabled, the 16 bit counter decrements through the reference clock, and on each successive pass through zero, it decrements the 8 bit counter value until it reaches zero. The logic is configured to provide a debounce time of (SMSTABLE + 1) multiples of the 16 bit full count. For a 48MHz reference clock, this gives a programmable debounce time in the range 1.38ms to 350.28ms in 1.38ms steps.
4-10
Copyright © 1997 ARM Limited. All rights reserved.
DDI 0095A
Programmer’s Model
The 16 bit counter can be bypassed for test purposes by setting the EXDBNCE bit high. The reference clock then feeds the 8 bit SMSTABLE counter, with the interrupt status and signals being set when this counter reaches zero. If the debounce period is satisfied an internal status bit, CARDIN, (within the SMINSTAT register) and SMRESTIRQ (an external signal) are set. 4.3.13
SMICTRL: ICC control (write only) [3] (+0x6C) Activation, deactivation and warm reset events are initiated in software by writing to the SMICTRL register. If a write occurs during the deactivation sequence, it is ignored. At any other time, a 1 written to the FINISH bit immediately starts the deactivation sequence. Table 4-7 ICC Control register
4.3.14
Bit
Name
Function
0
STARTUP
write of 1 starts the activation of the card
1
FINISH
write of 1 deactivates the card
2
WRESET
write of 1 causes a warm reset
SMISTAT: ICC status [4] (+0x70) The status register provides direct access to ICC signals and is only required if a non-EMV-compliant configuration is used. The status register is updated automatically during activation, deactivation and warm reset events. Writes do not affect the PRESENT bit. Table 4-8 ICC Status register
DDI 0095A
Bit
Name
Function
0
PRESENT
R
1 if Smart Card is present
1
POWER
R/W
Controls Smart Card VCC
2
CRESET
R/W
Controls Smart Card reset signal
3
CLKEN
R/W
Enables Smart Card clock 0 forces Smart Card clock low
Copyright © 1997 ARM Limited. All rights reserved.
4-11
Programmer’s Model
4.3.15
SMATIME: Activation event timing [16] (+0x74) The SMATIME register defines the duration in Smart Card clock cycles of the time taken for each of the three stages of the card activation process The programmed value must satisfy the minimum SMnRESET low time of 40000 cycles and should be sufficient time for the interface power to stabilize.
4.3.16
SMDTIME: Deactivation event timing [16] (+0x78) The SMDTIME register defines the time in reference clock cycles of the time taken for each stage the three stages of the card deactivation process. The total deactivation time must be less than 1ms, hence the maximum SMDTIME must be less than 0.33ms. The deactivation sequence can be initiated by software, by writing a “1” to the FINISH bit at the SMICTRL location, or hardware, on detection of card removal via a “0” on the SMDETECT signal.
4.3.17
SMATRSTIME: Time to Start of ATR reception [16] (+0x7C) The SMATRSTIME register defines the receive timeout threshold from the de-assertion of SMnRESET to the start of the first character in the ATR. This is specified in Smart Card clock cycles and its initial value is 40000 Smart Card clock cycles. Note that the time in seconds will vary with Smart Card clock frequency. On timeout this timer will set an internal ATRSTOUT interrupt bit within the SMISTAT register and also set the SMRESTIRQ external interrupt.
4.3.18
SMATRDTIME: Maximum Duration of the ATR character stream [16] (+0x80) The SMATRDTIME register defines the receive timeout threshold for the duration of the ATR sequence, from the start bit of the first ATR character until the end of the ATR block. This is specified in etu's and should be programmed to 19200 etus as per the current specifications. On timeout this timer will set an internal ATRDTOUT interrupt bit within the SMISTAT register and also set the SMRESTIRQ external interrupt signal. In normal operation this interrupt will be disabled after the full ATR block has been received by setting, using a software routine, ATRDEN = 0 in the terminal control register SMTCTRL.
4-12
Copyright © 1997 ARM Limited. All rights reserved.
DDI 0095A
Programmer’s Model
4.3.19
SMBLKTIME: Receive timeout [16] (+0x84) This is the maximum delay from the start leading edge of the last character that gave the right to send to the card, and the first character to be sent by the card. SMBLKTIME applies to both T0 and T1 protocols.
•
•
Note For T0, the SMBLKTIME is effectively offset by 12 etus internally, e.g to obtain a block time out of 50 etus, then the SMBLKTIME register should be programmed with 38. For T1, the SMBLKTIME is effectively offset by 11 etus internally, e.g to obtain a block time out of 50 etus, then the SMBLKTIME register should be programmed with 39.
The SMBLKTIME register defines one of above respective values in etus. Failure to meet the SMBLKTIME value results in the setting of the internal BLKTOUT interrupt bit within the SMINTSTAT interrupt status register and the external SMRESTIRQ interrupt signal. Note The SMBLKTIME parameter is not applicable to the ATR reception. The reception of the first character of the ATR stream must not exceed the value programmed in the SMATRSTIME register, which is in terms of Smart Card clock cycles. The SMATRSTIME value is defined as 40000 Smart Card clock cycles.
4.3.20
SMCHTIME: Character To Character timeout [16] (+0x088) The SMCHTIME register defines the maximum time in etus between the leading edges of two consecutive characters for both T0 (character) and T1 (block) protocols. It is also in force during the ATR reception. For T0, this is termed the “work waiting time” and is simply the time between characters. Note For T0, the SMCHTIME is effectively offset by 12 etus internally, e.g to obtain a character to character time of 50 etus, then the SMCHTIME register should be programmed with 38.
DDI 0095A
Copyright © 1997 ARM Limited. All rights reserved.
4-13
Programmer’s Model
For T1, this is termed the character waiting time (CWT), and the respective characters must reside in the same block. Note For T1, the SMCHTIME is effectively offset by 11 etus internally, for example, to obtain a character to character time of 50 etus, then the SMCHTIME register should be programmed with 39. Failure to meet the SMCHTIME results in setting of the CHTOUT bit within the SMISTAT interrupt status register and the external SMRESTIRQ interrupt signal. 4.3.21
SMCLKICC: External Smart Card clock frequency [8] (+0x8C) The external Smart Card clock frequency (f) is generated by dividing the reference clock by value of SMCLKICC + 1 and then dividing again by 2: I
UHIFORFN 60&/.,&& ;
If SMCLKICC is set to 0, f is refclock / 2. If SMCLKICC is set to 1, f is refclock / 4 SMCLKICC is an 8-bit register and must be programmed with a value between 0 and 255 before SMCLOCK is enabled. 4.3.22
SMNBAUD: Baud rate clock [16] (+0x90) The SMNBAUD register defines the divide value used to generate an N X baud rate clock from the reference clock, where N is set in the SMNVALUE register. SMNBAUD is a 16-bit register and must be programmed with a value between 1 and 0xFFFF. The frequency of the N X BAUD rate clock is equal to the frequency of the reference clock divided by (SMNBAUD + 1).
4.3.23
SMNVALUE: SMNBAUD cycles [8] (+0x94) The SMNVALUE register defines the number of SMNBAUD cycles per etu. This register is 8 bits wide and may be programmed with any value between 3 and 255.
4-14
Copyright © 1997 ARM Limited. All rights reserved.
DDI 0095A
Programmer’s Model
4.3.24
SMCHGUARD: Character To Character Extra Guard Time [8] (+0x098) The SMCHGUARD value is the extra guardtime that will be added to the minimum duration between the leading edges of the start bits of two consecutive characters for subsequent communication from the interface to the Smart Card. The SMCHGUARD value is derived from the TC1 value that is extracted from the ATR character stream. The TC1 value may have any value between 0 and 255. The software must read the TC1 value and program the SMCHGUARD register as detailed in Table 4-9, to provide the resultant applied guard time in etus. Table 4-9 SMCHGUARD register values for T0 and T1 ATR TC1 Value
SMCHGUARD Value
Resultant Guard Time (etus)
T0
T1
T0
T1
0=
