8
7
6
5
4
2
3
1
80331 DDR DIMM CUSTOMER REFERENCE BOARD D
D
TABLE OF CONTENTS BLOCK DIAGRAM
PAGE 2
80331 - PRIMARY AND SECONDARY PCI
PAGE 3
80331 - DDR / PBI / JTAG / UART / I2C
PAGE 4
80331 - POWER / GROUND
PAGE 5
PRIMARY PCI BUS - EDGE CONNECTOR
PAGE 6
SECONDARY PCI BUS - SLOT
PAGE 7
DDR333 SERIES TERMINATION
PAGE 8
DDR333 DIMM CONNECTOR
PAGE 9
C
DDR333 TERMINATION
PAGE 10
PBI FLASH INTERFACE / RESET STRAPS
PAGE 11
CPLD / HEX DISPLAY
PAGE 12
I2C / UART
PAGE 13
VOLTAGE REGULATORS
PAGE 14
DDR BATTERY BACKUP
PAGE 15
MICTOR CONNECTORS
PAGE 16
REVISION HISTORY
PAGE 17
B
INFORMATION IN THIS DOCUMENT IS PROVIDED IN CONNECTION WITH INTEL® PRODUCTS. NO LICENSE, EXPRESS OR IMPLIED, BY ESTOPPEL OR OTHERWISE, TO ANY INTELLECTUAL PROPERTY RIGHTS IS GRANTED BY THIS DOCUMENT. EXCEPT AS PROVIDED IN INTEL'S TERMS AND CONDITIONS OF SALE FOR C SUCH PRODUCTS, INTEL ASSUMES NO LIABILITY WHATSOEVER, AND INTEL DISCLAIMS ANY EXPRESS OR IMPLIED WARRANTY, RELATING TO SALE AND/OR USE OF INTEL PRODUCTS INCLUDING LIABILITY OR WARRANTIES RELATING TO FITNESS FOR A PARTICULAR PURPOSE, MERCHANTABILITY, OR INFRINGEMENT OF ANY PATENT, COPYRIGHT OR OTHER INTELLECTUAL PROPERTY RIGHT. Intel products are not intended for use in medical, life saving, life sustaining applications. Intel may make changes to specifications and product descriptions at any time, without notice. Designers must not rely on the absence or characteristics of any features or instructions marked “reserved” or “undefined.” Intel reserves these for future definition and shall have no responsibility whatsoever for conflicts or incompatibilities arising from future changes to them. The 80331 DDR DIMM Customer Reference Board may contain design defects or errors known as errata which may cause the product to deviate from published specifications. Current characterized errata are available on request. MPEG is an international standard for video compression/decompression promoted by ISO. Implementations of MPEG CODECs, or MPEG enabled platforms may require licenses from various entities, including Intel Corporation. This schematic is furnished under license and may only be used or copied in accordance with the terms of the license. The information in this manual is furnished for informational use only, is subject to change without notice, and should not be construed B as a commitment by Intel Corporation. Intel Corporation assumes no responsibility or liability for any errors or inaccuracies that may appear in this document or any software that may be provided in association with this document. Except as permitted by such license, no part of this document may be reproduced, stored in a retrieval system, or transmitted in any form or by any means without the express written consent of Intel Corporation. Contact your local Intel sales office or your distributor to obtain the latest specifications and before placing your product order. Copies of documents which have an ordering number and are referenced in this document, or other Intel literature may be obtained by calling 1-800-548-4725 or by visiting Intel's website at http://www.intel.com. AnyPoint, AppChoice, BoardWatch, BunnyPeople, CablePort, Celeron, Chips, CT Media, Dialogic, DM3, EtherExpress, ETOX, FlashFile, i386, i486, i960, iCOMP, InstantIP, Intel, Intel Centrino, Intel logo, Intel386, Intel486, Intel740, IntelDX2, IntelDX4, IntelSX2, Intel Create & Share, Intel GigaBlade, Intel InBusiness, Intel Inside, Intel Inside logo, Intel NetBurst, Intel NetMerge, Intel NetStructure, Intel Play, Intel Play logo, Intel SingleDriver, Intel SpeedStep, Intel StrataFlash, Intel TeamStation, Intel Xeon, Intel A XScale, IPLink, Itanium, MCS, MMX, MMX logo, Optimizer logo, OverDrive, Paragon, PC Dads, PC Parents, PDCharm, Pentium, Pentium II Xeon, Pentium III Xeon, Performance at Your Command, RemoteExpress, SmartDie, Solutions960, Sound Mark, StorageExpress, The Computer Inside., The Journey Inside, TokenExpress, VoiceBrick, VTune, and Xircom are trademarks or registered trademarks of Intel Corporation or its subsidiaries in the United States and other countries. *Other names and brands may be claimed as the property of others. Copyright © 2003, Intel Corporation
A
SHEET TITLE: DESIGN ENGINEER:
Copyright 2003, Intel Corporation 8
80331 DDR DIMM CRB
DESIGN NAME:
STORAGE COMPONENTS DIVISION 7
80331 CRB 6
5
4
DATE MODIFIED:
REVISION:
12-5-2003_8:37 3
2.0 2
ProtoB
SHEET 1
1
OF
17
8
D
7
6
5
4
2
3
1
80331 DDR DIMM CUSTOMER REFERENCE BOARD DDR SDRAM Battery Backup
Target Market y RAID Card y TCP/IP Offload Card y Low End NAS
C
D
C
DDR 333 HEX LED
Buzzer
Local Bus
B
B
Secondary PCI-X Bus (133MHz) 8 MB StrataFLASH
32 KB NV RAM
A
RS-232
Slot
80331
RS-232 I2C GPIOs
Primary PCI-X Bus (133MHz)
Edge Connector
JTAG
A
SHEET TITLE: DESIGN ENGINEER:
Copyright 2003, Intel Corporation 8
BLOCK DIAGRAM
DESIGN NAME:
STORAGE COMPONENTS DIVISION 7
80331 CRB 6
5
4
DATE MODIFIED:
REVISION:
12-5-2003_8:37 3
2.0 2
ProtoB
SHEET 1
2
OF
17
6
RP4A5
2
3
4
8.2K RP4A5 8.2K RP4A5 8.2K RP4A5 8.2K RP4A1
NO_POP=TRUE
1
2
3
4
8.2K RP4A1 8.2K RP4A1 8.2K RP4A1 8.2K
8 5%
NC
7 5%
NC
6 5%
S_C/BE1_N
5 5%
S_C/BE0_N
8.2K RP3A1
4
8 5%
S_C/BE7_N
7 5%
S_C/BE6_N
6 5%
S_C/BE5_N
5 5%
S_C/BE4_N
S_C/BE2_N
3
4
6 S_FRAME_N 5%
5 5% 8.2K NO_POP=TRUE RP3A2 1 8 5% 8.2K RP3A2 2 7 5% 8.2K RP3A2 3 6 5% 8.2K RP3A2 4 5 5% 8.2K NO_POP=TRUE RP3A3 1 8 5% 8.2K RP3A3 2 7 5% 8.2K RP3A3 3 6 5% 8.2K RP3A3 4 5 5% 8.2K
8.2K RP5A2 8.2K RP5A3
NO_POP=TRUE
1
S_IRDY_N 2 S_TRDY_N 3 S_DEVSEL_N 4 S_STOP_N
8.2K RP5A3 8.2K RP5A3 8.2K RP5A3 8.2K RP5A4
NO_POP=TRUE
1
S_LOCK_N 2 S_PERR_N 3 S_SERR_N 4 S_ACK64_N
8.2K RP5A4 8.2K RP5A4 8.2K RP5A4 8.2K RP5A5
NO_POP=TRUE
1
8.2K
S_REQ64_N 2
3
C
4
RP5A5 8.2K RP5A5 8.2K RP5A5 8.2K
1
RP4A2
7 S_AD46 5%
2
6 S_AD45 5%
3
5 S_AD44 5%
4
8.2K RP4A2 8.2K RP4A2 8.2K RP4A2 8.2K RP4A3
NO_POP=TRUE
8 S_AD43 5%
1
7 S_AD42 5%
2
6 S_AD41 5%
3
4
5 S_AD40 5%
8.2K RP4A3 8.2K RP4A3 8.2K RP4A3 8.2K RP4A4
NO_POP=TRUE
8 S_AD39 5%
1
7 S_AD38 5%
2
6 S_AD37 5%
3
4
5 S_AD36 5%
8.2K RP4A4 8.2K RP4A4 8.2K RP4A4 8.2K RP5A1
NO_POP=TRUE
8 S_AD35 5%
1
8.2K
7 S_AD34 5%
2
6 S_AD33 5%
3
5 S_AD32 5%
4
RP5A1 8.2K RP5A1 8.2K RP5A1 8.2K
8 S_AD63 5% S_AD63 S_AD62 S_AD61 S_AD60 S_AD59 S_AD58 S_AD57 S_AD56 S_AD55 S_AD54 S_AD53 S_AD52 S_AD51 S_AD50 S_AD49 S_AD48 S_AD47 S_AD46 S_AD45 S_AD44 S_AD43 S_AD42 S_AD41 S_AD40 S_AD39 S_AD38 S_AD37 S_AD36 S_AD35 S_AD34 S_AD33 S_AD32 S_AD31 S_AD30 S_AD29 S_AD28 S_AD27 S_AD26 S_AD25 S_AD24 S_AD23 S_AD22 S_AD21 S_AD20 S_AD19 S_AD18 S_AD17 S_AD16 S_AD15 S_AD14 S_AD13 S_AD12 S_AD11 S_AD10 S_AD9 S_AD8 S_AD7 S_AD6 S_AD5 S_AD4 S_AD3 S_AD2 S_AD1 S_AD0
7 S_AD62 5% 6 S_AD61 5% 5 S_AD60 5% 8 S_AD59 5% 7 S_AD58 5% 6 S_AD57 5% 5 S_AD56 5% 8 S_AD55 5% 7 S_AD54 5% 6 S_AD53 5% 5 S_AD52 5% 8 S_AD51 5% 7 S_AD50 5% 6 S_AD49 5% 5 S_AD48 5%
S_AD[63:0] 7/A7
S_C/BE[7:0]_N
S_PAR
7/B5 7/B5 7/B5 7/B5 7/B8 7/B8 7/B8 7/B8 7/B8 7/B7 7/B7 7/C1 7/A8 7/A5
1 33
R3A42 CR1206
5%
S_PAR
S_STOP_N
S_STOP_N
S_TRDY_N
S_TRDY_N
S_FRAME_N
S_FRAME_N
S_IRDY_N
S_IRDY_N
S_DEVSEL_N
S_DEVSEL_N
S_PERR_N
S_PERR_N
S_SERR_N
S_SERR_N
S_LOCK_N
S_LOCK_N
S_PCIXCAP
S_PCIXCAP
S_M66EN
S_M66EN
S_PAR64
S_PAR64
S_ACK64_N
S_ACK64_N
S_REQ64_N
S_REQ64_N
S_RST_N
7/C5
S_C/BE7_N S_C/BE6_N S_C/BE5_N S_C/BE4_N S_C/BE3_N S_C/BE2_N S_C/BE1_N S_C/BE0_N
F26 D28 E28 C28 E29 F29 G29 E26 E27 R21
S_REQ0_N S_REQ1_N S_REQ2_N S_REQ3_N
7/D4,13/B8
NC NC NC
U8 NC_U8 W8 NC_W8 T8 NC_T8
PART 8 OF 9
80331 IOP PART 1 OF 9 SECONDARY PCI-X BUS (IOP BUS)
80331 IOP PRIMARY PCI-X BUS
S_C/BE7_N S_C/BE6_N S_C/BE5_N S_C/BE4_N S_C/BE3_N S_C/BE2_N S_C/BE1_N S_C/BE0_N S_PAR S_STOP_N S_TRDY_N S_FRAME_N S_IRDY_N S_DEVSEL_N S_PERR_N S_SERR_N S_LOCK_N
P_PAR P_STOP_N P_TRDY_N P_FRAME_N P_IRDY_N P_DEVSEL_N P_PERR_N P_SERR_N P_LOCK_N
S_PCIXCAP
P_M66EN P_PAR64 P_ACK64_N P_REQ64_N VSS NC_H13 NC_V8 HPI_N P_INTA_N P_INTB_N P_INTC_N P_INTD_N P_GNT_N NC_K5 NC_G12 P_IDSEL NC_K2 NC_H12 NC_F11 NC_H11 NC_T4 P_REQ_N
U27 S_INTA_N U28 S_INTB_N T24 S_INTC_N R23 S_INTD_N
S_INTB_N S_INTC_N S_INTD_N
R2D12
5%
16/D8 12/C8 7/C8
NC 33.2 S_CLKO_MICTOR S_CLKO_CPLD
1%
R2D10 33.2
S_CLKO_SLOT
1%
R2D5 33.2
R2D8 33.2
S_CLKO3_R S_CLKO_MICTOR_R S_CLKO_CPLD_R S_CLKO_SLOT_R
1%
1%
S_CLKOUT_R
G25 G27
NC_H7 NC_H9 NC_H8 NC_J8 NC_F7 NC_E7 P_CLK
S_CLKOUT S_CLKIN
S_RCOMP T29 S_RCOMP
R2D7 33.2
H23 S_CLKO3 F25 S_CLKO2 G24 S_CLKO1 H24 S_CLKO0
S_CLKIN
P_AD63 P_AD62 P_AD61 P_AD60 P_AD59 P_AD58 P_AD57 P_AD56 P_AD55 P_AD54 P_AD53 P_AD52 P_AD51 P_AD50 P_AD49 P_AD48 P_AD47 P_AD46 P_AD45 P_AD44 P_AD43 P_AD42 P_AD41 P_AD40 P_AD39 P_AD38 P_AD37 P_AD36 P_AD35 P_AD34 P_AD33 P_AD32 P_AD31 P_AD30 P_AD29 P_AD28 P_AD27 P_AD26 P_AD25 P_AD24 P_AD23 P_AD22 P_AD21 P_AD20 P_AD19 P_AD18 P_AD17 P_AD16 P_AD15 P_AD14 P_AD13 P_AD12 P_AD11 P_AD10 P_AD9 P_AD8 P_AD7 P_AD6 P_AD5 P_AD4 P_AD3 P_AD2 P_AD1 P_AD0 P_C/BE7_N P_C/BE6_N P_C/BE5_N P_C/BE4_N P_C/BE3_N P_C/BE2_N P_C/BE1_N P_C/BE0_N
U25 S_GNT3_N P22 S_GNT2_N B24 S_GNT1_N A23 S_GNT0_N
S_INTA_N
2
2
5%
7/D8,13/B8
S_GNT0_N
1
1
NO_POP=TRUE R2D1 8200
2
5%
1
NO_POP=TRUE R2D3 8200
NO_POP=TRUE R2D13 8200
1
5%
2
NO_POP=TRUE R2D2 8200
7/D4,13/B8
AA1 NC_AA1 U6 NC_U6 U5 NC_U5 V7 NC_V7 W7 NC_W7
N25 S_REQ0_N F28 S_REQ1_N E21 S_REQ2_N K25 S_REQ3_N
NC NC NC
+3_3V
7/D8,13/B8
NC NC NC NC NC
R25 NC_R25 R22 S_RST_N
NC
S_RST_N
7/C5
1_5V
U3E3
C20 S_M66EN K29 S_PAR64 J28 S_ACK64_N J29 S_REQ64_N
S_REQ0_N
7/C8
L27 L26 K28 K27 D27 C27 H17 H20
U3E3
LD_1
NC_K6
LD_8
2 100
B
+3_3V
7/A7
L29 S_AD63 M26 S_AD62 M28 S_AD61 M29 S_AD60 N27 S_AD59 N29 S_AD58 N28 S_AD57 P29 S_AD56 P27 S_AD55 P26 S_AD54 R29 S_AD53 R28 S_AD52 R26 S_AD51 T27 S_AD50 T26 S_AD49 U29 S_AD48 J22 S_AD47 J23 S_AD46 J25 S_AD45 J26 S_AD44 K24 S_AD43 K22 S_AD42 L22 S_AD41 L24 S_AD40 L23 S_AD39 M22 S_AD38 M23 S_AD37 M25 S_AD36 N22 S_AD35 N24 S_AD34 P24 S_AD33 P23 S_AD32 A21 S_AD31 B21 S_AD30 A22 S_AD29 C22 S_AD28 D22 S_AD27 B23 S_AD26 C23 S_AD25 A24 S_AD24 D24 S_AD23 A25 S_AD22 C25 S_AD21 D25 S_AD20 A26 S_AD19 B26 S_AD18 C26 S_AD17 B27 S_AD16 G18 S_AD15 H18 S_AD14 F19 S_AD13 G19 S_AD12 H19 S_AD11 E20 S_AD10 F20 S_AD9 D21 S_AD8 G21 S_AD7 H21 S_AD6 F22 S_AD5 G22 S_AD4 H22 S_AD3 E23 S_AD2 F23 S_AD1 E24 S_AD0
P_RCOMP
Y1 R1 P4 P3 P1 N1 N2 N3 M1 M2 M4 L1 L3 L4 K1 J1 J2 R8 R7 R5 P6 P7 P8 N5 N6 N8 M5 M7 M8 L6 L7 L8 K8 B10 C10 A9 B9 D9 A8 C8 D8 B7 C7 A6 B6 D6 A5 C5 A4 B3 C3 C2 D3 D2 D1 E4 F4 F2 F1 G3 G2 G1 H4 H3 H1
P_AD63 P_AD62 P_AD61 P_AD60 P_AD59 P_AD58 P_AD57 P_AD56 P_AD55 P_AD54 P_AD53 P_AD52 P_AD51 P_AD50 P_AD49 P_AD48 P_AD47 P_AD46 P_AD45 P_AD44 P_AD43 P_AD42 P_AD41 P_AD40 P_AD39 P_AD38 P_AD37 P_AD36 P_AD35 P_AD34 P_AD33 P_AD32 P_AD31 P_AD30 P_AD29 P_AD28 P_AD27 P_AD26 P_AD25 P_AD24 P_AD23 P_AD22 P_AD21 P_AD20 P_AD19 P_AD18 P_AD17 P_AD16 P_AD15 P_AD14 P_AD13 P_AD12 P_AD11 P_AD10 P_AD9 P_AD8 P_AD7 P_AD6 P_AD5 P_AD4 P_AD3 P_AD2 P_AD1 P_AD0
U3 T3 U2 U1 A7 D5 B4 E1
P_C/BE7_N P_C/BE6_N P_C/BE5_N P_C/BE4_N P_C/BE3_N P_C/BE2_N P_C/BE1_N P_C/BE0_N
P_AD[63:0] 6/A7
C P_C/BE[7:0]_N 6/A8
P_PAR P_STOP_N P_TRDY_N P_FRAME_N P_IRDY_N P_DEVSEL_N
C4 G6 H10 E6 F5 G5 J4 J5 J7 E3 R2 H6 G11 W4 H13 V8 AA8 W3 V5 V4 V2 R4 K5 G12 K3 K2 H12 F11 H11 T4 T6
P_PERR_N P_SERR_N P_LOCK_N P_M66EN P_PAR64 P_ACK64_N P_REQ64_N
6/B5
+3_3V
6/B5 6/B5 6/B5 6/B8 6/B8 6/B8 6/B8 6/B8 6/B8 6/C2 6/A8 6/A5
B
HPI_N
NC NC
13/B8
6/D5 P_INTA_N P_INTB_N
6/D8 P_INTC_N
6/D5
P_INTD_N P_GNT_N_A0
NC
P_GNT_N_B0
NO_POP=TRUE 0
5%
2
1
0
5% 2
1
6/D8
P_GNT_N
R3E2
R7R2
6/C5
P_IDSEL
6/C5
NC NC NC
P_REQ_N_B0
NC
P_REQ_N_A0
H7 H9 H8 J8 F7 E7 G9
NC NC NC NC NC NC
K6
NC
V1
P_RCOMP
1%
R3C8 1
A
D
NO_POP=TRUE 5%
0
2
0
2
1
R7R1
1
R3E3
5%
P_REQ_N
P_CLK
6/C8
6/C8
1 R4D6 2 100
1
7 5%
8.2K RP5A2
8 S_AD47 5%
8200
8.2K RP3A1
3 NO_POP=TRUE
S_C/BE3_N
+1_5V NO_POP=TRUE
2
+3_3VPCI
8.2K RP3A1
2
8 5%
8.2K RP5A2
1
5%
RP3A1
1
2
3
R2D15
1
2
D
RP5A2
NO_POP=TRUE
NO_POP=TRUE
4
1
+3_3VPCI
Place Resitor Packs near PCI Connector NO_POP RPACKS
5 +3_3VPCI
7 +3_3VPCI
8
A A0/B0 Routing of REQ/GNT
GND
GND
GND
A0 silicon
B0 silicon
R83
Populate
Don't Populate
R85
Don't Populate
Populate
R84
Don't Populate
Populate
R82
Populate
Don't Populate
SHEET TITLE: DESIGN ENGINEER:
Copyright 2003, Intel Corporation 8
80331 PRIMARY AND SECONDARY PCI
DESIGN NAME:
STORAGE COMPONENTS DIVISION 7
80331 CRB 6
5
4
DATE MODIFIED:
REVISION:
12-5-2003_8:37 3
2.0 2
ProtoB
SHEET 1
3
OF
17
8
7
6
5
4
2
3
PBI INTERFACE
DDR INTERFACE DDR_I2C_SCL
U0_TXD
13/B7
U0_CTS_N
1000 5%
GND
GND
DDRDRVCRES AC29 DDRDRVCRES DDRSLWCRESAC28
DDRSLWCRES
2
13/B7
U1_CTS_N
1%
13/B7
PBI_ALE_R PBI_OE_N PBI_WE_N
AA26 PCE0_N AA25 PCE1_N
PBI_CE0_N PBI_CE1_N
11/A8,12/C8,16/C6
1
11/C6,12/C8,16/C6 11/C6,12/C8,16/C6 DDRCRES0
11/C8,16/C6
AC27 DDRCRES0
+2_5V
12/C8,16/C6,16/C6
100
PART 3 OF 9
2
PBI_A[2:0] 11/D7,16/D5
C6P6 0.1UF
R4D3
100
PBI_AD[15:0] 11/D4,12/C8,16/D8
AE1 DM[0] AG5 DM[1] AJ9 DM[2] AJ13 DM[3] AJ19 DM[4] AE21 DM[5] AG25 DM[6] AE27 DM[7] AH15 DM[8]
DDRVREF
0
16V
2
C6P8 0.1UF 16V
DDR SDRAM INTERFACE
1
PBI_A[22:16] 11/D7,12/B8,16/D5
+3_3V
GND
GND
+3_3V
1000
10K
DUT_TDO
13
14
MR_RESET_N
15
16
17
18
19
20
1 2
1 2
1
1
1 2
2
2
5%
R4D7
1
12
21500 5%
R9N4
1
5%
1 31.6K
NO_POP=TRUE
GND
1%
GND
MR_N
R6E2
1
GND
5 12.4K
VCC
GND 4 RST_IN
1
R6E1
2
1%
10
11
C5E6 0.1UF 16V
R5E2
1
16V
8
9
2
3
RESET_N
SOT23_5
C5E10 0.1UF
7
1%
1
R5E1
MR_RESET_N
6
DUT_TMS
2
1000
U6E1
2 PWRDELAY_N
5
NC
5%
R5E3 2
+3_3V
MAX6306UK29D3
A
4
DUT_TDI
DUT_TCK DUT_TDI DUT_TDO DUT_TMS DUT_TRST_N
Y2 TCK Y6 TDI AB3 TDO AB4 TMS AA5 TRST_N
+5V
1
PWR_OK
3
NC
PU_NC1 PU_NC2 PU_NC3
21500
LD_7
1
GND GND
2
DUT_TRST_N
NC
R4D5
1000
9
JTAG/MISC
2
1%
2
Q6E1
AB1 NC33 AA2 NC34 AA4 NC35
5%
R3E4 2 1 10K
D5E1
6
SI3441
1
Leave floating for production designs
+3_3V
1
1
2
1 2
1 2
1
2
2
1
5
0 NO_POP=TRUE
P1C1
8200
4
2
R4D4
5%
3
GND
DDR_VREF
0
DUT_TCK
8200
4
GND SN74LVC1G14
5%
3
8200
+3_3V
220
2
5%
5%
5
1
NO_POP=TRUE
U3E2 NC VCC
2
R4D8
8200
1
TRST_MR_N
R5P6 R5P3
The 80331 has weak internal pullups on the JTAG TDI, TMS, TRST_N signals
Y5 SPARE0 W6 SPARE1 T1 SPARE2 Y8 SPARE3
80331_RESET_N
NC
TRST_R_N
8200
74LVC2G08 GND;4 +3_3V;8
3
SOT143
5%
NO_POP=TRUE
8200
80331_RESET_N
RESET_N MR_N
GND
U3E3 AB6 VSS AA7 PWRGD/P_RST_N PART 7 OF W1 PWRDELAY_N
2 +3_3V
2
R5P4
5%
NO_POP=TRUE
7
8200
PWR_OK
5%
9/A8,9/D2,15/B3
U3E1 1
P_RST_N
NO_POP=TRUE
33.2 1% NO_POP=TRUE
8200
R3E1
P_RST_N
5%
6/C5
NO_POP=TURE
B
R5P2
R5P5
NO_POP=TRUE
R6R1
4
5%
R4D1
VCC
NO_POP=TRUE
GND
GND
NO_POP=TRUE
MAX811_EUS_T 1
8200
U4D1
8200
74LVC2G08 GND;4 +3_3V;8
R9N1
5%
+3_3V
NO_POP=TRUE
NC
6
5%
3
NO_POP=TRUE
C4D11 .01UF X7R CC0603
+3_3V
U3E1 5
R9N2
1
R9N3
+3_3V
9/A5,14/A7
R9N5
2
RESET LOGIC AND JTAG INTERFACE
DDR_LD_DQS0 NC
DDR_LD_DQS1
NC
DDR_LD_DQS2
NC
DDR_LD_DQS3
NC
DDR_LD_DQS4
NC
D
DDR_LD_DQS5
NC
DDR_LD_DQS6
NC
DDR_LD_DQS7
NC
DDR_LD_DQS8
8/C4
NC 8/B4
DDR_LD_CAS_N DDR_LD_RAS_N DDR_LD_WE_N DDR_M_RST_N DDR_LD_CS0_N DDR_LD_CS1_N
8/B4 9/B4 8/B4
NC NC
8/B4
DDR_LD_CKE0 DDR_LD_CKE1
DDR_LD_A0 DDR_LD_A1 DDR_LD_A2 DDR_LD_A3 DDR_LD_A4 DDR_LD_A5 DDR_LD_A6 DDR_LD_A7 DDR_LD_A8 DDR_LD_A9 DDR_LD_A10 DDR_LD_A11 DDR_LD_A12 DDR_LD_A13
8/B4 8/B4
DDR_LD_A[13:0] 8/D5
DDR_LD_BA0
8/B4
DDR_LD_BA1
8/B4
DDR_LD_DM[8:0] AC1
0.1UF
AC13 MA[0] AE12 MA[1] AC12 MA[2] AF11 MA[3] AG11 MA[4] AH10 MA[5] AH9 MA[6] AD7 MA[7] AJ10 MA[8] AC9 MA[9] AC18 MA[10] AC8 MA[11] AF5 MA[12] AD22 MA[13] AD18 BA[0] AD13 BA[1]
DDR_LD_DQS[8:0] 8/D6
16V
1
R4D2
C4D8
PBI_A16 PBI_A17 PBI_A18 PBI_A19 PBI_A20 PBI_A21 PBI_A22
W29 A16 Y27 A17 U21 A18 V22 A19 Y29 A20 Y28 A21 W22 A22
R3C3
13/B7
PBI_ALE
53.6
2
1%
PBI_AD0 PBI_AD1 PBI_AD2 PBI_AD3 PBI_AD4 PBI_AD5 PBI_AD6 PBI_AD7 PBI_AD8 PBI_AD9 PBI_AD10 PBI_AD11 PBI_AD12 PBI_AD13 PBI_AD14 PBI_AD15
V29 AD0 V28 AD1 W24 AD2 V23 AD3 T23 AD4 V26 AD5 T22 AD6 W23 AD7 W26 AD8 W27 AD9 T21 AD10 Y24 AD11 U24 AD12 V25 AD13 U22 AD14 Y22 AD15
LD_2
1
PBI_A0 PBI_A1 PBI_A2
Y25 A0 AA29 A1 W21 A2
C
R3C6
R6P1
PBI / GPIO
AA28 ALE V21 POE_N Y21 PWE_N
R3C4
1
13/A7
U1_RTS_N
AE4 DQS[0] AE3 DQS_N[0] AJ5 DQS[1] AJ4 DQS_N[1] AF9 DQS[2] AE9 DQS_N[2] AG13 DQS[3] AH13 DQS_N[3] AF19 DQS[4] AG19 DQS_N[4] AH23 DQS[5] AJ23 DQS_N[5] AJ26 DQS[6] AJ25 DQS_N[6] AE29 DQS[7] AF29 DQS_N[7] AG16 DQS[8] AF16 DQS_N[8] AC21 CAS_N AC19 RAS_N AD20 WE_N AH3 M_RST_N AE20 CS[0]_N AD23 CS[1]_N AC22 ODT[0] AB20 ODT[1] AG4 CKE[0] AH4 CKE[1]
2
U1_RXD
385
13/B7
1%
U0_RTS_N
845
13/B7
U1_TXD
PART 2 OF 9
U3E3
1
13/B7
AB28 DDRRES[1] AB29 DDRRES[2]
2
1000
13/C7
R3C7
U0_RXD
5%
SCD1
2
13/C7
1
D
9/D4,13/D3
SCL1
R3C5
AA23 SCL0 AB21 SCD0 AB22 SCL1 AC24 SCD1 AB26 GPIO[0]/U0_RXD AB27 GPIO[1]/U0_TXD AA21 GPIO[2]/U0_CTS_N AA22 GPIO[3]/U0_RTS_N AC26 GPIO[4]/U1_RXD AC25 GPIO[5]/U1_TXD AB23 GPIO[6]/U1_CTS_N AB24 GPIO[7]/U1_RTS_N
DDRRES1 DDRRES2
9/D4,13/D3
DDR_I2C_SDA
U3E3
1
LD_3
GND GND
AD5 DQ0 AD4 DQ1 AF3 DQ2 AG2 DQ3 AD2 DQ4 AD1 DQ5 AF1 DQ6 AF2 DQ7 AE7 DQ8 AF6 DQ9 AJ7 DQ10 AG7 DQ11 AD8 DQ12 AE6 DQ13 AH6 DQ14 AJ6 DQ15 AG8 DQ16 AJ8 DQ17 AG10 DQ18 AD11 DQ19 AH7 DQ20 AF8 DQ21 AD10 DQ22 AE10 DQ23 AH12 DQ24 AJ12 DQ25 AE13 DQ26 AD14 DQ27 AJ11 DQ28 AF12 DQ29 AF14 DQ30 AG14 DQ31 AF18 DQ32 AE18 DQ33 AG20 DQ34 AJ21 DQ35 AJ18 DQ36 AH18 DQ37 AJ20 DQ38 AH20 DQ39 AJ22 DQ40 AG22 DQ41 AG23 DQ42 AF23 DQ43 AH21 DQ44 AF21 DQ45 AJ24 DQ46 AH24 DQ47 AF24 DQ48 AF25 DQ49 AG26 DQ50 AG27 DQ51 AE24 DQ52 AE23 DQ53 AH26 DQ54 AH27 DQ55 AF28 DQ56 AE26 DQ57 AD29 DQ58 AD28 DQ59 AG28 DQ60 AF27 DQ61 AD25 DQ62 AD26 DQ63 AE15 CB[0] AF15 CB[1] AD17 CB[2] AC16 CB[3] AC15 CB[4] AC14 CB[5] AD16 CB[6] AE17 CB[7]
DDR_LD_DM0 DDR_LD_DM1 DDR_LD_DM2 DDR_LD_DM3 DDR_LD_DM4 DDR_LD_DM5 DDR_LD_DM6 DDR_LD_DM7 DDR_LD_DM8
C
8/C6
DDR_LD_DQ[63:0] 8/D8
DDR_LD_DQ0 DDR_LD_DQ1 DDR_LD_DQ2 DDR_LD_DQ3 DDR_LD_DQ4 DDR_LD_DQ5 DDR_LD_DQ6 DDR_LD_DQ7 DDR_LD_DQ8 DDR_LD_DQ9 DDR_LD_DQ10 DDR_LD_DQ11 DDR_LD_DQ12 DDR_LD_DQ13 DDR_LD_DQ14 DDR_LD_DQ15 DDR_LD_DQ16 DDR_LD_DQ17 DDR_LD_DQ18 DDR_LD_DQ19 DDR_LD_DQ20 DDR_LD_DQ21 DDR_LD_DQ22 DDR_LD_DQ23 DDR_LD_DQ24 DDR_LD_DQ25 DDR_LD_DQ26 DDR_LD_DQ27 DDR_LD_DQ28 DDR_LD_DQ29 DDR_LD_DQ30 DDR_LD_DQ31 DDR_LD_DQ32 DDR_LD_DQ33 DDR_LD_DQ34 DDR_LD_DQ35 DDR_LD_DQ36 DDR_LD_DQ37 DDR_LD_DQ38 DDR_LD_DQ39 DDR_LD_DQ40 DDR_LD_DQ41 DDR_LD_DQ42 DDR_LD_DQ43 DDR_LD_DQ44 DDR_LD_DQ45 DDR_LD_DQ46 DDR_LD_DQ47 DDR_LD_DQ48 DDR_LD_DQ49 DDR_LD_DQ50 DDR_LD_DQ51 DDR_LD_DQ52 DDR_LD_DQ53 DDR_LD_DQ54 DDR_LD_DQ55 DDR_LD_DQ56 DDR_LD_DQ57 DDR_LD_DQ58 DDR_LD_DQ59 DDR_LD_DQ60 DDR_LD_DQ61 DDR_LD_DQ62 DDR_LD_DQ63 DDR_LD_CB0 DDR_LD_CB1 DDR_LD_CB2 DDR_LD_CB3 DDR_LD_CB4 DDR_LD_CB5 DDR_LD_CB6 DDR_LD_CB7
AJ16 M_CK[0] AJ17 M_CK[0]_N AJ14 M_CK[1] AJ15 M_CK[1]_N AH17 M_CK[2] AG17 M_CK[2]_N
B
DDR_LD_CB[7:0] 8/B6
A DDR_CK0 DDR_CK0_N
DDR_CK1 DDR_CK1_N DDR_CK2 DDR_CK2_N
8/C2 8/C2
8/C2 8/C2 8/C2 8/C2
GND
SHEET TITLE: DESIGN ENGINEER:
Copyright 2003, Intel Corporation 8 $4I121
80331 - DDR / PBI / JTAG
DESIGN NAME:
STORAGE COMPONENTS DIVISION 7
80331 CRB 6
5
4
DATE MODIFIED:
REVISION:
12-5-2003_12:31 3
2.0 2
ProtoB
SHEET 1
4
OF
17
8
7
6
5
4
2
3
1
+3_3V
U3E3
C8P2 0.1UF 16V
C4E4
C6N4
C8N1
C6N5
C7N2
C8P1
C7N3
C3E4
C7N7
C3E1
C2D2
16V
16V
16V
16V
16V
16V
16V
16V
16V
16V
16V
0.1UF
0.1UF
0.1UF
0.1UF
0.1UF
0.1UF
0.1UF
0.1UF
0.1UF
0.1UF
0.1UF
C2C1 22UF X5R
C2D7
C4D3
22UF X5R
22UF X5R
1
C2E2
2
150UF POLYMER
NC NC NC NC NC NC NC NC NC NC NC NC NC NC NC NC
+1_5V
D
+3_3V GND
G14 NC_G14 F14 NC_F14 E12 NC_E12 D12 NC_D12 A11 NC_A11 A12 NC_A12 D14 NC_D14 C14 NC_C14 D16 NC_D16 C16 NC_C16 E18 NC_E18 D18 NC_D18 A18 NC_A18 B18 NC_B18 E17 NC_E17 F17 NC_F17
GND
PART 9/9 NC
F13 NC_F13 E13 NC_E13 C12 NC_C12 B12 NC_B12 C11 NC_C11 D11 NC_D11 E15 NC_E15 D15 NC_D15 C17 NC_C17 B17 NC_B17 D19 NC_D19 C19 NC_C19 A19 NC_A19 A20 NC_A20 F16 NC_F16 G16 NC_G16
+3_3V NC NC NC NC NC NC NC NC NC NC NC NC NC NC NC NC
AA24 VCC33_1 Y26 VCC33_2 W20 VCC33_3 V24 VCC33_4 U20 VCC33_5 U26 VCC33_6
H15 VCC15_H15 G15 VSS_G15 B15 VSS_B15 A16 VSS_A16
C3C8 0.1UF 16V
C6N3
C7R1
C6N6
C6R7
C8N2
C8R1
C2D3
C2C2
C4C8
C4C9
C2E1
16V
16V
16V
16V
16V
16V
16V
16V
16V
16V
16V
0.1UF
0.1UF
0.1UF
0.1UF
0.1UF
0.1UF
0.1UF
0.1UF
+1_35V
0.1UF
0.1UF
0.1UF
C3B1 22UF X5R
C3C6 22UF X5R
R20 VCC33_7 R24 VCC33_8 R27 VCC33_9 P21 VCC33_10 N20 VCC33_11 N23 VCC33_12 N26 VCC33_13 M21 VCC33_14 M27 VCC33_15 L20 VCC33_16 L25 VCC33_17 K17 VCC33_18 K19 VCC33_19 K21 VCC33_20 J18 VCC33_21 J20 VCC33_22 J24 VCC33_23 J27 VCC33_24 H26 VCC33_25 G23 VCC33_26 F21 VCC33_27 D26 VCC33_28 C21 VCC33_29 C24 VCC33_30 C29 VCC33_31
A15 VCC15_A15 A14 VSS_A14
C4C3 22UF X5R
GND
GND
GND
+1_5V
1% R7P1
0.1UF 16V
VCC_PLL1_L
4.7UH
0.5
C5P2
C6P9
C5D6
C4D10
C4D9
16V
16V
16V
16V
16V
0.1UF
0.1UF
0.1UF
0.1UF
C5D5
C4D7
0.1UF
10UF X5R
2
C6P7
1
C
C7P1
22UF X5R
AJ27 VSS_1 AH2 VSS_2 AH5 VSS_3 AH8 VSS_4 AH14 VSS_5 AH19 VSS_6 AH22 VSS_7 AH25 VSS_8 AH28 VSS_9 AG1 VSS_10 AG6 VSS_11 AG9 VSS_12 AG12 VSS_13 AG15 VSS_14 AG18 VSS_15 AG21 VSS_16 AG24 VSS_17 AG29 VSS_18 AF7 VSS_19 AE2 VSS_20 AE5 VSS_21 AE8 VSS_22 AE11 VSS_23 AE14 VSS_24 AE16 VSS_25 AE19 VSS_26 AE22 VSS_27 AE25 VSS_28 AE28 VSS_29 AD3 VSS_30 AD9 VSS_31 AD15 VSS_32 AD21 VSS_33 AD27 VSS_34 AC4 VSS_35 AC7 VSS_36 AC11 VSS_37 AC17 VSS_38 AC23 VSS_39 AC2 VSS_40 AB2 VSS_41 AB5 VSS_42 AB8 VSS_43 AB10 VSS_44 AB12 VSS_45 AB14 VSS_46 AB16 VSS_47 AB18 VSS_48 AB25 VSS_50 AA3 VSS_52 AA6 VSS_53 AA9 VSS_54 AA11 VSS_55 AA13 VSS_56 AA15 VSS_57 AA17 VSS_58 AA19 VSS_59 AA27 VSS_60 Y3 VSS_61 Y4 VSS_62 Y7 VSS_63 Y10 VSS_64 Y12 VSS_65 Y14 VSS_66 Y16 VSS_67 Y18 VSS_68 Y20 VSS_69 Y23 VSS_70 W2 VSS_71 W9 VSS_72 W11 VSS_73 W13 VSS_74 W15 VSS_75 W17 VSS_76 W19 VSS_77 W25 VSS_78 W28 VSS_79 V6 VSS_80 V10 VSS_81 V12 VSS_82 V14 VSS_83 V16 VSS_84 V18 VSS_85 V20 VSS_86 V27 VSS_87 U4 VSS_88 U9 VSS_89 U11 VSS_90 U13 VSS_91 U15 VSS_92 U17 VSS_93 U19 VSS_94 U23 VSS_95 T2 VSS_96 T5 VSS_97 T7 VSS_98 T10 VSS_99 T12 VSS_100 T14 VSS_101 T16 VSS_102 T18 VSS_103 T20 VSS_104 T25 VSS_105 T28 VSS_106 R9 VSS_107 R11 VSS_108 R13 VSS_109 R17 VSS_110 R19 VSS_111 P2 VSS_112 P5 VSS_113
U3E3
PART 5 OF 9 W5 VCC33_32 V3 VCC33_33 U7 VCC33_34 R3 VCC33_35 R6 VCC33_36 M3 VCC33_37 M6 VCC33_38 L5 VCC33_39 J3 VCC33_40 H5 VCC33_41 G10 VCC33_42 F3 VCC33_43 F6 VCC33_44 E9 VCC33_45 D4 VCC33_46 C1 VCC33_47 C6 VCC33_48 C9 VCC33_49
LD_5
22UF X5R
+1_5V +1_5V GND
1%R6R3
4.7UH
2
1
VCC_PLL2_L
0.5
+1_5V
C6R4
+2_5V
+2_5V
+1_35V 22UF X5R
C6P2 0.1UF 16V
C6P4
C6P1
C4C6
C4D2
C4D6
C4D1
C4C5
C7N4
C6N2
C7N1
C3C5
C3C3
16V
16V
16V
16V
16V
16V
16V
16V
16V
16V
16V
16V
0.1UF
0.1UF
0.1UF
0.1UF
0.1UF
0.1UF
0.1UF
0.1UF
0.1UF
0.1UF
0.1UF
0.1UF
C4D5
Y9 VCC13_1 Y11 VCC13_2 Y13 VCC13_3 W10 VCC13_4 W12 VCC13_5 V13 VCC13_6 U12 VCC13_7
C3C2
22UF X5R
22UF X5R
VCC_PLL1
M19 VCC_PLL1
VSSA1
M18 VSSA1
VCC_PLL2
M11 VCC_PLL2
VSSA2
M12 VSSA2
GND
B
L15
V9 VCC15B_1 U10 VCC15B_2 T9 VCC15B_3 R10 VCC15B_4 P9 VCC15B_5 N10 VCC15B_6 M9 VCC15B_7 L10 VCC15B_8 K9 VCC15B_9 K10 VCC15B_10 K11 VCC15B_11 K13 VCC15B_12 J10 VCC15B_13 J12 VCC15B_14
U3E3
VSS_L15
K15 VSS_K15
+1_5V
VCC_PLL4
R15 VCC_PLL4
VSSA4
R16 VSSA4
VCC_PLL5
P13 VCC_PLL5
VSSA5
P14 VSSA5
+1_5V 1%R7N1
4.7UH
2
1
VCC_PLL4_L
0.5
C7N6
AJ3 VCCDDR_1 AH11 VCCDDR_2 AH16 VCCDDR_3 AF4 VCCDDR_4 AF10 VCCDDR_5 AF13 VCCDDR_6 AF17 VCCDDR_7 AF20 VCCDDR_8 AF22 VCCDDR_9 AF26 VCCDDR_10 AD6 VCCDDR_11 AD12 VCCDDR_12 AD19 VCCDDR_13 AD24 VCCDDR_14 AC10 VCCDDR_15 AC20 VCCDDR_16 AB9 VCCDDR_17 AB11 VCCDDR_18 AB13 VCCDDR_19 AB15 VCCDDR_20 AB17 VCCDDR_21 AB19 VCCDDR_22 AB7 VCCDDR_23 AA10 VCCDDR_24 AA12 VCCDDR_25 AA14 VCCDDR_26 AA16 VCCDDR_27 AA18 VCCDDR_28 AA20 VCCDDR_29
22UF X5R
C5E4 0.1UF 16V
C5R1
C5R3
C5E5
C6E2
C5P3
C6R2
C5E3
C5D9
C5R2
C2D5
C2D8
C3E3
C3D1
16V
16V
16V
16V
16V
16V
16V
16V
16V
16V
16V
16V
16V
0.1UF
0.1UF
0.1UF
0.1UF
0.1UF
0.1UF
0.1UF
0.1UF
0.1UF
0.1UF
0.1UF
0.1UF
0.1UF
+1_5V
1%R6R2
4.7UH
GND
2
VCC_PLL5_L
1
0.5 +1_5V
C6R3 GND
22UF X5R
A C6R1 1UF X5R 10V
C7N8
C4E2
1UF X5R 10V
1UF X5R 10V
C4E1 10UF X5R
C5D8 10UF X5R
C2D4 10UF X5R
D
U3E3 PART 6 OF 9
C3E2
PART 4 OF 9
LD_4
Y15 VCC15C_1 Y17 VCC15C_2 Y19 VCC15C_3 W14 VCC15C_4 W16 VCC15C_5 W18 VCC15C_6 V15 VCC15C_7 V17 VCC15C_8 V19 VCC15C_9 U14 VCC15C_10 U16 VCC15C_11 U18 VCC15C_12 T11 VCC15C_13 T13 VCC15C_14 T15 VCC15C_15 T17 VCC15C_16 T19 VCC15C_17 R12 VCC15C_18 R14 VCC15C_19 R18 VCC15C_20 P11 VCC15C_21 P15 VCC15C_22 P17 VCC15C_23 P19 VCC15C_24 N12 VCC15C_25 N14 VCC15C_26 N16 VCC15C_27 N18 VCC15C_28 M13 VCC15C_29 M15 VCC15C_30 M17 VCC15C_31 L12 VCC15C_32 L18 VCC15C_33
+1_5V
J14 VCC15E_1 J16 VCC15E_2 E14 VCC15E_3 E16 VCC15E_4 C13 VCC15E_5 C18 VCC15E_6 A13 VCC15E_7
LD_6
P10 VSS_114 P12 VSS_115 P16 VSS_116 P18 VSS_117 P20 VSS_118 P25 VSS_119 P28 VSS_120 N4 VSS_121 N7 VSS_122 N9 VSS_123 N11 VSS_124 N13 VSS_125 N15 VSS_126 N17 VSS_127 N19 VSS_128 N21 VSS_129 M10 VSS_130 M14 VSS_131 M16 VSS_132 M20 VSS_133 M24 VSS_134 L2 VSS_135 L9 VSS_136 L11 VSS_137 L13 VSS_138 L14 VSS_139 L16 VSS_140 L17 VSS_141 L19 VSS_142 L21 VSS_143 L28 VSS_144 K4 VSS_145 K7 VSS_146 K12 VSS_147 K14 VSS_148 K16 VSS_149 K18 VSS_150 K20 VSS_151 K23 VSS_152 K26 VSS_153 J6 VSS_154 J9 VSS_155 J11 VSS_156 J13 VSS_157 J15 VSS_158 J17 VSS_159 J19 VSS_160 J21 VSS_161 A27 VSS_216 A17 VSS_215 A10 VSS_214 A3 VSS_213 B28 VSS_212 B25 VSS_211 B22 VSS_210 B20 VSS_209 B19 VSS_208 B16 VSS_207 B14 VSS_206 B13 VSS_205 B11 VSS_204 B8 VSS_203 B5 VSS_202 B2 VSS_201 C15 VSS_200 D29 VSS_199 D23 VSS_198 D20 VSS_197 D17 VSS_196 D13 VSS_195 D10 VSS_194 D7 VSS_193 E25 VSS_192 E22 VSS_191 E19 VSS_190 E11 VSS_189 E10 VSS_188 E8 VSS_187 E5 VSS_186 E2 VSS_185 F27 VSS_184 F24 VSS_183 F18 VSS_182 F15 VSS_181 F12 VSS_180 F10 VSS_179 F9 VSS_178 F8 VSS_177 G28 VSS_176 G26 VSS_175 G20 VSS_174 G17 VSS_173 G13 VSS_172 G8 VSS_171 G7 VSS_170 G4 VSS_169 H29 VSS_168 H28 VSS_167 H27 VSS_166 H25 VSS_165 H16 VSS_164 H14 VSS_163 H2 VSS_162 AC3 VSS_217 AC5 VSS_218 AC6 VSS_219 AG3 VSS_220
C
B
A
V11 VCC15F_1
GND
10UF X5R
GND
SHEET TITLE: DESIGN ENGINEER:
Copyright 2003, Intel Corporation 8
80331 POWER/GROUND
DESIGN NAME:
STORAGE COMPONENTS DIVISION 7
80331 CRB 6
5
4
DATE MODIFIED:
REVISION:
12-5-2003_8:37 3
2.0 2
ProtoB
SHEET 1
5
OF
17
8
7
6
5
4
2
3
1
+5V +5V +5V +3_3V
+12V
-12V
-12V
+12V
+3_3V
J1E3 C2E5 B1 NC
B2 B3
D
B4 B5 B6 3/B2 3/B2
P_INTB_N
B7
P_INTD_N
B8 B9 B10
NC
B11
NC
-12V
TRST_N
TCK
+12V
GND1
TMS
TDO
TDI
+5V1
+5V5
+5V2
INTA_N
INTB_N
INTC_N
INTD_N
+5V6
PRSNT1_N RSVD1
RSVD3 +3.3VIO3
PRSNT2_N
RSVD4
A1
NC
10UF X5R
A2 A3
C4E6
C2E8
C4E7
C8R4
C6R6
16V
16V
16V
16V
0.1UF
10UF X5R
0.1UF
0.1UF
C8R6
C8R5
22UF TANT
TANT 22UF
.01UF X7R CC0603
.01UF X7R CC0603
C2E6
0.1UF
C2E9
NC
D
A4 +3_3V A5
GND
A6
P_INTA_N
A7
P_INTC_N
GND
GND
3/B2 3/B2
A8 A9
C5E7
NC
A10 A11
10UF X5R
C2E3 10UF X5R
C2E7
C5R4
C3E5
C5R5
C6R5
C4E3
C5E8
C5E9
16V
16V
16V
16V
16V
16V
16V
16V
0.1UF
0.1UF
0.1UF
0.1UF
0.1UF
0.1UF
0.1UF
0.1UF
C8R2
C4E5
C8R3
C6R8
C7R3
16V
16V
16V
16V
16V
0.1UF
0.1UF
0.1UF
0.1UF
0.1UF
NC Route 3_3V_AUX as a 30 mil trace
Key B14
NC
B15 3/A1
B16
P_CLK
B17 3/B2
B18
P_REQ_N
B19 P_AD31
B20
P_AD29
B21 B22
C
P_AD27
B23
P_AD25
B24 B25 B26
P_C/BE3_N P_AD23
B27 B28
P_AD21
B29
P_AD19
B30 B31
P_AD17
B32 B33
P_C/BE2_N
B34 3/B2
B35
P_IRDY_N
B36 3/B2
B37
P_DEVSEL_N P_PCIXCAP
3/B2 3/B2
B38 B39
P_LOCK_N
B40
P_PERR_N
B41 3/B2
B42
P_SERR_N
B43
B
C3E6 0.1UF 16V
B44
P_C/BE1_N P_AD14
B45 B46
P_AD12 GND 3/B2
B47
P_AD10
B48 B49
P_M66EN
B50 B51 P_AD8
B52
P_AD7
B53 B54
P_AD5
B55
P_AD3
B56 B57 B58
P_AD1
B59 3/B2
P_ACK64_N
B60 B61 B62
A
GND
RSVD2
+3.3VAUX
GND4
RST_N
CLK
+3.3VIO4
GND5
GNT_N
REQ_N
GND15
+3.3VIO1
PME_N
AD31
AD30
AD29
+3.3V7
GND6
AD28
AD27
AD26
AD25
GND16 AD24
+3.3V1 CBE3_N
IDSEL
AD23
+3.3V8
GND7
AD22
AD21
AD20 GND17
AD19 +3.3V2
AD18
AD17
AD16
CBE2_N
+3.3V9 FRAME_N
GND8
GND18
IRDY_N
TRDY_N
+3.3V3 DEVSEL_N PCIXCAP LOCK_N
GND19 STOP_N +3.3V10
PERR_N
RSVD5
+3.3V4
RSVD6
SERR_N +3.3V5 CBE1_N AD14 GND10 AD12 AD10 M66EN GND2
GND20 PAR AD15 +3.3V11 AD13 AD11 GND21 AD09 GND13
GND3
GND14
AD08
CBE0_N
AD07 +3.3V6
+3.3V12 AD06
AD05
AD04
AD03
GND22
GND12
AD02
AD01
AD00
+3.3VIO2
+3.3VIO5
ACK64_N
REQ64_N
+5V3
+5V7
+5V4
+5V8
3_3V_AUX
A14
7/C5
A15
P_RST_N
GND
4/B8
+3_3V
+3_3V
A16 A17
P_GNT_N
3/B2
A18 A19
PCI_PME_N
A20
J1E3
7/C5
P_AD30
Key
Continued
A21 A22
B63
NC
P_AD28
B64 A23
P_AD26 P_C/BE6_N
B65
P_C/BE4_N
B66
A24 A25
P_AD24 B67
A26
P_IDSEL
3/B1
P_AD63
B68
P_AD61
B69
A27 A28
P_AD22
A29
P_AD20
B70 P_AD59
B71
P_AD57
B72
A30 A31
P_AD18
A32
P_AD16
B73 A33 A34
P_FRAME_N
P_AD55
B74
P_AD53
B75
3/B2
B76
A35 A36
P_TRDY_N
3/B2
P_AD51
B77
P_AD49
B78
A37 B79 P_STOP_N
A38
3/C2
P_AD47
B80
P_AD45
B81
A39 A40 A41
NC
B82
NC
P_AD43
B83
P_AD41
B84
A42 A43
P_PAR
A44
3/C2
B85
P_AD15 P_AD39
B86
P_AD37
B87
A45 A46
P_AD13 B88
A47
P_AD11 P_AD35
B89
P_AD33
B90
A48 A49
P_AD9 B91
A50
B92
NC
A51 A52
B93
NC
P_C/BE0_N
B94 A53 A54
P_AD6
A55
P_AD4
RSVD7
GND31
GND23
CBE7_N
CBE6_N
CBE5_N
CBE4_N
+3.3VIO9
GND24
PAR64
AD63
AD62
AD61
GND32
+3.3VIO6
AD60
AD59
AD58
AD57
GND33
GND25
AD56
AD55
AD54
AD53
+3.3VIO10
GND26
AD52
AD51
AD50
AD49
GND34
+3.3VIO7
AD48
AD47
AD46
AD45
GND35
GND27
AD44
AD43
AD42
AD41
+3.3VIO11
GND28
AD40
AD39
AD38
AD37
GND36
+3.3VIO8
AD36
AD35
AD34
AD33
GND37
GND29
AD32
RSVD8
RSVD10
RSVD9
GND38
GND30
RSVD11
A63 A64
P_C/BE7_N
A65
P_C/BE5_N
C
A66 A67
P_PAR64
3/B2
P_AD62
A68 A69 A70
P_AD60
A71
P_AD58
A72 A73
P_AD56
A74
P_AD54
A75 A76
P_AD52
A77
P_AD50
A78 A79
P_AD48
A80
P_AD46
A81 A82
P_AD44
A83
P_AD42
A84 A85
P_AD40
A86
P_AD38
B
A87 A88
P_AD36
A89
P_AD34
A90 P_AD32
A91 A92
NC
A93 A94
NC
PCI - EDGE CONNECTOR PART 2 of 2
A56 A57
P_AD2
A58
P_AD0
GND
GND
A59 P_REQ64_N
A60
3/B2
A61 A62
Key Continued PCI - EDGE CONNECTOR PART 1 of 2
A GND
P_AD[63:0] 3/C2 P_C/BE[7:0]_N 3/C2
SHEET TITLE: DESIGN ENGINEER:
Copyright 2003, Intel Corporation 8
PRIMARY PCI BUS - EDGE CONNECTOR
DESIGN NAME:
STORAGE COMPONENTS DIVISION 7
80331 CRB 6
5
4
DATE MODIFIED:
REVISION:
12-5-2003_8:37 3
2.0 2
ProtoB
SHEET 1
6
OF
17
6
5
1
B5 B6
GND
B7 B8
S_INTA_N
B9 NC
B10 B11
B14 B15
S_CLKO_SLOT
GND
B16
GND
B17 B18
S_REQ0_N
3/B6
B19 S_AD31
B20
S_AD29
B21 B22
C S_AD27
B23
S_AD25
B24 B25 B26
S_C/BE3_N S_AD23
B27 B28
+3_3V S_AD21 1500
S_AD19
2
B30
5%
B31 B32
S_C/BE2_N
B33
R7L1
1
S_AD17
B34 B35 B36
3/B6 3/B8
S_DEVSEL_N
B37
S_PCIXCAP
B38 B39
S_LOCK_N
3/B6
B40
S_PERR_N
3/B6
B41 B42
S_SERR_N
3/B6
+3_3V
B
B43
0.1UF
S_AD14
CR1206
B46
1
S_AD12
B47
S_AD10
B48
GND
33
R3A2
B45
5%
16V
3/B8
B44
S_C/BE1_N
C7L1 2
B49
S_M66EN
B50 B51 S_AD8
B52
S_AD7
B53 B54
S_AD5
B55
S_AD3
B56 B57
S_AD1
B58 B59
3/B7
INTC_N
INTD_N
+5V6
PRSNT1_N RSVD1
R2A3 2 4300
5%
5%
R2A1 2 4300
C8L1
16V
16V
0.1UF
RSVD2
S_INTB_N
A7
A9
22UF TANT
B60
S_ACK64_N
B61
A
B62
GND
C8L4
TANT 22UF
.01UF X7R CC0603
C2A8
S_INTD_N
GND
GND
3/B7,13/B8 3/A7,13/B8
C2A5
A11
C5A1
NC 10UF X5R
A10
RSVD4
10UF X5R
C5L1
C6L1
C6L2
C7L3
C7L2
C5L2
C8L3
C8L2
16V
16V
16V
16V
16V
16V
16V
16V
0.1UF
0.1UF
0.1UF
0.1UF
0.1UF
0.1UF
0.1UF
0.1UF
NC
GND +3.3VAUX RST_N
GNT_N
REQ_N
GND15
+3.3VIO1
PME_N
AD31
AD30
AD29
+3.3V7
GND6
AD28
AD27
AD26
AD25
GND16
CBE3_N
+3.3V8
GND7
AD22
AD21
A15
S_RST_N
6/C5 3/B8
S_GNT0_N
3/B7
A18 A19
PCI_PME_N
A20
J2A1
6/C5
S_AD30
Key
A22
S_AD28
A23
S_AD26
NC
S_C/BE6_N
B65
S_C/BE4_N
B66
A24 A25
S_AD24 B67
A26
S_SLOT_IDSEL
A27 S_AD22
A28
AD18
AD17
AD16
CBE2_N
A30
RSVD5 RSVD6
CBE1_N
A40 A41
GND14
AD08
CBE0_N
AD07
AD04
AD03
GND22
GND12
AD02
AD01
AD00
+3.3VIO2
+3.3VIO5
ACK64_N
REQ64_N
+5V3
+5V7
+5V4
+5V8
B75
3/B6
B76
3/C6
S_AD51
B77
S_AD49
B78
3/C6
S_AD47
B80
S_AD45
B81
NC
B82
NC
S_PAR
S_AD43
B83
S_AD41
B84
3/C8
B85
S_AD15 S_AD39
B86
S_AD37
B87
S_AD13 S_AD11 S_AD35
B89
S_AD33
B90
S_AD9
A49
B91
A50 NC
A51 A52
NC
S_C/BE0_N
B92 B93 B94
A53
AD06
AD05
S_AD53
A48
+3.3V12
+3.3V6
S_STOP_N
A47
AD09
GND3
B74
B88
GND13
GND2
S_TRDY_N
A46
GND21
M66EN
S_AD55
A45
AD11
AD10
S_FRAME_N
A44
AD13
AD12
B73
A43
+3.3V11
GND10
B72
A42
AD15
AD14
S_AD57
A39
PAR
+3.3V5
B71
B79
GND20
SERR_N
S_AD16
A38
+3.3V10
PERR_N
A32
S_AD59
A37
GND19
+3.3V4
S_AD18
A36
STOP_N
LOCK_N
B69
A35
TRDY_N
PCIXCAP
A31
A34
GND18
DEVSEL_N
S_AD61
S_AD17
FRAME_N
+3.3V3
B68
B70
A33
+3.3V9
IRDY_N
S_AD63
S_AD20
A29
GND17
+3.3V2
B63 B64
AD20
AD19
Continued
A21
IDSEL
AD23
3_3V_AUX
A17
AD24
+3.3V1
A14
A16
+3.3VIO4
GND5
GND8
.01UF X7R CC0603
A8
+3.3VIO3
GND4 CLK
C9L1
C2A6
0.1UF
GND GND
A6
RSVD3
PRSNT2_N
C4A2
16V
0.1UF
A5
1
B29
S_IRDY_N
3/B6
INTB_N
C4A3
16V
0.1UF
Key NC
3/A6
INTA_N
10UF X5R
C2A4
D
1%
16V
0.1UF
+5V5
+5V2
S0_TDI
10UF X5R
200
16V
0.1UF
+5V1
A4
-12V
+3_3VPCI
C2A3
TDI
S0_TMS
C4A1
+3_3VPCI
C2A2
TMS
TDO
A3
2
3/B7,13/B8
A2
R3A1
S_INTC_N
3/B7,13/B8
GND1
S0_TRST_N
1
B4
+12V
C2A1
1
1 5%
R2A2 2 4300
NC
TCK
A1
+12VPCI
B3
TRST_N
1
+3_3VPCI
D
B2
S0_TCK
-12V
2
3
+5VPCI
J2A1 B1
4
+3_3VPCI
+3_3VPCI
+12VPCI
+5VPCI
+3_3VPCI
+5VPCI -12V
5%
7
R8L1 2 4300
8
A54
S_AD6
A55
S_AD4
RSVD7
GND31
GND23
CBE7_N
CBE6_N
CBE5_N
CBE4_N
+3.3VIO9
GND24
PAR64
AD63
AD62
AD61
GND32
+3.3VIO6
AD60
AD59
AD58
AD57
GND33
GND25
AD56
AD55
AD54
AD53
+3.3VIO10
GND26
AD52
AD51
AD50
AD49
GND34
+3.3VIO7
AD48
AD47
AD46
AD45
GND35
GND27
AD44
AD43
AD42
AD41
+3.3VIO11
GND28
AD40
AD39
AD38
AD37
GND36
+3.3VIO8
AD36
AD35
AD34
AD33
GND37
GND29
AD32
RSVD8
RSVD10
RSVD9
GND38
GND30
RSVD11
A63 A64
S_C/BE7_N
A65
S_C/BE5_N
C
A66 A67
S_PAR64
3/B8
S_AD62
A68 A69 A70
S_AD60
A71
S_AD58
A72 A73
S_AD56
A74
S_AD54
A75 A76
S_AD52
A77
S_AD50
A78 A79
S_AD48
A80
S_AD46
A81 A82
S_AD44
A83
S_AD42
A84 A85
S_AD40
A86
S_AD38
B
A87 A88
S_AD36
A89
S_AD34
A90 S_AD32
A91 A92
NC
A93 A94
NC
PCI - 64B CONNECTOR PART 2 of 2
A56 A57
S_AD2
A58
S_AD0
GND
GND
A59 A60
S_REQ64_N
3/B7
A61
A
A62
Key Continued PCI - 64B CONNECTOR PART 1 of 2
GND
S_AD[63:0] 3/C5 S_C/BE[7:0]_N 3/C8
SHEET TITLE: DESIGN ENGINEER:
Copyright 2003, Intel Corporation 8
SECONDARY PCI-X BUS
DESIGN NAME:
STORAGE COMPONENTS DIVISION 7
80331 CRB 6
5
4
DATE MODIFIED:
REVISION:
12-5-2003_8:37 3
2.0 2
ProtoB
SHEET 1
7
OF
17
8
7
6
DDR_DQ[63:0]
DDR_LD_DQ[63:0]
5
4
2
3
1
9/D6,9/D4,10/D8
4/C1
D
DDR_LD_DQ63
22
R4C9
DDR_DQ63
DDR_LD_DQ62
22
5%
R4C10
DDR_DQ62
DDR_LD_DQ61
22
5%
R4C4
DDR_DQ61
DDR_LD_DQ60
22
5%
R4C3
DDR_DQ60
DDR_LD_DQ59
22
5%
R4C12
DDR_DQ59
DDR_LD_DQ58
22
5%
R4C11
DDR_DQ58
DDR_LD_DQ57
22
5%
R4C6
DDR_DQ57
22
5%
DDR_LD_DQ56
22
5%
R4C21
DDR_DQ55
DDR_LD_DQ54
22
5%
R4C19
DDR_DQ54
DDR_LD_DQ53
22
5%
R4C13
DDR_DQ53
DDR_LD_DQ52
22
5%
R4C14
DDR_DQ52
DDR_LD_DQ51
22
5%
R5C1
DDR_DQ51
DDR_LD_DQ50
22
5%
R4C20
DDR_DQ50
22
5%
DDR_LD_DQ48
22
5%
R4C15
DDR_DQ48
DDR_LD_DQ47
22
5%
R5C5
DDR_DQ47
DDR_LD_DQ46
22
5%
DDR_LD_DQ45
22
5%
A
R5C7
DDR_DQ46
R5C13
DDR_DQ45
5%
DDR_LD_DQ43
22
5%
R5C2
DDR_DQ43
DDR_LD_DQ42
22
5%
R5C3
DDR_DQ42
DDR_LD_DQ41
22
5%
R5C10
DDR_DQ41
R5C12
Place DDR Addr/CMD Series Resistors 0.25 to 0.5 inches of DIMM connector
DDR_LD_DQS8
22
R5C28
DDR_DQS8
DDR_LD_DQS7
22
5%
R4C8
DDR_DQS7
DDR_LD_DQS6
22
5%
R4C16
DDR_DQS6
DDR_LD_DQS5
22
5%
R5C6
DDR_DQS5
DDR_LD_DQS4
22
5%
R5C18
DDR_DQS4
DDR_LD_DQS3
22
5%
R6C12
DDR_DQS3
DDR_LD_DQS2
22
5%
R6C29
DDR_DQS2
R7C11
DDR_DQS1
DDR_LD_DQS1 DDR_LD_DQS0
22
5%
22
5%
R7C20
22
5%
R5C11
DDR_DQ40
DDR_LD_DQ39
22
5%
R5C16
DDR_DQ39
DDR_LD_DQ38
22
5%
R5C17
DDR_DQ38
DDR_LD_DQ37
22
5%
R5C22
DDR_DQ37
DDR_LD_DQ36
22
5%
DDR_LD_DQ35
22
DDR_LD_DQ34
22
DDR_LD_DQ33 DDR_LD_DQ32
9/C7,9/C4,10/C5 DDR_LD_A13
DDR_LD_A11
DDR_LD_A9
DDR_DQS0
5%
DDR_LD_DM6
22
5%
DDR_DM8
R4C7
DDR_DM7
R4C18
DDR_DM6
22
5%
R5C9
DDR_DM5
22
5%
R5C19
DDR_DM4
22
5%
R6C13
DDR_DM3
DDR_LD_DM2
22
5%
R6C28
DDR_DM2
DDR_LD_DM1
22
5%
R7C10
DDR_DM1
DDR_LD_DM0
22
5%
R7C19
DDR_DM0
R5C14
DDR_DQ35
5%
R5C15
DDR_DQ34
22
5%
R5C21
DDR_DQ33
22
5%
R5C20
DDR_DQ32
DDR_LD_DQ31
22
5%
R6C9
DDR_DQ31
DDR_LD_DQ30
22
5%
R6C8
DDR_DQ30
DDR_LD_DQ29
22
5%
R6C17
DDR_DQ29
DDR_LD_DQ28
22
5%
R6C18
DDR_DQ28
DDR_LD_DQ27
22
5%
R6C10
DDR_DQ27
DDR_LD_DQ26
22
5%
R6C11
DDR_DQ26
DDR_LD_DQ25
22
5%
R6C14
DDR_DQ25
DDR_LD_DQ24
22
5%
R6C15
DDR_DQ24
DDR_LD_DQ23
22
5%
R6C22
DDR_DQ23
DDR_LD_DQ22
22
5%
R6C24
DDR_DQ22
DDR_LD_DQ21
22
5%
R7C2
DDR_DQ21
DDR_LD_DQ20
22
5%
R7C3
DDR_DQ20
DDR_LD_DQ19
22
5%
R6C19
DDR_DQ19
DDR_LD_DQ18
22
5%
R6C20
DDR_DQ18
DDR_LD_DQ17
22
5%
R6C30
DDR_DQ17
DDR_LD_CB7
22
DDR_LD_DQ16
22
5%
R6C31
DDR_DQ16
DDR_LD_CB6
22
DDR_LD_DQ15
22
5%
R7C7
DDR_DQ15
DDR_LD_CB5
22
DDR_LD_DQ14
22
5%
R7C6
DDR_DQ14
DDR_LD_CB4
DDR_LD_DQ13
22
5%
R7C13
DDR_DQ13
DDR_LD_CB3
DDR_LD_DQ12
22
5%
R7C14
DDR_DQ12
DDR_LD_DQ11
22
5%
R7C5
DDR_DQ11
DDR_LD_DQ10
22
5%
R7C4
DDR_DQ10
DDR_LD_DQ9
22
5%
R7C9
DDR_DQ9
DDR_LD_DQ8
22
5%
R7C12
DDR_DQ8
DDR_LD_DQ7
22
5%
R7C18
DDR_DQ7
DDR_LD_DQ6
22
5%
R7C17
DDR_DQ6
DDR_LD_DQ5
22
5%
R7C21
DDR_DQ5
DDR_LD_DQ4
22
5%
R7C22
DDR_DQ4
DDR_LD_DQ3
22
5%
R7C15
DDR_DQ3
DDR_LD_DQ2
22
5%
R7C16
DDR_DQ2
DDR_LD_DQ1
22
5%
R7C23
DDR_DQ1
DDR_LD_DQ0
22
5%
R7C24
DDR_DQ0
DDR_A5
22R5C36
DDR_LD_A4
DDR_A4
4/A1
DDR_CK0
5%
22R5C37
22R4C26
DDR_333_CK0
9/C7
5%
C
DDR_A3
5%
DDR_LD_A1
DDR_A6
5%
22R5C38
4/A1
DDR_A2
DDR_CK0_N
22R4C25
DDR_CK1
22R4C28
DDR_333_CK0_N
9/C6
5%
5%
22R5C39
DDR_A1
5%
DDR_LD_DM3
5%
22R5C35
22R5C34
DDR_LD_A2
DDR_LD_DM4
DDR_DQ36
DDR_A7
5%
DDR_LD_A3
Place DDR Clock Series Resistors within 0.5 inches of 80331
DDR_A8
5%
22R5C32
5%
R5C29
DDR_LD_DM5
R5C23
DDR_A9
22R5C33
DDR_LD_A6 DDR_LD_A5
DDR_A10
5%
22R5C31 5%
9/D7,10/D5
22
DDR_A11
22 R6C2
DDR_LD_A8
DDR_DM[8:0]
DDR_A12
5%
5%
DDR_LD_DM[8:0]
DDR_LD_DM7
22 R5C4
22 R5C8
DDR_LD_A10
4/C2
22
DDR_A13
5%
DDR_LD_A7
DDR_LD_DM8
22 R7C8
DDR_LD_A12
5%
DDR_DQ44
DDR_LD_DQ40
DDR_A[13:0]
DDR_LD_A[13:0] 4/C1
DDR_DQ49
22
DDR_LD_DQ44
B
R4C17
9/D4,10/B5
4/D1
DDR_DQ56
DDR_LD_DQ55
DDR_LD_DQ49
C
R4C5
D DDR_DQS[8:0] DDR_LD_DQS[8:0]
22 R6C1
DDR_LD_A0
4/A1
DDR_A0
DDR_333_CK1
9/C3
5%
5% 4/A1
22R4C27
DDR_CK1_N
DDR_333_CK1_N
9/C4
5%
5% 4/D2
DDR_LD_CAS_N
22R6C26
DDR_CAS_N
4/A1
9/C3,10/C3
22R4C24
DDR_CK2
4/D2
DDR_LD_RAS_N
22R6C21
DDR_RAS_N
4/A1
9/C7,10/C3
22R4C23
DDR_CK2_N
DDR_LD_WE_N
22R6C23
DDR_WE_N
9/B4
DDR_333_CK2_N
9/B3
5%
5%
4/D2
DDR_333_CK2
5%
5%
9/C3,10/C3
5%
4/C1
22R6C16
DDR_LD_BA0
DDR_BA0
9/C3,10/C3
5%
4/C1
22 R6C6
DDR_LD_BA1
DDR_BA1
9/C3,10/C3
5%
B 4/D2
DDR_LD_CS0_N
22R6C25
DDR_CS0_N
9/C7,10/C3
5%
DDR_CB[7:0] 9/C7,9/C4,10/A5
DDR_LD_CB[7:0] 4/A1
4/D2
DDR_LD_CS1_N
22R6C27
DDR_CS1_N
9/C6,10/C3
5%
R5C26
DDR_CB7
5%
R5C27
DDR_CB6
5%
R6C7
DDR_CB5
22
5%
R6C5
DDR_CB4
22
5%
R5C24
DDR_CB3
DDR_LD_CB2
22
5%
R5C25
DDR_CB2
DDR_LD_CB1
22
5%
R6C3
DDR_CB1
DDR_LD_CB0
22
5%
R6C4
DDR_CB0
4/D2
DDR_LD_CKE0
22R5C30
DDR_CKE0
9/B4,10/B3
5%
4/C2
DDR_LD_CKE1
22R4C22
DDR_CKE1
9/B7,10/B3
5%
5%
A
5%
SHEET TITLE: DESIGN ENGINEER:
Copyright 2003, Intel Corporation 8
DDR333 SERIES TERMINATION
DESIGN NAME:
STORAGE COMPONENTS DIVISION 7
80331 CRB 6
5
4
DATE MODIFIED:
REVISION:
12-5-2003_8:37 3
2.0 2
ProtoB
SHEET 1
8
OF
17
8
7
6
5
4
2
3
1
+2_5V
CKE0_LATCH_FB
U5C1 5
C6C1 10UF X5R
C7C1 10UF X5R
C4C4 10UF X5R
C7C2
C4N1
C4B4
C6B3
C7B6
C3N1
C6N1
16V
16V
16V
16V
16V
16V
16V
0.1UF
0.1UF
0.1UF
0.1UF
0.1UF
0.1UF
4/B8,9/A8,15/B3
0.1UF
PWR_OK
6
U4C1
3
CKE0_LATCH DDR_CKE0
74LVC2G32 GND;4 +2_5V;8
5
3
6
74LVC2G08 GND;4 +2_5V;8
+2_5V
D
D +2_5V
+3_3V GND
DDR_I2C_SCL
J4C1
DDR_DM[8:0]
8/C5,10/D5
DDR_DQ1 DDR_DQ5 DDR_DM0 DDR_DQ6 DDR_DQ3 NC DDR_DQ13 DDR_DQ9 DDR_DM1
DDR_A[13:0] 8/D3,9/C4,10/C5
DDR_A13 DDR_DQ15 DDR_DQ14 DDR_DQ20 DDR_DQ21 DDR_CS1_N
8/B3,10/C3
DDR_DM2 DDR_CS0_N
8/B3,10/C3
DDR_DQ23 DDR_RAS_N
8/B3,10/C3
DDR_DQ18 DDR_DQ29 DDR_DQ24 DDR_DM3 DDR_DQ26 DDR_DQ31 DDR_CB[7:0]
8/B5,9/C4,10/A5
SCL SDA NC_90 VSS_12 DQ59 DQ58 DQS7 VDD_5 DQ57 DQ56 VDDID VSS_11 DQ51 DQ50 DQS6 VDDQ_6 CK2 CK2_N VSS_10 DQ49 DQ48 NC_71 VDD_4 DQ43 DQ42 DQS5 VSS_9 CAS_N DQ41 WE_N VDDQ_5 DQ40 DQ35 BA0 VSS_8 DQ34 DQS4 DQ33 VDDQ_4 DQ32
92 91 90 89 88 87 86 85 84 83 82 81 80 79 78 77 76 75 74 73 72 71 70 69 68 67 66 65 64 63 62 61 60 59 58 57 56 55 54 53
Q5C1
4/D5,13/D3 3
DDR_DQ[63:0] NC
8/D7,9/D6,10/D8 DDR_DQ0 DDR_DQ4 DDR_DQS0
DDR_DQS[8:0]
GND 8/D5,10/B5
DDR_DQ7 DDR_DQ2
NC DDR_DQ12 DDR_DQ8 DDR_DQS1 DDR_333_CK1 DDR_DQ11 DDR_DQ10
DDR_333_CK1_N
8/C1 8/C1
NC DDR_DQ16 DDR_DQ17 DDR_DQS2 DDR_CAS_N DDR_DQ22 DDR_WE_N
8/C3,10/C3
C
8/B3,10/C3
DDR_DQ19 DDR_DQ28 DDR_BA0 DDR_DQ25 DDR_DQS3 DDR_DQ27
DDR_A[13:0]
DDR_DQ30
DDR_CB[7:0]
8/B3,10/C3
8/D3,9/C7,10/C5 8/B5,9/C7,10/A5
KEY
DDR_333_CK0
8/C1
DDR_CB2 DDR_CB3 DDR_DQ36 DDR_DQ32 DDR_A3 DDR_DM4 DDR_DQ38 DDR_DQ34 DDR_A6 DDR_DQ44 DDR_A8 DDR_DQ40 DDR_DM5 DDR_A11 DDR_DQ46
B
DDR_A12 DDR_DQ43 NC DDR_CKE1
8/B3,10/B3
DDR_DQ55 DDR_DQ54 DDR_DM6 DDR_DQ49 DDR_DQ48
DDR_DQ58 DDR_DQ63 DDR_DM7
PNP_MMBT3906 2
Q4C1
1
DDR_DQ56 DDR_DQ60
3
DDR_BA1
52 51 50 49 48 47 46 45 44 43 42 41 40 39 38 37 36 35 34 33 32 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1
DDR_CB4
8/B3,10/C3
DDR_CB1 DDR_A0 DDR_DQS8 DDR_CB6 DDR_CB7 DDR_A1 DDR_A2 DDR_DQ37 DDR_DQ33 DDR_A4 DDR_DQS4 DDR_DQ39 DDR_DQ35 DDR_A5 DDR_DQ45 DDR_A7 DDR_DQ41 DDR_A9 DDR_DQS5 DDR_DQ47 DDR_DQ42
B DDR_CKE0
DDR_DQ51 DDR_DQ50 DDR_333_CK2_N DDR_DQS6 DDR_DQ52 DDR_DQ53
DDR_333_CK2
DDR_M_RST_N NC
8/B3,10/B3
+2_5V
8/C1 8/C1
4/D1
100
NC NC NC
BA1 CB3 VSS_7 CB2 A0 DQS8 VDD_3 CB1 CB0 A1 VSS_6 A2 DQ27 DQ26 VDD_2 A4 DQS3 DQ25 VSS_5 DQ24 A5 DQ19 VDDQ_3 A7 DQ18 A9 VSS_4 DQS2 DQ17 DQ16 VDDQ_2 CKE0 DQ11 DQ10 VSS_3 CK1_N CK1 VDDQ_1 DQS1 DQ9 DQ8 VSS_2 NC_10 NC_9 DQ3 VDD_1 DQ2 DQS0 DQ1 VSS_1 DQ0 VREF
CB7 VDDQ_12 CB6 A10 DM8 VSS_18 CK0_N CK0 VDDQ_11 CB5 CB4 DQ31 VSS_17 DQ30 A3 DM3 VDDQ_10 DQ29 DQ28 A6 VSS_16 DQ23 A8 DQ22 VDD_7 DM2 A11 DQ21 VSS_15 A12 DQ20 BA2 VDDQ_9 CKE1 DQ15 DQ14 VDD_6 DM1 DQ13 DQ12 VDDQ_8 NC_103 TEST NC_101 VSS_14 DQ7 DQ6 DM0 VDDQ_7 DQ5 DQ4 VSS_13
DDR_DQ59
2
DDR_CB0 DDR_A10 DDR_DM8
DDR_333_CK0_N
8/C1
144 143 142 141 140 139 138 137 136 135 134 133 132 131 130 129 128 127 126 125 124 123 122 121 120 119 118 117 116 115 114 113 112 111 110 109 108 107 106 105 104 103 102 101 100 99 98 97 96 95 94 93
C4C1
DDR_DQ62 DDR_DQS7 DDR_DQ57
0.1UF 16V
1
DDR_CB5
R3C2
C
NC
VDDSPD SA2 SA1 SA0 VDDQ_16 DQ63 DQ62 DM7 VSS_22 DQ61 DQ60 NC_173 VDDQ_15 DQ55 DQ54 DM6 VDD_9 A13 DQ53 DQ52 VDDQ_14 NC_163 DQ47 DQ46 VSS_21 DM5 S1_N S0_N VDDQ_13 DQ45 RAS_N DQ44 VSS_20 DQ39 DQ38 DM4 VDD_8 DQ37 DQ36 VSS_19
DIMM 184pin
DDR_DQ[63:0] 8/D7,9/D4,10/D8
184 183 182 181 180 179 178 177 176 175 174 173 172 171 170 169 168 167 166 165 164 163 162 161 160 159 158 157 156 155 154 153 152 151 150 149 148 147 146 145
PNP_MMBT3906 2
4/D5,13/D3
1
DDR_I2C_SDA
R4C1
DDR_DQ61 DDR_333_VREF
C3C1 0.1UF
0
2
GND
16V
100
C4C2 0.1UF 16V
GND
1
GND
U5C1 4/B8,9/D2,15/B3
PWR_OK
A
1
1
7
CKE1_LATCH
2
R3C1
U4C1 7
2
A
74LVC2G08 GND;4 +2_5V;8
74LVC2G32 GND;4 +2_5V;8
4/B3,14/A7
CKE1_LATCH_FB
DDR_VREF
R4C2 GND
GND
0 NO_POP=TRUE
SHEET TITLE: DESIGN ENGINEER:
Copyright 2003, Intel Corporation 8
DDR333 DIMM CONNECTOR
DESIGN NAME:
STORAGE COMPONENTS DIVISION 7
80331 CRB 6
5
4
DATE MODIFIED:
REVISION:
12-5-2003_8:37 3
2.0 2
ProtoB
SHEET 1
9
OF
17
8
7
6
5
4
2
3
1
DDR_VTT
DDR_DQ[63:0] 8/D7,9/D6,9/D4 DDR_DQ63 DDR_DQ62
D
49.9 49.9 1%
DDR_DQ61 DDR_DQ60
1%
DDR_DQ58
DDR_DQ56
DDR_DQ54
DDR_DQ52
DDR_DQ50
DDR_DQ48
DDR_DQ46
49.9
DDR_DM1 DDR_DM0
DDR_DQ42
8/C3,9/C3
DDR_DQ40
DDR_DQ38
DDR_A[13:0]
DDR_DQ36
DDR_DQ34
DDR_DQ32 DDR_DQ31 DDR_DQ30
DDR_DQ28
DDR_DQ26
DDR_DQ24
DDR_DQ22
B
DDR_DQ20
DDR_DQ18
DDR_DQ16
DDR_DQ14
DDR_DQ12
DDR_DQ10
DDR_DQ8
DDR_DQ6
DDR_DQ4
A
DDR_DQ2
DDR_DQ0
R5B26
49.9 49.9
8/B3,9/C7
DDR_CS0_N
49.9
R6B15 1%
8/B3,9/C6
R5B14
DDR_CS1_N
49.9
C5B9
C5B5
C5B8
C5B4
C4B1
C4B7
C4B8
16V
16V
16V
16V
16V
16V
16V
0.1UF
R6B16
0.1UF
0.1UF
0.1UF
0.1UF
0.1UF
0.1UF
1%
R5B33 49.9
8/B3,9/B4
R5B34
DDR_CKE0
49.9
R4B22 1%
1%
DDR_A0
49.9
DDR_VTT
R6B20 8/B3,9/B7
1%
DDR_CKE1
49.9
R4B11
GND
1%
8/D5,9/D4
C4B3
C5B7
C7B8
C6B4
C4B9
C4B5
C4B10
16V
16V
16V
16V
16V
16V
16V
0.1UF
R5B37
49.9
0.1UF
0.1UF
0.1UF
0.1UF
0.1UF
0.1UF
DDR_DQS7
R4B14
49.9
DDR_DQS6
R4B19
49.9 1%
DDR_DQS5
R5B21
49.9
DDR_VTT
1%
R6B35
DDR_DQS4
GND
R5B29
49.9 1%
DDR_DQS3
R6B26
49.9
R7B2
1%
DDR_DQS2
1%
DDR_DQS1
R7B6
R6B34
49.9
R7B14
49.9
1%
1%
DDR_DQS0
R7B13
C4B11 C4B6
C6B7
C6B8
C6B6
C6B9
C7B3
16V
16V
16V
16V
16V
16V
0.1UF
R7B19
49.9
0.1UF 16V
0.1UF
0.1UF
0.1UF
0.1UF
0.1UF
1%
1%
R7B5
49.9
DDR_CB[7:0]
1%
8/B5,9/C7,9/C4
R7B18
49.9
DDR_CB7
1%
DDR_CB6
R5B36
49.9
R7B10
49.9
GND
R5B35
49.9
1%
1%
DDR_CB5
1%
R6B6
49.9
A
1%
1%
DDR_CB3
R7B11
49.9
R7B21
R6B22
49.9
1%
R7B17 1%
DDR_CB4
R7B7
49.9
R5B17
49.9 1%
DDR_CB2
1%
R5B18
49.9 1%
DDR_CB1
1%
R6B21
49.9 1%
DDR_CB0
R6B5
49.9 1%
SHEET TITLE: DESIGN ENGINEER:
Copyright 2003, Intel Corporation 8
B
1%
1%
R7B20
49.9
DDR_VTT
R5B30
DDR_A1
R6B30
49.9
1%
DDR_DQ1
R6B23
1%
R7B8
49.9
49.9
1%
1%
DDR_DQ3
C
R5B10
49.9
DDR_A2
1%
R7B15
49.9
DDR_BA1
1%
R6B18
49.9
1%
DDR_DQ5
0.1UF
GND
1%
1%
R7B12
49.9
16V
R5B24
49.9
DDR_A4
R6B14
49.9
1%
DDR_DQ7
49.9
DDR_DQS8
R7B16
49.9
0.1UF
R6B27
49.9
1%
DDR_DQ9
8/B3,9/C3
1%
R7B1
49.9
R5B22
49.9
R6B25
49.9
1%
DDR_DQ11
0.1UF
DDR_DQS[8:0]
R6B36
49.9
16V
0.1UF
1%
R6B12
49.9
DDR_DQ13
C5B10
16V
16V
R6B28
1%
DDR_A5
R6B11
49.9
1%
DDR_DQ15
C5B11 C5B6
16V
0.1UF
1%
R6B19
49.9
C6B2
16V
0.1UF
1%
1%
49.9
1%
DDR_DQ17
49.9
C6B10 C6B5
16V
0.1UF
1%
1%
R6B32
49.9
DDR_BA0
C7B2
1%
R6B7
49.9
1%
R6B31
1%
DDR_A7
1%
R6B10
49.9
DDR_DQ19
GND
R6B13
49.9
R5B8
DDR_A3
49.9
1%
DDR_DQ21
8/B3,9/C3
1%
49.9
1%
R6B8
49.9
R5B5
49.9
DDR_A8
R5B31
49.9
1%
DDR_DQ23
DDR_WE_N
R6B4
DDR_A9
1%
R6B29
49.9
49.9
R5B27
49.9
1%
DDR_DQ25
49.9
1%
1%
49.9
DDR_RAS_N
1%
49.9
DDR_A6
R6B24
49.9
DDR_DQ27
8/B3,9/C3
R5B3
1%
R5B32
49.9
1%
0.1UF
R7B3
1%
R5B15
49.9
DDR_DQ29
49.9
DDR_A10
R5B28
49.9
1%
0.1UF
1%
R5B11
49.9
R5B23
49.9
1%
16V
DDR_VTT
R6B33
49.9
1%
1%
R5B16
49.9
DDR_A12
1%
49.9
1%
DDR_DQ33
49.9
DDR_A11
R5B12
49.9
DDR_DQ35
0.1UF
1%
DDR_A13
R5B2
49.9
1%
DDR_DQ37
8/B3,9/C7
8/D3,9/C7,9/C4
R5B25
1%
R5B7
49.9
16V
0.1UF
1%
1%
1%
DDR_DQ39
C7B7
16V
0.1UF
1%
R5B19
49.9
DDR_CAS_N
R5B20
49.9
1%
DDR_DQ41
C7B9
16V
16V
1%
R5B9
49.9
C7B10 C4B2
16V
0.1UF
R7B9
49.9
R4B7
49.9
1%
C7B4
16V
0.1UF
1%
R5B4
49.9
DDR_DQ43
C
C7B11 C7B5
1%
1%
DDR_DQ44
R6B17
49.9
R7B4
49.9
1%
49.9
1%
DDR_DQ45
1%
DDR_DM2
R4B21
49.9
1%
49.9
R4B17
R6B9
49.9
1%
R4B6
49.9
R5B13
49.9 1%
1%
49.9
1%
DDR_DQ47
DDR_VTT
R5B6
49.9
DDR_DM4 DDR_DM3
R4B20
49.9
DDR_DQ49
DDR_DM5
R4B10 1%
R4B18 1%
DDR_DQ51
DDR_VTT
R4B8
49.9 1%
1%
R4B9
49.9
1%
DDR_DM6
R4B13
49.9
1%
DDR_DQ53
R6B3
49.9
R4B3
49.9
1%
1%
49.9
D
1%
DDR_DM7
1%
49.9
R4B2
49.9
DDR_DM8
R4B16
49.9
1%
DDR_DQ55
1%
R4B5
49.9
DDR_DQ57
DDR_VTT DDR_DM[8:0] 8/C5,9/D7
R4B12
49.9
R4B1
49.9
DDR_DQ59
R4B4 1%
R4B15
DDR333 TERMINATION
DESIGN NAME:
STORAGE COMPONENTS DIVISION 7
80331 CRB 6
5
4
DATE MODIFIED:
REVISION:
12-5-2003_8:37 3
2.0 2
ProtoB
SHEET 1
10
OF
17
8
7
4/C7,12/C8,16/C6 4/C6,12/C8,16/C6
D
6
5
4
2
3
1
PBI_WE_N PBI_OE_N
D PBI_AD[15:0]
4/C6,12/C8,16/D8 PBI_A[2:0] 4/C6,16/D5 PBI_A[22:16] 4/C6,12/B8,16/D5
PBI_A2
PBI_A1
PBI_A0
PBI_AD0
PBI_AD6
PBI_AD5
PBI_AD3 PBI_AD15 1500
NC 1500
NC
5%
R8B6
1
1
5%
5%
2
2
1500
1500
5% 1
18
20
11
13
15
17
19
1500 5%
R8B5
1
5%
2
2
1500
1500 2
2
5% 1
5% 1
5%
1500
1500 2
1500
1500 2
2
5% 1
1
2
5% 1
1
PD_DIP17
NC1 E_N NC2 HSB_N G_N 16 W_N VSS NVSRAM 32KX8
9
16
S7C1
GND 9 24
7
14
NC NC
OPEN
PUSH DOWN = 1 3 1
Q8C1
B
1500
2
5%
NC NC
5
12
+3_3V
P_BOOT16# = 16-BIT FLASH R7A1
B10 KEY_1 C19 KEY_2
3
R7B22
PBI_AD7 PBI_AD6 PBI_AD5 PBI_AD4 PBI_AD3 PBI_AD2 PBI_AD1 PBI_AD0
1
PD_DIP15
21 20 19 18 17 15 14 13
10
R3L3
DQ7 DQ6 DQ5 DQ4 DQ3 DQ2 DQ1 DQ0
8
PD_PBI_A2
U8A1
NC NC NC NC NC NC NC
6
P_PCI32BITPCI# = Pull down 32bit bus - high 64bit bus
A14 A13 A12 A11 A10 A9 A8 A7 A6 A5 A4 A3 A2 A1 A0
A32 GND0 B1 GND1 B31 GND2 B32 GND3 C0 GND4 D0 GND5 D18 GND6 D19 GND7
D8 DACK0* B17 DACK1* B26 DACK2* B15 DACK3* D10 DACK5* D12 DACK6* D14 DACK7*
4
R3L1
NVSRAM_CE_N 22 NVSRAM_HSB_N 31 25 30
NVSRAM_CE_N NVSRAM_HSB_N
12/B8 12/B8
2 29 3 26 23 27 28 4 5 6 7 8 10 11 12
+3_3V
2
PD_PBI_A1
PBI_LA14 PBI_LA13 PBI_LA12 PBI_LA11 PBI_LA10 PBI_LA9 PBI_LA8 PBI_LA7 PBI_LA6 PBI_LA5 PBI_LA4 PBI_LA3 PBI_A2 PBI_A1 PBI_A0
STK14C88_3 VCAP VCCX
NC NC NC NC NC NC NC
PUSH DOWN = 0 (enable pulldown)
PRIVMEM = Normal addressing
1 32
B
PBI_A20 PBI_A21 PBI_A22
D9 DRQ0 B18 DRQ1 B6 DRQ2 B16 DRQ3 D11 DRQ5 D13 DRQ6 D15 DRQ7
R3L2
GND
+3_3V
C8 LA17 C7 LA18 C6 LA19 C5 LA20 C4 LA21 C3 LA22 C2 LA23
PD_PBI_A0
150UF POLYMER
NC NC NC
PRIVDEV = disable private devices on S-PCI
2
D17 MASTER* B27 TC B8 ENDXFR*
R2L2
C7B1
PD_PBI_AD0
1
12/B8
NC NC NC NC NC NC NC NC NC NC
BRG_EN = disable bridge
TI SN74LVC573APWR
GND
PC104_IRQ3
1 0 1 0 1 1 1 0 0 0
R1L1
GND
PBI_LA3 PBI_LA4 PBI_LA5 PBI_LA6 PBI_LA7
NC NC NC NC NC NC NC NC
DEFAULT SWITCH CONFIGURATION
PD_PBI_AD6
PBI_AD3 PBI_AD4 PBI_AD5 PBI_AD6 PBI_AD7
NC NC NC
B25 IRQ3 B24 IRQ4 B23 IRQ5 B22 IRQ6 B21 IRQ7 B4 IRQ9 D3 IRQ10 D4 IRQ11 D5 IRQ12 D7 IRQ14 D6 IRQ15
12/B8
NC
RETRY = PCI CONFIGURATION ENABLED
300
20 VCC3 19 1Q 18 2Q 17 3Q 16 4Q 15 5Q 14 6Q 13 7Q 12 8Q 11 LE
A31 SA0 A30 SA1 A29 SA2 A28 SA3 A27 SA4 A26 SA5 A25 SA6 A24 SA7 A23 SA8 A22 SA9 A21 SA10 A20 SA11 A19 SA12 A18 SA13 A17 SA14 A16 SA15 A15 SA16 A14 SA17 A13 SA18 A12 SA19
PC104_CE
R1L2
5%
1 OE_N 2 1D 3 2D 4 3D 5 4D 6 5D 7 6D 8 7D 9 8D 10 GND
PBI_A0 PBI_A1 PBI_A2 PBI_LA3 PBI_LA4 PBI_LA5 PBI_LA6 PBI_LA7 PBI_LA8 PBI_LA9 PBI_LA10 PBI_LA11 PBI_LA12 PBI_LA13 PBI_LA14 PBI_LA15 PBI_A16 PBI_A17 PBI_A18 PBI_A19
A11 AEN C1 SBHE* B28 BALE C9 MEMR* C10 MEMW* B12 SMEMR* B11 SMEMW* D1 MEMCS16* D2 IOCS16* A1 IOCHCHK* A10 IOCHRDY B14 IOR* B13 IOW*
C
R8B4
R6B2
GND
+3_3V
U6B1
PD_PBI_AL1 PD_PBI_UD
300
2000
NC NC
PD_PBI_AD5
5%
5%
NC NC
B19 REFRESH* B2 RESETDRV
PD_PBI_AD3
R6B1
GND
R7A2
NC
B20 SYSCLK B30 OSC
CORE_RST# = HOLD CPU CORE IN RESET
A4
PU_FLA_STS
H6 H4 B2
B9 12V B7 -12V B5 -5V
S_PCIX133EN = 100MHZ MAX PCI-X A BUS
+3_3V
+3_3V 74LVC573A
E8
A9 SD0 A8 SD1 A7 SD2 A6 SD3 A5 SD4 A4 SD5 A3 SD6 A2 SD7 C11 SD8 C12 SD9 C13 SD10 C14 SD11 C15 SD12 C16 SD13 C17 SD14 C18 SD15
R6B37
D4 F8 G8 F1
NC NC NC NC NC NC NC NC NC NC
PBI_AD0 PBI_AD1 PBI_AD2 PBI_AD3 PBI_AD4 PBI_AD5 PBI_AD6 PBI_AD7 PBI_AD8 PBI_AD9 PBI_AD10 PBI_AD11 PBI_AD12 PBI_AD13 PBI_AD14 PBI_AD15
PBI_A20
FLASH_RP_N
PC104_MOD B3 +5V1 B29 +5V2 D16 +5V3
1500
PBI_CE0_N
-12V
J9A1
2
12/C8
B6 C6 D5 D6 E6 F6 F7 G1 H2 H8
+12V
+5V
5%
4/C7,16/C6
PBI_AD15 PBI_AD14 PBI_AD13 PBI_AD12 PBI_AD11 PBI_AD10 PBI_AD9 PBI_AD8 PBI_AD7 PBI_AD6 PBI_AD5 PBI_AD4 PBI_AD3 PBI_AD2 PBI_AD1 PBI_AD0
1
H1 B8 B4
GND
E7 G7 H5 F5 F4 F3 E3 E1 H7 G6 G5 E5 E4 G3 E2 F2
NO_POP=TRUE
C
A8 C8 C7 B7 A7 D8 D7 C5 B5 A5 C4 D3 C3 B3 A3 C2 A2 D2 D1 C1 B1 A1 G2
DQ15 DQ14 DQ13 VCC3_Q DQ12 DQ11 DQ10 A22 DQ9 A21 DQ8 A20 U7B1 DQ7 A19 A18 28F640J3A DQ6 DQ5 A17 DQ4 A16 DQ3 A15 DQ2 A14 DQ1 A13 DQ0 A12 A11 A10 A9 NC1 A8 NC2 A7 NC3 A6 NC4 A5 NC5 A4 NC6 A3 NC7 A2 NC8 A1 NC9 A0 NC10 CE2 CE1 CE0 FLASH_4MX16 RP_N OE_N STS WE_N GND3 BYTE_N GND2 GND1 VPEN
R8A1
G4 PBI_A22 PBI_A21 PBI_A20 PBI_A19 PBI_A18 PBI_A17 PBI_A16 PBI_LA15 PBI_LA14 PBI_LA13 PBI_LA12 PBI_LA11 PBI_LA10 PBI_LA9 PBI_LA8 PBI_LA7 PBI_LA6 PBI_LA5 PBI_LA4 PBI_LA3 PBI_A2 PBI_A1 PBI_A0
VCC3_1 VCC3_2
PCIODT_EN = Pull down disables Internal 8.2K PU Resistors
A6 H3
+3_3V
PBI_AD4
PBI_A20
GND
RESULT OF PULL DOWN ACTIVE
PIN/GATE SWAPS OK GND 74LVC573A GND
R6A1
5%
PD_PBI_AL2 PBI_AD8 PBI_AD9 PBI_AD10 PBI_AD11 PBI_AD12 PBI_AD13 PBI_AD14 PBI_AD15
300
A
GND
4/D7,12/C8,16/C6
GND
U6A1
1 OE_N 2 1D 3 2D 4 3D 5 4D 6 5D 7 6D 8 7D 9 8D 10 GND
20 VCC3 19 1Q 18 2Q 17 3Q 16 4Q 15 5Q 14 6Q 13 7Q 12 8Q 11 LE
+3_3V PBI_LA8 PBI_LA9 PBI_LA10 PBI_LA11 PBI_LA12 PBI_LA13 PBI_LA14 PBI_LA15
+3_3V
A
TI SN74LVC573APWR
PBI_ALE
PBI_LA[15:3]
C3C4
C2D1
C6P5
C5P1
C2C3
C2D6
C8P3
16V
16V
16V
16V
16V
16V
16V
0.1UF
0.1UF
0.1UF
0.1UF
0.1UF
0.1UF
0.1UF
GND
SHEET TITLE: DESIGN ENGINEER:
Copyright 2003, Intel Corporation 8
PBI FLASH INTERFACE / RESET STRAPS
DESIGN NAME:
STORAGE COMPONENTS DIVISION 7
80331 CRB 6
5
4
DATE MODIFIED:
REVISION:
12-5-2003_8:37 3
2.0 2
ProtoB
SHEET 1
11
OF
17
8
7
6
5
4
2
3
1
8200
8200
J7C1
2
2
NC1
GND1
13
12
NC2
GND2
11
CPLD_TDI
10
TDI
GND3
9
CPLD_TDO
8
TDO
GND4
7
CPLD_TCK
6
TCK
GND5
5
CPLD_TMS
4
TMS
GND6
3
2
VREF
GND7
1
5%
5%
14
NC
R8C2
1
NC R8C3
R7C1
1
1
5%
2
8200
+3_3V
+3_3V
D
+3_3V
1000 2
5%
1000 2
5%
1000 2
5%
1000 5%
1000
2
5%
1000
1000
1000
2
5%
2
5%
2
5%
2
1
2
5%
LED1_SEGD
5
1
NC
LED0 LED1 LED2 LED3 LED4 LED5 LED6 LED7 PBI_A19 PBI_A20 PBI_A21 PBI_A22 TEMP_OS ESN_SLOW
1000
1000 5%
1000 5%
1000 5%
5%
LED2_SEGD
5
SEG_G
SEG_C
SEG_E
DP
SEG_D
CATH_1
10
LED2_SEGA
9
LED2_SEGB
8
LED2_SEGC
7
LED2_DP
6
GND
C
1
2
+3_3V ROT_SW_4
C1
3
6
8 C2
4
ROT_SW_8
5 4
2
+3_3V ROT_SW_2
HAB16W S01002
1
1
21 GND1 31 GND2 44 GND3 62 GND4 69 GND5 75 GND6 84 GND7 100 GND8
1
B +3_3V
GND
BUZZER_P
GND
+3_3V
GND 2000
XC9572XL-10TQ100C XILINX
E9B1
1000
2
5%
1
NC
U9A2
Q9C1
6
Q9C1
GND
4
R9C3
SN74LVC1G14
NPN_MMBT3904 SWAPPABLE
1
GND 1
1
R9C5
1
1
GND
2
LED0_R
BUZZER_ENABLE_N R9C6
1
2
1%
422
1
J9C2
2
BUZZER_VOL
BUZZER_OSC_FB
1
2
Install jumper to decrease buzzer volume
C9C1
BUZZER_EN_Q
GND
A
1UF X5R 10V
Install Jumper to enable Buzzer
2
1%
1%
2
GND
J9C1
422
LED1_R
2
422
LED2_R 1%
1%
2
2
2
422
LED3_R
2
422
LED4_R 2
2
1%
1%
2
2
1%
2
422
LED5_R 422
LED6_R 422
LED7_R 422
2
LED9A6
GRN
2
LED9A4 GRN
2
LED9A3 GRN
16V
0.1UF
LED9A7 GRN
C4C7
16V
0.1UF
LED9A8 GRN
C4D4
16V
0.1UF
LED9A2 GRN
C6P3
16V
0.1UF
GRN
C7R2
GRN
GND
1
R1L3
1
R1L5
1
R1L6
1
1
R1L9
GND
R1L10
GND
R1L7
1
R1L4
1
1
GND R1L8
A
LED9A5
1%
LED9A1
2 NPN_MMBT3904 SWAPPABLE
4
1
1
BUZZER_Q
8200
1%
LED0 1
1
2
5%
2
5
+3_3V
1
422
DS2430A_TSOC
LED1
3
2
NC NC NC
3
LED2
5
2 6 NC4 5 NC3 4 NC2
1%
NC
LED3
2 DMT_1206_SMT_BUZZER BUZZER_N
1
GND
LED4
U9C1 NC VCC
1
1 GND 2 DATA 3 NC1
R9C4
LED5
-
1
1%
LED6
2
DS2430A_TSOC
R9C1
NC NC NC
R9C2
LED7
6 NC4 5 NC3 4 NC2
681
NC
31.6K
1 GND 2 DATA 3 NC1
GND
5%
+3_3V
1
R2L1
PBI_A[22:16] 4/C6,11/D7,16/D5
1
2
U9A1
+
+3_3V
TEMP_OS
13/C1
1
26 VCCIO1 38 VCCIO2 51 VCCIO3 88 VCCIO4
B
4
SEG_B
S9B1 ROT_SW_1
R1M8
+3_3V
3
LED2_SEGE
SEG_A
SEG_F
ROT_SW_4 ROT_SW_8 BUZZER_ENABLE_N
R1M7
5 VCCINT1 57 VCCINT2 98 VCCINT3
LED2_SEGG
CATH
8200
PBI_A16 PBI_A17 PBI_A18
2
5%
NC
NVSRAM_CE_N NVSRAM_HSB_N PC104_CE PC104_IRQ3
1
LED2_SEGF
IPN=C37226-001
8200
NC
BATT_DISCHRG
65 IO4_1 67 IO4_2 71 IO4_3 72 IO4_4 68 IO4_5 76 IO4_6 77 IO4_7 70 IO4_8 66 IO4_9 81 IO4_10 74 IO4_11 82 IO4_12 85 IO4_13 78 IO4_14 89 IO4_15 86 IO4_16 90 IO4_17 79 IO4_18
DS9A1
2
GBE_SMBALRT_N FLASH_RP_N BATT_ENABLE_N BATT_PRESENT_N BATT_CHRG
87 IO2_1 94 IO2_2 91 IO2_3 93 IO2_4 95 IO2_5 96 IO2_6 3 IO2_7/GTS1 97 IO2_8 99 IO2_9/GSR 1 IO2_10 4 IO2_11/GTS2 6 IO2_12 8 IO2_13 9 IO2_14 11 IO2_15 10 IO2_16 12 IO2_17 92 IO2_18
1
D22002 7SEG_DISPLAY HDSP_A103
5%
11/B7 11/B7 11/C3 11/C3
PBI_AD12 PBI_CE1_N
1
LED1_SEGA LED1_SEGB LED1_SEGC LED1_SEGD LED1_SEGE LED1_SEGF LED1_SEGG LED1_DP LED2_SEGA LED2_SEGB LED2_SEGC LED2_SEGD LED2_SEGE LED2_SEGF LED2_SEGG LED2_DP ROT_SW_1 ROT_SW_2
2
15/B4
PBI_OE_N
1
2
GND
5%
11/C8 15/B3 15/B5 15/B5
PBI_AD13 PBI_AD14 PBI_AD15 PBI_AD9
1
2
1
4/C6,16/C6,16/C6
PBI_WE_N
1
2
GND
1
4/C6,11/C6,16/C6
PBI_AD8 PBI_AD10 PBI_AD11
6
R1M9
4/C7,11/C6,16/C6
S_CLKO_CPLD PBI_ALE
LED1_DP
1
2
R1M10
3/A6 4/D7,11/A8,16/C6
41 IO3_1 32 IO3_2 49 IO3_3 50 IO3_4 35 IO3_5 53 IO3_6 54 IO3_7 37 IO3_8 42 IO3_9 60 IO3_10 52 IO3_11 61 IO3_12 63 IO3_13 55 IO3_14 56 IO3_15 64 IO3_16 58 IO3_17 59 IO3_18
8200
C
16 IO1_1 13 IO1_2 18 IO1_3 20 IO1_4 14 IO1_5 15 IO1_6 25 IO1_7 17 IO1_8 22 IO1_9/GCK1 28 IO1_10 23 IO1_11/GCK2 33 IO1_12 36 IO1_13 27 IO1_14/GCK3 29 IO1_15 39 IO1_16 30 IO1_17 40 IO1_18
CATH_1
7
1
2
IPN=C37226-001
8200
PBI_AD0 PBI_AD1 PBI_AD2 PBI_AD3 PBI_AD4 PBI_AD5 PBI_AD6 PBI_AD7
SEG_D
2
4/C6,11/D4,16/D8
DP
1
2
D22002 7SEG_DISPLAY HDSP_A103
2
R8A2 PBI_AD[15:0]
SEG_E
LED1_SEGC
2
R1M6
4
8
2
R1M4
LED1_SEGE
SEG_C
LED1_SEGB R1M2
83 TDO 45 TDI 48 TCK 47 TMS
NC NC NC NC NC NC NC NC NC
SEG_B
SEG_G
LED1_SEGA
9
R1L11
2 NC1 7 NC2 19 U8B1 NC3 24 NC4 34 NC5 43 NC6 46 NC7 73 NC8 80 NC9
SEG_F
10
R8B3
3
SEG_A
R8B2
LED1_SEGG GND
CATH
R8B1
2
R8A3
LED1_SEGF
1000
1
GND GND
5%
J07014_2X7_XILINX_JTAG_HEADER
1000
R9B2
R9B1
R9A2
R9A1
DS9A2 5%
1
1000
1
5%
1
1000
1
R1M5
R8C1
1
R1M3
R1M1
R1L12
8200
1
5%
1
1
+3_3V
5%
5%
2
8200
D
GND
GND
GND
GND
GND
GND
SHEET TITLE: DESIGN ENGINEER:
Copyright 2003, Intel Corporation 8
CPLD AND HEX DISPLAY
DESIGN NAME:
STORAGE COMPONENTS DIVISION 7
80331 CRB 6
5
4
DATE MODIFIED:
REVISION:
12-5-2003_8:37 3
2.0 2
ProtoB
SHEET 1
12
OF
17
8
7
6
5
4
2
3
1
2000 2
2
5%
GND
1
6V_0X75A
R1C1
2 J1C2
2
1 CONN_4P_I2C 4/D5,9/D4
D
4/D5,9/D4
+3_3V
+12V
Header for Active BGA Heatsink Fan
1
F1C1
1
R1C8
3
5%
+3_3V 4
2000
+3_3V +3_3V
DDR_I2C_SCL
FB 1
2000 5%
C1E2
22UF TANT
22UF TANT
1
3
24LC16B MSOP8 +3_3V
7 PD_EEPROM_WP
GND
1
R1C4
5%
2000
LM75_SOP8-3
CONN_4P_I2C
GND
SO8 U1D1 2 SCL 8 1 SDA VCC
GND
2
R1C9 R1D1 R1D2
5% 5%
2
GND GND GND
2
VSS
4
1
2
1 A0_X 2 A1_X 3 A2_X
8
1
5%
2000 PD_EEPROM_A0 2000 PD_EEPROM_A1 2000 PD_EEPROM_A2
WP
1
2
5%
2
1
5%
1
R1C7 R1C6 R1C5
1
GND GND GND
VCC
2
6 SCL 5 SDA
SCD1
GND
GND
J1C1
1
SCL1
GND
GND 2
U1C1
4/D5
C2E4
2
C9R1 .01UF X7R CC0603
4
R1C3
R1C2
1
5%
2
2
2000
+12_FAN
4/D5
D
J2D1
DDR_I2C_SDA
5%
7 A0 6 A1 5 A2
2000 PD_LM75A_A0 2000 PD_LM75A_A1 2000 PD_LM75A_A2
O.S. GND
+3_3V
3
TEMP_OS
4
12/B6
GND
C
C +3_3V
8200
7
U0_RTS_N
4/D6 4/D6 4/D6 4/D6 4/D6 4/D6 4/D6
6
U1_TXD
20
U1_RTS_N
21
U0_RXD
8
U0_CTS_N
5
U1_RXD
26
U1_CTS_N
22 NC
19 24
T1IN
+6.6V to -6.6V Doubler V-
+3.3V 400K
x4
3 T2OUT
UART0_RTS_N
1 T3OUT
UART1_TXD
T4IN
28 T4OUT
UART1_RTS_N
9 R1IN
UART0_RXD
4 R2IN
UART0_CTS_N
27 R3IN
UART1_RXD
R4OUT
23 R4IN
UART1_CTS_N
R5OUT
18 R5IN
R1OUT R2OUT
x5
R3OUT
GND
EN_N
5K
2
5%
B
GND PINOUT NOT VERIFIED 9
GND
GND UART0_TXD
2 T1OUT
T3IN
T2IN
1UF X5R 10V
2
0
UART_VN
17
1
15 C2+ 16 C2-
R1D4
1UF X5R 10V UART_C2N
C1D1
13UART_VP 3.3V to 6.6V Doubler V+
5%
12 C1+ 14 C1-
U0_TXD
4/D6
U1D2
UART_C2P
C1D2
1UF X5R 10V
1
5% 1
UART_C1N
11 VCC
MAX561
0
2
8200 1
5%
2
8200 1
5%
2
8200 2
5%
C1E1
1UF X5R 10V
R1D5
9
C9P1
R2D18
8
GND
R2D17
9
B
R2D16
HPI_N
3/B1
7
1
8
NC
R2D14
6
8200
7
NC
2
5
5%
6
NC
+3_3V UART_C1P
1
4
R2D11
3
5
NC
8200
2
4
2
3
S_INTD_N
5%
S_INTC_N
J1E1
1
1
R2D9
2
8200
3/A7,7/D4
S_INTB_N
2
3/B7,7/D8
+3_3V
1
5%
3/B7,7/D4
J2C1
S_INTA_N
1
3/B7,7/D8
5 5%
8200
8.2K
6 5%
R2D6
8.2K RP2D1
7 5%
2
4
8.2K RP2D1
8 5%
5%
3
8.2K RP2D1
1
2
RP2D1
R2D4
NO_POP=TRUE 1
1 2 3 4 5 6 7 8
J1E2
RJ11 DUAL
10
GND NC UART_SHDN
25 SHDN
1
J1D1
2
+3_3V
0
0 2
1
1
R9R1
GND
A
R9P1
C36912-001
5%
8200
2
5%
5%
1
R1D3
2
10
A
GND GND
SHEET TITLE: DESIGN ENGINEER:
Copyright 2003, Intel Corporation 8
I2C INTERFACE / UARTS
DESIGN NAME:
STORAGE COMPONENTS DIVISION 7
80331 CRB 6
5
4
DATE MODIFIED:
REVISION:
12-5-2003_8:37 3
2.0 2
ProtoB
SHEET 1
13
OF
17
8
7
6
5
4
2
3
DDR Voltage Regulator
1.35V Voltage Regulator
ProtoB #6: Added diode to prevent battery power from draining into 5V rail
+5V
1
D5C2
GND 1
2
+1_35V +3_3V
MBRS340T 6 GND_BASE
+3_3V
C6C3 10UF X5R
16V
V2_5_LX
6 DL
V2_5_DL
LX
MAX1954EUB USOP_10
PGND GND
GND
4
GND
7
2 GND
53.6 2
1%
GND
8
3
7
4
6
L6D1 2
GND
3.3UH 1
Q6D1
V2_5_FB
R5D1
1%
1
R5D2
1
2
1%
8870
C6C4
1
C6C2
22UF X5R
2
150UF 2 POLYMER
1
1%
GND
C6D1 150UF POLYMER
10K
2
R5C41
12.4K
CHECK ESR > 50MOHM
V1_3_ADJ
6A maximum output current
5
FDS6898A
GND
3 FB
GND
1
422
9
10UF X5R
2
V2_5_DH
D
C5D7
1%
U5C2
5
1
8
DH
ADJ
R5D4
COMP
SHDN
10UF X5R
2
2
C5D1 47PF COG
GND
1
V2_5_COMP
62K
1
V2_5_BST C6C5
5%
C5D2 1000PF X7R
C5D4
+2_5V
0.1UF
5 1
2
V2_5_COMP_R R5C40
10 BST
HSD
4
DDPAK5
GND
IN 1
HSD Req. Kelvin connection to drain
1.5A maximum OUT
1
X7R
U5D1
LT1963
R5D3
C5D3
IN
3
NC
D
2
3
GND
D5C1 1 2
GND
AUX CONNECTOR FOR SLOT POWER +12V
0.1UF
4
GND
3
7
4
6 DL
Q6D3 1%
8870
1%
GND
6A maximum output current HSD Req. Kelvin connection to drain
3.3UH 1
V3_3S_COMP_R 110K
5
FDS6898A
GND V1_5_FB
L6E1 2
6
V1_5_DL
7
3 FB
GND
GND
GND
C6D4 22UF X5R
1 2
C6D2
X7R
R1A1
1
150UF 2 POLYMER
C6E1
1%
1
V3_3S_COMP 2
COMP DH
C1A1 47PF COG
C1A2 1000PF X7R
10 BST
HSD
U1A1
LX
USOP_10
GND
GND
8
V3_3S_DH
9
V3_3S_LX
4
GND
GND
NO_POP=TRUE
1
C1A4 1
GND
2
8
3
7 6
3 FB
V3_3S_FB
Q1A1 R9L2 R9L3
GND
+3_3VPCI
3.3UH 1
5
FDS6898A
GND
1%
1%
2
L2A1 2
V3_3S_DL
7
R3A3
0.01 1%
4
6 DL
PGND
10K GND
V3_3S_BST
MAX1954EUB
150UF POLYMER
+3_3V
GND
1
V1_5_LX
8
10UF X5R
C1A3
+1_5V 2
3
IN
9
22UF TANT
1
1
V1_5_DH
MAX1954EUB
PGND GND
8
2
LX
22UF TANT
2
U5D2 USOP_10
GND
GND
V1_5_BST
1
COMP
C9L2
D1A1 1 2
C1B1 NC
1
HSD
DH
C5D10 47PF COG
2
2
10 BST
R5D6 R5D7
C5E1 1000PF X7R
2
V1_5_COMP
44.2K
R1B1
0.01 1% C2A7
C6D5
1%
1
16V
5 2
R5D5
1
V1_5_COMP_R
+5VPCI True Pinout Represented
GND
IN 1
NO_POP=TRUE
2
X7R
0.01 1%
GND
16V
C5E2
HSD Req. Kelvin connection to drain
4
10UF X5R
GND
C
2
0.1UF
NC
3
3
R1A2
5
1 2
1
2
2
C6D3
D5D1
NO_POP=TRUE +12VPCI
3.3V Voltage Regulator for PCI Slot
1
+3_3V
+5V
+5VPCI
CONN_4P_DISK_KEY J1A1 1
C
+12VPCI
MUST USE SAME POWER SUPPLY AS HOST
+5VPCI
1.5V Voltage Regulator
+5V
+12VPCI
GND
31.6K
C7L4 1
C3A1
22UF X5R
150UF 2 150UF POLYMER POLYMER
2
1
C3A2
10K
B
B
+12VPCI
+12V
DDR VTT Voltage Regulator
GND
+3_3VPCI
GND
+3_3V
LED Indicators
VREF MUST NOT POWER UP BEFORE 1.8V
+2_5V +1_5V
+3_3V
+3_3V
C5B1 0.1UF
+3_3V
DDR_VREF
16V
0.1UF
U5B1
1
LED7E2
LED5D1
UXXXX2_LP2996
5%
2
100
1000
2
100
1000
Locate decoupling near load rather than supply
1
3
R4P1
R6D2
1
1
1
R3R2
R3R1
Q6D2
Q6D2
5
6
8
2
1
C6B1
2
150UF POLYMER
GND
GND
GND
NPN_MMBT3904 SWAPPABLE
1
GND
NPN_MMBT3904 SWAPPABLE
4
VTT
2
A
R5P1
R6D1
1
1
16V
0.1UF
GND
R5L1
10UF X5R
1
2
5%
2
2
1%
2 1
C5M1
LED6D1
2
2
2
100
422
422
C4M1 DDR_VTT
R9L1
C5B3
1
GRN
16V
LED7E1 2
GRN
GND
PV_IN
2
GRN
Attach near DIMM
2
GRN
7
A
3 VSENSE
1
LED5A1
LED1A1
VDDQ
AV_IN
1
GND
GRN
6
1
1
4
2
VREF
GRN
5
SD_N
1%
2
0.1UF
5%
8200
C5B2
1
2
R5B1
1
+2_5V
4/B3,9/A5
100
16V
GND GND
GND
GND
SHEET TITLE: DESIGN ENGINEER:
Copyright 2003, Intel Corporation 8
VOLTAGE REGULATORS
DESIGN NAME:
STORAGE COMPONENTS DIVISION 7
80331 CRB 6
5
4
DATE MODIFIED:
REVISION:
12-5-2003_8:37 3
2.0 2
ProtoB
SHEET 1
14
OF
17
8
7
6
5
4
2
3
1
D
D
+2_5V
GND
MAX8863T
100K
8200
2
SHDN_N 5 SET
GND
BATT_REG_SET
SOT23_5
5%
5%
2
GND
1
MAX6383 VCC
SC70 2 RESET_N
BATT_REG_RST_N
1%
1%
1
1
R7D1
NC2 BATT_OFF NC
GND
R7D5
6
39K
GND
1
1
1.3M
4.7UF X5R
1%
1%
3
BATT_ENABLE_N
12/C8
74LVC373A 2
D
1
11
PWR_OK
LE OE_N
4/B8,9/A8,9/D2
R7C25
1
2
8200
1.3M
5%
+
BATT_CHRG
1
2
1.3M
5%
5
+
7
BATT_DISCHRG
12/B8
6-
C7C4 0.1UF
NPN_MMBT3904 SWAPPABLE
16V
GND
GND
C7C3 .01UF X7R CC0603
2
1 1
U8C1
1000
2
GND
LM393 GND;4 +12V;8
GND
Need to resolve the 12V output from comparator
74LVC373A 12 13
GND
D
Q
U7D1
A GND;10 V_BATT;20
GND
74LVC373A 16
D
1
NC
Q
U7D1
NC 11
74LVC373A 19 18 D
GND;10 V_BATT;20
Q
U7D1
LE
LE OE_N
11
17
11
4
74LVC373A 5
D
Q
GND;10 V_BATT;20
1
74LVC373A 9 8
U7D1
NC 11
D
GND;10 V_BATT;20
Q
U7D1
LE
LE
1
NC
11
7
74LVC373A 6
D
Q
11
GND;10 V_BATT;20
1
14
GND;10 V_BATT;20
74LVC373A 15
D
NC
Q
U7D1
LE
LE
1
NC
U7D1
NC
11
LE OE_N
2
5%
B 2
OE_N
1
+1_5V
R7E4
Q7D1
12/B8
OE_N
6
NC
+3_3V
R7D3
R8C5
LM393 GND;4 +12V;8
Q7D4
R8D3
1%
1 39K VBATT_D_Q
1%
1
2-
OE_N
VBATT_COMP
5%
2
U8C1 3 GND
2
BATT_ENABLE_RC
5%
12/C8
1
8200 2
2
BATT_PRESENT_N
3
R8D4
OE_N
NPN_MMBT3904 SWAPPABLE
215K
BATT_DFLOP_OE_N
200
5%
39K
1
16V
1
5%
R7D12 2
BATT_QB
R7C26
1
4
5
1
3
Q7D4
R8C4
1
R7E1
B
GND;10 V_BATT;20
C7D1 0.1UF
1
GND VBATT_COMP_L
2
1%
1
R7D14
GND
GND
+3_3V
VBATT_COMP_H
10K
1%
2
16V
R8D6
1
0.1UF
10UF X5R
R8D2
C7E2
10K
C7E3
Q
U7D1
GND
OE_N
GND BATT_ADJ
2
2
16
R8D5
2
5%
100K
1
A48014-001 PAD
GND
5%
GND R7D2
110K
5
C
1
A39481-001 CLIP
NPN_MMBT3904 SWAPPABLE
2
39K A78958-001 Battery
3
C2P1 BATT_RST_N R7D10
2
2
2
162K 1%
2
GND
1
R7D13
4
1
100
NC1
J8D1 1
GND 2
BATT_BATB
10 2
EOC_N RESET_N
ADJ
GND
NPN_MMBT3904 SWAPPABLE
5%
GND
GND
SD_N
1
R7E3 BATT_COMP_R
14 13 4
BATA BATB VL
COMP
GND
1%
2
11
PROG
15
A/B
R8D1
5
BATT_SD_N
SO16
100K
16.5K
53.6 1%
2
GND
9
ISET
CS+ CS-
BATT_CS_P BATT_CS_N
1
12
GND BATT_COMP
ADP3801
7 6
R7D11
8
Q7D2 BATT_OFF_Q 2
PWR_GD_Q 5 4
3 VCC
BATT_ISET
1
DRV
U7D4
1
0.1UF
Q7D2
3
BATT_DRV
10K 2
10UF X5R
16V
1%
C7D8
R6D3
10UF X5R
C7D7
C7D3 1000PF X7R
NC
C7D5
C7E1 1000PF X7R
GND
2
+12V GND
22UF X5R
GND THRESHOLD=2.31V
GND
C7D2
22PF
100K
1
R7D8
3
1
C7D4 COG
R7D4
1
U7D2
R7D9
5%
R7D6
1
1%
2
10UF X5R
GND
C
NO_POP=TRUE 100K 1
1000
R7D7
2
C7D6
U7D3 OUT4
IN
2
3
V_BATT
1
1%
2
4300 2
220UF TANT
D7D1
1
5%
4
1
3
C8E1
1
5
2
2
D7D2
6
R7E2
SI3441
0.5 VBATT_D 2
1%
4300
Q7D3 1
R8E1
VBATT_R
4.7UH 1
2
2
1
L8E1
VBATT_IND
1
GND;10 V_BATT;20
A
1
SHEET TITLE: DESIGN ENGINEER:
Copyright 2003, Intel Corporation 8
DDR BATTERY BACKUP
DESIGN NAME:
STORAGE COMPONENTS DIVISION 7
80331 CRB 6
5
4
DATE MODIFIED:
REVISION:
12-5-2003_8:37 3
2.0 2
ProtoB
SHEET 1
15
OF
17
7
3/A6
S_CLKO_MICTOR
MICTOR A 1 38 +5V SCL 2 37 GND SDA 3 36 CLK_E/CLK:0 CLK:1/CLK_O 35 4 A1:7/D15_O D15_E/A3:7 34 5 A1:6/D14_O D14_E/A3:6 33 6 A1:5/D13_O D13_E/A3:5 32 7 A1:4/D12_O D12_E/A3:4 31 8 A1:3/D11_O D11_E/A3:3 30 9 A1:2/D10_O D10_E/A3:2 29 10 A1:1/D9_O D9_E/A3:1 28 11 A1:0/D8_O D8_E/A3:0 27 12 A0:7/D7_O D7_E/A2:7 26 13 A0:6/D6_O D6_E/A2:6 25 14 A0:5/D5_O D5_E/A2:5 24 15 A0:4/D4_O D4_E/A2:4 23 16 A0:3/D3_O D3_E/A2:3 J05001 22 17 A0:2/D2_O D2_E/A2:2 21 18 A0:1/D1_O D1_E/A2:1 20 19 A0:0/D0_O D0_E/A2:0
NC GND
PBI_AD[15:0] 4/C6,11/D4,12/C8
PBI_AD15 PBI_AD14 PBI_AD13 PBI_AD12 PBI_AD11 PBI_AD10 PBI_AD9 PBI_AD8 PBI_AD7 PBI_AD6 PBI_AD5 PBI_AD4 PBI_AD3 PBI_AD2 PBI_AD1 PBI_AD0
C
J8B1
5
4
2
3
D PBI_A[22:16] 4/C6,11/D7,12/B8
NC NC PBI_A22 PBI_A21 PBI_A20 PBI_A19 PBI_A18 PBI_A[2:0]
PBI_A17
4/C6,11/D7
PBI_A16 PBI_A2 PBI_A1 PBI_A0 PBI_CE1_N PBI_CE0_N PBI_ALE PBI_OE_N PBI_WE_N PBI_CE1_N
4/C6,12/C8,16/C6 4/C7,11/C8 4/D7,11/A8,12/C8 4/C6,11/C6,12/C8 4/C7,11/C6,12/C8
C
4/C6,12/C8,16/C6
M ictor C onnector P in out A gilent’s vs. T ektronix
NC
NO_POP=TRUE
T ek 1 G N D (1) 2 G N D (1) 3 CLK 4 X 3:7 5 X 3:6 6 X 3:5 7 X 3:4 8 X 3:3 9 X 3:2 10 X 3:1 11 X 3:0 12 X 2:7 13 X 2:6 14 X 2:5 15 X 2:4 16 X 2:3 17 X 2:2 18 X 2:1 19 X 2:0
GND
B
+5V
C7N5
C3C7
16V
16V
0.1UF
1
NC
M1
D
6
G1GND0 G2GND1 G3GND2 G4GND3 G5GND4
8
0.1UF
GND
A gilent 1 +5V D C (3) 3 G N D (3) 5 CLKe 7 D 15e 9 D 14e 11 D 13e 13 D 12e 15 D 11e 17 D 10e 19 D 9e 21 D 8e 23 D 7e 25 D 6e 27 D 5e 29 D 4e 31 D 3e 33 D 2e 35 D 1e 37 D 0e
• • • • • • • • • • • • • • • • • • •
A gilent 2 SC L (2) 4 SD A (2) 6 CLKo 8 D 15o 10 D 14o 12 D 13o 14 D 12o 16 D 11o 18 D 10o 20 D 9o 22 D 8o 24 D 7o 26 D 6o 28 D 5o 30 D 4o 32 D 3o 34 D 2o 36 D 1o 38 D 0o
• • • • • • • • • • • • • • • • • • •
T ek 38 G N D (1) 37 G N D (1) 36 C L K 35 X 1:7 34 X 1:6 33 X 1:5 32 X 1:4 31 X 1:3 30 X 1:2 29 X 1:1 28 X 1:0 27 X 0:7 26 X 0:6 25 X 0:5 24 X 0:4 23 X 0:3 22 X 0:2 21 X 0:1 20 X 0:0
B
(1) T ektronix doesn't use pins 1,2,37,38 but recom m ends that they are grounded. (2) Pins 2 & 4 are not to be used they are outputs from the logic analyzer used to program em ulation or analysis probes. (3) Pins 1 & 3 are not to be used they should be left as no connects. T hey are pow er pins for analysis/em ulation probes.
A
A
SHEET TITLE: DESIGN ENGINEER:
Copyright 2003, Intel Corporation 8
DEBUG - MICTOR CONNECTORS
DESIGN NAME:
STORAGE COMPONENTS DIVISION 7
80331 CRB 6
5
4
DATE MODIFIED:
REVISION:
12-5-2003_8:37 3
2.0 2
ProtoB
SHEET 1
16
OF
17
8
7
6
5
4
2
3
1
Revision History D
Rev 2.0 - ProtoB
12/5/2003
D
C
C
B
B
A
A
SHEET TITLE: DESIGN ENGINEER:
Copyright 2003, Intel Corporation 8
REVISION HISTORY - 80331 CRB
DESIGN NAME:
STORAGE COMPONENTS DIVISION 7
FP333 6
5
4
DATE MODIFIED:
REVISION:
12-5-2003_8:37 3
2.0 2
ProtoB
SHEET 1
17
OF
17
