6.5.5 Encoders in Verilog It is straightforward to write a behavioral description of an encoder in Verilog using a for loop. For example, Table 6-31 is a behavioral Verilog module for a priority encoder function equivalent to the 74x148.

Within the always block, it initializes the outputs as if no asserted input will be found. Then it uses a for loop to look for an asserted input, working from the lowest priority to the highest. In the end, A will be set to the number of the last (highest priority) asserted input that was found, if any.

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6.6 Three-State Devices In Section 3.7.3 we described the electrical design of a device whose outputs may be in one of three states; 0, 1, or Hi-Z. In this section we'll show how to use them. 6.6.1 Three-State Buffers The most basic three-state device is a three-state buffer, often called a three-state driver. The logic symbols for four physically different three-state buffers are shown in Figure 6-51.

The basic symbol is that of a non-inverting buffer (a, b) or an inverter (c, d). The extra signal at the top of the symbol is a three-state enable input, which may be active high [(a), (c)] or active low [(b), (d)]. When the enable input is asserted, the device behaves like an ordinary buffer or inverter. When the enable input is negated, the device output "floats" i.e. it goes to a high-impedance (Hi-Z), disconnected state and functionally behaves as if it weren't even there. Three-state devices allow multiple sources to share a single “party line”, as long as only one device "talks" on the line at a time. Figure 6-52 gives an example of how this can be done. Three input bits, SSRC2-SSRC0, select one of eight sources of data that may drive a single line, SDATA. A 3-to-8 decoder (74x138), ensures that only one of the eight SEL lines is asserted at a time, enabling only one three-state buffer to drive SDATA. However, if not all of the EN lines are asserted, then none of the three-state buffers is enabled. The logic value on SDATA is undefined in this case.

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Typical three-state devices are designed so that they go into the Hi-Z state faster than they come out of it. This means that if the outputs of two three-state devices are connected to the same party line and we simultaneously disable one and enable the other, the first device will get off the party line before the second one gets on. This is important because if both devices were to drive the party line at the same time, and if both were trying to maintain opposite output values (0 and 1), then excessive current could flow and create noise in the system, as discussed in Section 3.7.7. This is called fighting. Unfortunately, delays and timing skews in control circuits make it difficult to ensure that the enable inputs of different three-state devices change "simultaneously." Even when this is possible, a fighting can still arise if three-state devices from different speed logic families are connected to the same party line.

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The only really safe way to use three-state devices is to design control logic that guarantees a dead time on the party line during which no one is driving it. The dead time must be long enough to account for the worst-case differences between turn-off and turn-on times of the devices and for skews in the three-state control signals. A timing diagram that illustrates this sort of operation for the party line of Figure 6-52 is shown in Figure 6-53. This timing diagram illustrates a drawing convention for three-state signals, when in the Hi-Z state, they are shown at an "undefined" level halfway between 0 and 1.

6.6.2 Standard MSI Three-State Buffers Like logic gates, several independent three-state buffers may be packaged in a single SSI IC. However, most party-line applications use a bus with more one bit of data. For example, in an 8-bit microprocessor system, the data bus is eight bits wide, and peripheral devices normally place data on the bus eight bits at a time. Thus, a peripheral device enables eight three-state drivers to drive the bus, all at the same time. Independent enable inputs, as shown in Figure 6-52 are not necessary. So to reduce the package size in wide-bus applications, most commonly used MSI parts contain multiple three-state buffers with common enable inputs. For example, Figure 6-54 shows the logic diagram and

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symbol for a 74x541 octal non-inverting three-state buffer. Both enable inputs, G1_L and G2_L, must be asserted to enable the device's three-state outputs. The little rectangular symbols inside the buffer symbol indicate hysteresis, an electrical characteristic of the inputs that improves noise immunity. The 74x541 inputs typically have 0.4 volts of hysteresis.

Figure 6-55 shows part of a microprocessor with an 8-bit data bus, DB[0-7] and a 74x541 used as an input port. The microprocessor selects Input Port 1 by asserting INSEL1 and requests a read operation by asserting READ. The selected 74x541 responds by driving the microprocessor data bus with user-

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supplied input data. The other inputs ports can be selected when a different INSEL line is asserted along with a READ.

A bus transceiver contains pairs of three-state buffers connected in opposite directions between each pair of pins, so that data can be transferred in either direction. For example, Figure 6-56 shows the logic diagram and symbol for a 74x245 octal three-state transceiver. The DIR input determines the direction of transfer, from A to B (DIR = 1) or from B to A (DIR = 0). The three-state buffer for the selected direction is enabled only if G_L is asserted.

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6.6.5 Three-State Output in Verilog Verilog has built-in bit-data value ‘z’ for the high-Z state so it is easy to specify three-state outputs. Table 6-39 is a Verilog module for an 8-bit three-state buffer similar to the 74x540. Using with the conditional ( ?: ), it takes just one continuous-assignment statement to specify the output, a copy of the input if the device is enabled, and eight bits of "z" otherwise.

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The preceding example used its three-state port for output only, but output ports can be used as inputs as well if they are declared as type "inout". This capability would be used in a transceiver application with functionality similar to the 74x245 (Figure 6-56 on page 422). A corresponding Verilog module is shown in Table 6-40.

6.7 Multiplexers A multiplexer (mux) is a digital switch, it connects data from one of n sources to its output. Figure 659(a) shows the inputs and outputs of an n-input, b-bit multiplexer. There are n sources of data, each of which is b bits wide, and there are b output bits. In commercially available multiplexers, n = 1, 2, 4, 8, or 16, and b = 1, 2, or 4. There are s inputs that select among the n sources, so s = [log2n]. An enable input EN allows the multiplexer to "do its thing"; when EN = 0, all of the outputs are 0.

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Figure 6-59(b) shows a switch circuit that is roughly equivalent to the mux. However, unlike a mechanical switch, a multiplexer is a unidirectional device: information flows only from inputs (on the left) to outputs (on the right). Multiplexers are useful devices in applications in which data must be switched from multiple sources to a destination. One common use in microprocessor systems is in input/output (I/O) devices that have several registers for storing data and control information, where any one of those registers may be selected periodically to be read by software. Suppose there are eight 32-bit registers, and a 3-bit field in the I/O address selects which one to read. This 3-bit field gets connected to the select inputs of an 8-input, 32-bit multiplexer. The mux's data inputs are connected to the eight registers, and its data outputs are connected to the microprocessor's data bus to read the selected register. 6.7.1 Standard MSI Multiplexers At one extreme is the 74x151, shown in Figure 6-60, which selects among eight 1-bit inputs. The select inputs are named C (S2), B (S1), and A (S0), where C is most significant numerically. The enable input EN_L is active low: and both active-high (Y) and active-low (Y_L) versions of the output are provided.

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The 74x151's truth table is shown in Table 6-42. Here we have once again extended our notation for truth tables. Up until now, our truth tables have specified an output of 0 or 1 for each input combination. In the 74x151's table, only the "control" inputs are listed under the "Inputs" heading. Each output is specified as 0, 1, or a simple logic function of the "data" inputs (e.g., D0 or D0'). This notation saves eight columns and eight rows in the table.

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At the other extreme of muxes we have the 74x157 shown in Figure 6-61, which selects between two 4bit inputs. The extended truth-table notation makes the 74xl57's description very compact as shown in Table 6-43. Intermediate between the 74x151 and 74x157 is the 74x153, a 4-input 2-bit multiplexer with separate enable inputs for each output bit.

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Some multiplexers have three-state outputs. The enable input of such a multiplexer, instead of forcing the outputs to zero, forces them to the Hi-Z state. For example, the 74x251 is identical to the '151 except that Y and Y_L are three-state outputs. When the EN_L input is negated, instead of forcing the outputs to be negated, it forces the outputs into the Hi-Z state. Similarly, the 74x257 is a three-state version of the '157. Three-state outputs are especially useful when n-input muxes are combined to form larger muxes. 6.7.2 Expanding Multiplexers Seldom does the size of an MSI multiplexer match the characteristics of the problem at hand. For example, suppose we needed a 32-input, 1-bit mux. Figure 6-62 shows one way to build it. Five select bits are required. A 74x138 is used as a 2-to-4 decoder for the two high-order select bits to enable one of four 74x151 8-input multiplexers. Since only one '151 is enabled at a time, the ‘151 outputs can simply be ORed to obtain the final output.

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6.7.3 Multiplexers, Demultiplexers, and Buses A multiplexer can be used to select one of n sources of data to transmit on a bus. At the far end of the bus, a demultiplexer can be used to route the bus data: to one of m destinations. Such an application, using a 1-bit bus, is depicted in terms of our switch analogy in Figure 6-64(a). In fact, block diagrams for logic circuits often depict multiplexers and demultiplexers using the wedge-shaped symbols in (b) to suggest

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visually how a selected one of multiple data sources gets directed onto a bus and routed to a selected one of multiple destinations.

The function of a demultiplexer is just the inverse of a multiplexer's. For example, a 1-bit, n-output demultiplexer has one data input and s inputs to select one of n = 2s data outputs. In normal operation, all outputs except the selected one are 0; the selected output equals the data input. This definition may be generalized for a b-bit, n-output demultiplexer; such a device has b data inputs and its s select inputs choose one of n = 2s sets of b data outputs.

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A binary decoder with an enable input can be used as a demultiplexer, as shown in Figure 6-65.

The decoder's enable input is connected to the data line, and its select inputs determine which of its output lines is driven with the data bit. The remaining output lines are negated. Thus, the 74x138 can be used as a 1-bit, 8-output demultiplexer. 6.7.6 Multiplexers in Verilog Muxes are very easy to describe in Verilog. In the dataflow style, a series of conditional operators ( ?: ) can provide the required functionality, as shown in Table 6-51, a Verilog module for a 4-input, 8-bit multiplexer.

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In a behavioral architecture, a case statement can be used. For example, Table 6-52 is a module using an always block and case statement for the same mux entity.

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6.8 Exclusive-OR Gates and Parity Circuits 6.8.1 Exclusive-OR and Exclusive-NOR Gates An Exclusive-OR (XOR) gate is a 2-input gate whose output is 1 if exactly one of its inputs is 1. Stated another way, an XOR gate produces a 1 output if its inputs are different. An Exclusive NOR (XNOR) or Equivalence gate is just the opposite, it produces a 1 output if its inputs are the same. A truth table for these functions is shown in Table 6-54.

The XOR operation is sometimes denoted by the symbol ! , that is, X ! Y = (X' • Y) + (X • Y') Although EXCLUSIVE OR is not one of the basic functions of switching algebra, discrete XOR gates are commonly used. Most switching technologies cannot perform the XOR function directly; instead, they use designs like the ones shown in Figure 6-68.

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Tbe logic symbols for XOR and XNOR functions are shown in Figure 6-69. There are four equivalent symbols for each function. All of these alternatives are a consequence of a simple rule: any two signals (inputs or output) of an XOR or XNOR gate may be complemented without changing the resulting logic function.

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6.8.2 Parity Circuits As shown in Figure 6-70(a), n XOR gates may be cascaded to form a circuit with n + 1 inputs and a single output. This is called an odd-parity circuit, because its output is 1 if an odd number of its inputs are 1. The circuit in (b) is also an odd-parity circuit, but it's faster because its gates are arranged in a treelike structure. If the output of either circuit is inverted, we get an even-parity circuit, whose output is 1 if an even number of its inputs are 1.

6.8.3 The 74x280 9-Bit Parity Generator Rather than build a multi-bit parity circuit with discrete XOR gates, it is more economical to put all of the XORs in a single MSI package with just the primary inputs and outputs available at the external pins. The

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74x280 9-bit parity generator, shown in Figure 6-71, is such a device. It has nine inputs and two outputs that indicate whether an even or odd number of inputs are 1.

6.8.4 Parity-Checking Applications In Section 2.15 we described error-detecting codes that use an extra bit, called a parity bit, to detect errors in the transmission and storage of data. In an even-parity code, the parity bit is chosen so that the total number of 1 bits in a code word is even. Parity circuits like the 74x280 are used both to generate the correct value of the parity bit when a code word is stored or transmitted and to check the parity bit when a code word is retrieved or received. Figure 6-72 shows how a parity circuit might be used to detect errors in the memory of a microprocessor system. The memory stores 8-bit bytes plus a parity bit for each byte. The microprocessor uses a bidirectional bus D[0:7] to transfer data to and from the memory. Two control lines, RD and WR, are

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used to indicate whether a read or write operation is desired, and an ERROR signal is asserted to indicate parity errors during read operations. Complete details of the memory chips, such as addressing inputs, are described in detail in Chapter 9. For parity checking, we are concerned only with the data connections to the memory.

To store a byte into the memory chips, we specify an address (not shown), place the byte on D[0-7], generate its parity bit on PIN, and assert WR. The AND gate on the I input of the 74x280 ensures that I is 0 except during read operations so that during writes the '280's output depends only on the parity of the D-bus data. The '280's ODD output is connected to PIN, so that the total number of 1s stored is even. To retrieve a byte, we specify an address (not shown) and assert RD; the byte value appears on DOUT[0-7] and its parity appears on POUT. A 74x541 drives the byte onto the D bus, and the '280 checks its parity. If the parity of the 9-bit word DOUT[0-7], POUT is odd during a read, ERROR is asserted.

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6.8.7 Exclusive-OR Gates and Parity Circuits in Verilog In Verilog, the XOR and XNOR functions are performed by the ( ^ ) and ( ~ ^ ) operators, respectively. For example, Table 6-59 is a dataflow-style program for a 3-input XOR device using the XOR operator.

It's also possible to specify the XOR or parity functions behaviorally, as Table 6-60 does for a 9-input parity function similar to the 74x280.

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6.9 Comparators Comparing two binary words for equality is a commonly used operation in computer systems and device interfaces. A circuit that compares two binary words and indicates whether they are equal is called a comparator. Some comparators interpret their input words as signed or unsigned numbers and also indicate an arithmetic relationship (greater or less than) between the words. These devices are often called magnitude comparators. 6.9.1 Comparator Structure Exclusive-OR and Exclusive-NOR gates may be viewed as 1-bit comparators. Figure 6-74(a) shows an interpretation of a 2-input XOR gate (e.g. 74x86) as a 1-bit comparator. The active-high output, DIFF, is asserted if the inputs are different. The outputs of four XOR gates are ORed to create a 4-bit comparator in (b). The DIFF output is asserted if any of the input-bit pairs are different. We can build an n-bit comparator using n XOR gates and an n-input OR gate.

Comparators can also be built using Exclusive-NOR (XNOR) gates. A 2-input XNOR gate produces a 1 output if its two inputs are equal. A multi-bit comparator can be constructed using one XNOR gate per bit, and ANDing all of their outputs together. The output of that AND function is 1 if all of the individual bits are pairwise equal.

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The n-bit comparators in this subsection are sometimes called parallel comparators because they look at each pair of input bits simultaneously and deliver the 1-bit comparison results in parallel to an n-input OR or AND function. It is also possible to design an "iterative comparator" that looks at its bits one at a time using a small, fixed amount of logic per bit. Before looking at an iterative comparator design, you should understand the general class of "iterative circuits” . 6.9.2 Iterative Circuits An iterative circuit is a special type of combinational circuit, with the structure shown in Figure 6-76.

The circuit contains n identical modules, each of which has both primary inputs and outputs and cascading inputs and output. The leftmost cascading inputs are called boundary inputs and are connected to fixed logic values in most iterative circuits. The rightmost cascading outputs are called boundary outputs and usually provide important information. Iterative circuits are well suited to problems that can be solved by a simple iterative algorithm: 1. Set C0 to its initial value and set i to 0. 2. Set Ci and PIi to determine the values of POi and Ci+1 3. Increment i.

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4. If i < n, go to step 2. In an iterative circuit, the loop of steps 2-4 is "unwound" by providing a separate combinational circuit that performs step 2 for each value of i. Examples of iterative circuits are the comparator circuit in the next subsection and the ripple adder in Section 6.10.2 (note they will generally be slower than parallel circuits). 6.9.3 An Iterative Comparator Circuit Two n-bit values X and Y can be compared one bit at a time using a single bit EQi at each step to keep track of whether all of the bit-pairs have been equal so far: 1. Set EQ0 to 1 and set i to 0. 2. If EQi is 1 and Xi and Yi are equal, set EQi+ l to 1. Else set EQi+1 to 0. 3. Increment i. 4. If i < n, go to step 2. Figure 6-77 shows a corresponding iterative circuit.

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6.9.4 Standard MSI Magnitude Comparators The 74x85 is a 4-bit comparator with the logic symbol shown in Figure 6-78. It provides a greater-than output (AGTBOUT) and a less-than output (ALTBOUT) as well as an equal output (AEQBOUT). The '85 also has cascading inputs (AGTBIN, ALTBIN, AEQBIN) for combining multiple '85s to create comparators for more than four bits. Both the cascading inputs and the outputs are arranged in a l-out-of-3 code, since in normal operation exactly one input and one output should be asserted.

6.9.8 Comparators in Verilog Verilog has built-in comparison operators: >, >=,