Edited by Chu Yu
Verilog HDL
Verilog Hardware Description Language (Verilog HDL)
Edited by Chu Yu http://ece.niu.edu.tw/~chu/
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Edited by Chu Yu
Verilog HDL
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Verilog HDL
Verilog HDL
Brief history of Verilog HDL ¾ 1985: Verilog language and related simulator Verilog-XL were developed by Gateway Automation. ¾ 1989: Cadence Design System purchased Gateway Automation. ¾ 1990: Open Verilog International formed. ¾ 1995: IEEE standard 1364 adopted.
Features of Verilog HDL ¾ Ability to mix different levels of abstract freely. ¾ One language for all aspects of design, testing, and verification.
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Verilog HDL
Verilog HDL z
HDL – Hardware Description Language A programming language that can describe the functionality and timing of the hardware.
z
Why use an HDL? It is becoming very difficult to design directly on hardware. It is easier and cheaper to different design options. Reduce time and cost. 4
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Verilog HDL
Programming LanguageHDL V.S. Verilog HDL Verilog ¾ Programming Language if (a>b) compiler { … }
sub a, b assembler … … …
(C code)
(asm code)
Computer
(CPU)
¾ Verilog HDL if (a>b) begin … end (Verilog code)
I0 I1
synthesizer
In a b
M
out
a>b (logic circuit)
(cell library)
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Verilog HDL
Verilog HDL z
Verilog-XL is an event-driven simulator that can emulate the hardware described by Verilog HDL.
z
Verilog-HDL allows you to describe the design at various levels of abstractions within a design. Behavioral Level RTL Level Gate Level Switch Level
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Verilog HDL
Time Wheel in Event-Driven Simulation Event queues at each time stamp
Et An event Et at time t Schedules another event at time t + 2
t t+1 t+2
z Time advances only when every event scheduled at that time is executed. 7
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Verilog HDL
Different Levels of Abstraction z
Architecture / Algorithmic (Behavior) A model that implements a design algorithm in high-level language construct. A behavioral representation describes how a particular design should responds to a given set of inputs.
z
Register Transfer Logic (RTL) A model that describes the flow of data between registers and how a design process these data.
z
Gate Level (Structure) A model that describes the logic gates and the interconnections between them.
z
Switch Level A model that describes the transistors and the interconnections between them. 8
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Verilog HDL
Three Levels of Verilog-HDL Behavioral Level (RTL)
Switch Level // AND gate of u2 pmos p0(VDD, nand, A), p1(VDD, nand, B); nmos n0(nand, wire1, A), n1(wire1, GND, B);
assign {Co, Sum} = A + B + Ci Gate Level xor xor and and or
u0(.z(hs), .a1(A), .a2(B)); u1(.z(Sum), .a1(Ci), .a2(hs)); u2(.z(hc0), .a1(A), .a2(B)); u3(.z(hc1), .a1(Ci), .a2(hs)); u4(.z(Co), .a1(hc0), .a2(hc1));
pmos p2(VDD, hc0, nand); nmos n2(hc0, GND, nand); M
U0 U1
hs
A B
Sum U2 U3 1
U4 3
1
2
3
hc1
1
2
3 2
Co
hc0 Cin
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Verilog HDL
Top-Down Design Flow in ASIC
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Verilog HDL
Top Down ASIC Design Flow Idea and Specification
Behavioral Modeling … sum = a + b; …
Behavior Model (Verilog HDL or C language)
Verification (Verilog-XL)
Partitioning and Re-modeling Logic Blocks with Function Definition … always @( a or b or c) {carry, sum} = a+b+c; …
RTL Modeling RTL Model (Verilog HDL)
Verification (Verilog-XL)
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Verilog HDL
Top Down ASIC Design Flow(Con’t) RTL Model (Verilog HDL)
Logic Synthesis (Synopsys) … xo03d1 u0(sum,a,b,c); an02d1 u1(g2,a,b); …
Gate Level Netlist (Verilog HDL)
Verification (Verilog-XL)
Physical Design (CELL3 Ensemble)
ASIC Libraries (Compass cell library)
GDS II 12
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Verilog HDL
Verilog-HDL Simulators VCS (Synopsys) ¾ Platform Windows NT/XP, SUN Solaris (UNIX), Linux. Modelsim (Mentor) ¾ Platform Windows NT/XP, SUN Solaris (UNIX), Linux. NC-Verilog (Cadence) ¾ Platform Windows NT/XP, SUN Solaris (UNIX), Linux. Verilog-XL (Cadence) ¾ Platform SUN Solaris (UNIX).
Other Simulators ¾ MAX+PLUS II, Quartus II (Altera) ¾ Active HDL (Aldec), Silos (Silvaco), … 13
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Verilog HDL
Overview of Verilog Module z A Verilog module includes the following parts: module module_name (port_name); port declaration data type declaration Task & function declaration module functionality or declaration timing specification endmodule
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Verilog HDL
Example of Adder z
A Full Adder module name
module adder (carry, sum, a, b, cin); output carry, sum; I/O pins input a, b, cin; I/O pin declaration wire w0, w1, w2;
a b cin
sum
U0
a b
U1
w0
a
xor u0(sum, a, b, cin); and u1(w0, a, b); and u2(w1, b, cin); and u3(w2, cin, b); or u4(carry, w0, w1, w2)
cin
U2
w1
U4
carry
b cin
U3
w2
endmodule logic circuit description
build-in module invoked
instantiation
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Verilog HDL
Three Levels of Abstraction z
A Full Adder module adder (carry, sum, a, b, cin); output carry, sum; input a, b, cin; reg sum, carry;
module adder (carry, sum, a, b, cin); output carry, sum; input a, b, cin; assign {carry, sum} = a + b + cin; endmodule //RTL level
always @(a or b or cin) {carry, sum} = a + b + cin; endmodule //behavioral level module adder (carry, sum, a, b, cin); output carry, sum; input a, b, cin; wire w0, w1, w2;
a b cin a b
xor u0(sum, a, b, cin); and u1(w0, a, b); and u2(w1, b, cin); and u3(w2, cin, b); or u4(carry, w0, w1, w2) endmodule //gate level
sum
U0
U1
w0
a cin
U2
w1
U4
carry
b cin
U3
w2
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Verilog HDL
Identifiers of Verilog z Identifiers are user-provided name for Verilog objects within a description. z Legal characters in identifiers: a-z, A-Z, 0-9, _, $
z The first character of an identifier must be an alphabetical character (a-z, A-Z) or an underscore (_). z Identifiers can be up to 1024 characters long. Example: Mux_2_1 abc123 ABC123 Sel_ A$b$10 17
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Verilog HDL
Escaped Identifiers z Escaped Identifiers start with a backslash (\) and end with a white space. z They can contain any printable ASCII characters. z Backslash and white space are not part of the identifiers. Example: module \2:1mux(out, a, b, sel); not u0(\~out, in);
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Verilog HDL
Case Sensitivity z Verilog is a case-sensitive language. z You can run Verilog in case-insensitive mode by specifying –u command line option. Example: module inv(out, in); … endmodule
module Inv(out, in); … endmodule
// Both inv and Inv are viewed as two different modules.
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Verilog HDL
Verilog-HDL Structural Language z
Verilog Module Modules are basic building blocks in hierarchy. Every module description starts with module name(output_ports, input_ports), and ends with endmodule.
z
Module Ports Module ports are equivalent to the pins in hardware. Declare ports to be input, output, or inout (bidirectional) in the module description.
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Verilog HDL
Nets and Registers z Nets: nets are continuously driven by the devices that drive them. wire, wor, wand, ... - example : wire [7:0] w1,w2; wire [0:7] w1; - if wire is not vector type, then it doesn’t need to declaration. z Registers: registers are used extensively in behavioral modeling and in applying stimulus. reg - example: reg [3:0] variable; 21
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Verilog HDL
Registers z More Examples reg mem1[127:0]; //128-bit memory with 1-bit wide reg mem2[63:0]; reg [7:0] mem3[127:0]; //128-bit memory with 8-bit wide M mem2=0; // illegal syntax mem2[5] = mem1[125]; mem2[10:8] = mem1[120:118]; mem3[11]=0; //8-bit zero value
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Verilog HDL
Other Types of Nets z Various net types are available for modeling designspecific and technology-specific functionality. Net Types
Functionality
wire, tri wand, triand trireg tri1 tri0 supply1 supply0
For multiple drivers that are Wired-OR For multiple drivers that are Wired-AND For nets with capacitive storeage For nets with weak pull up device For nets with weak pull down device Power net Ground net
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Verilog HDL
Example of Nets z Example I
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Verilog HDL
Example of Nets z Example II
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Verilog HDL
True Tables for tri, triand, and trior Nets
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Verilog HDL
Logic Level Modeling z Built-in primitive functions Gates
and nand nor or xor xnor not
buf bufif0 bufif1 notif0 notif1 pullup pulldown
MOS Switches and Bidirectional Transistors nmos pmos cmos rnmos rpmos rcmos
tran tranif0 tranif1 rtran rtranif0 rtranif1
Nets
wire wand wor tri triand trior trireg
supply0 supply1 trireg tri1 tri0
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Verilog HDL
Switch Level Modeling ctl nMOS (unidirectional)
in
out
nmos(out, in, ctl);
out
pmos(out, in, ctl);
ctl pMOS (unidirectional)
in pctl
cMOS (unidirectional)
in
out
cmos(out, in, nctl, pctl);
nctl 28
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Verilog HDL
Operators Used in Verilog (Cont.) z Verilog Language Operators
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Verilog HDL
Operators Used in Verilog (Cont.) Precedence Rules for Operators
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Verilog HDL
Operators Used in Verilog (Cont.) The Relational Operators Defined
The Equality Operators Defined
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Verilog HDL
Equality and Identity Operators
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Verilog HDL
Operators ¾ Unary Operator assign a = ~b; ¾ Binary Operator assign a = b&c; ¾ Ternary Operator assign out = sel ? a: b; //2-to-1 multiplexer
Comments ¾ One Line Comment // this is an example of one line comment ¾ Multiple Line Comment /* this is an example of multiple line comment */ ¾ Error Comment Remarks /* Error comment remark */ */
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Verilog HDL
Operators Used in Verilog z Index: example: a[11:6], b[2], ...
z Concatenation: {n{ *}} adder4 a1(sum,carry,{a[2],a[2:0]},b[3:0]); assign {carry, sum} = a+b+ci; sign = {4{in[3]}, in}; temp = 2’b01; out = {2{2’b10}, 2’b11, temp}; //out=8’b1010_1101
z Arithmetic operation: +,-,* example: a=b+c; x=y*z;
z Condition: = =, !=, >, =, q) = (0.390, 0.390); … $setup(d, posedge clk, Tsetup$d_cp, notifier); perform timing check $hold(posedge clk, d, Thold$d_cp, notifier); … endspecify endmodule
}
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Verilog HDL
Starting the Verilog-XL Simulation
UNIX Environment verolog Example 1: unix> verilog adder.v Example 2: unix> verilog file1.v file2.v file3.v or unix> verilog –f file4 file4 content in the text mode: file1.v file2.v file3.v 96
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Verilog HDL
Testing and Verification of Full Adder Test Fixture Stimulus and Control
a b cin
Full Adder
sum carry
Response Generation and Verification
z Test the full adder’s Verilog model by applying test patterns and observing its output responses. Stimulus and control: Changes on device inputs, simulation finish time, ... etc. Device under test: Behavior, gate, or switch level modules. Response generation and verification: Which signals to save/display, verification of generated response. 97
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Verilog HDL Circuit Description module add4(sum, carry, A, B, Cin); output [3:0] sum; …… endmodule
Testfixture module testfixture; reg [3:0] A, B; …… endmodule
Verilog Simulation Verilog Parser Simulation Engine
User Interface
0.00 ns in = 0 out = x 16.00 ns in = 0 out = 1 100.00 ns in = 1 out = 1 …… 98
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Verilog HDL
Example with a Test Fixture z
A Full Adder module adder (carry, sum, a, b, cin); output carry, sum; input a, b, cin; wire w0, w1, w2;
module testfixture; reg a, b, cin; wire sum, carry; adder u0 (carry, sum, a, b, cin);
xor u0(sum, a, b, cin); and u1(w0, a, b); and u2(w1, b, cin); and u3(w2, cin, b); or u4(carry, w0, w1, w2) endmodule
initial begin $monitor($time, “a=%b b=%b cin=%b sum=%b carry=%b”, a, b, cin, sum, carry); a=0; b=0; cin=0; #10 a=0; b=0; cin=1; #10 a=0; b=1; cin=0; #10 a=0; b=1; cin=1; #10 a=1; b=0; cin=0; #10 a=1; b=0; cin=1; #10 a=1; b=1; cin=0; #10 a=1; b=1; cin=1; #10 $stop; #10 $finish; end endmodule
This will generate some text outputs as 0 a=0 b=0 c=0 sum=0 carry=0 10 a=0 b=0 c=1 sum=1 carry=0 … … 99
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Verilog HDL
Useful System Tasks z Always and Initial ¾ always ¾ initial – $stop: Stopping the simulation. – $finish: Finishing the simulation.
z Monitoring Commands ¾ Text Format Output • $monitor($time,''a=%d, b=%b,...\n'',a,b); ¾ Graphic Output • $gr_waves('''',, ...); • $SimWave: $shm_open(“”), $shm_probe( ) 100
Edited by Chu Yu
Verilog HDL
Monitor System Task z Any expression parameter that has no corresponding format specification is displayed using the default decimal format. %h or %H
display in hexadecimal format
%d or %D
display in decimal format
%o or %O
display in octal format
%b or %B
display in binary format
%c or %C
display in ASCII character format
%v or %V
display net signal strength
%n or %N
display net normalized voltage in Switch-RC
%m or %M
display hierarchical name
%s or %S
display as a string
%t or %T
display in current time format 101
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Verilog HDL
SimWave z Using system tasks to save the circuit state into waveform database. z You can use SimWave to view the signal waveforms after Verilog-XL simulation. z Example module testfixture; …… initial begin $shm_open(“adder.shm”); $shm_probe(“A”); …… #10 $finish; end endmodule 102
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Verilog HDL
SimWave Window
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Verilog HDL
Trouble Shooting z If a=b is triggered by some event, a must be declared as reg. z A bus signal must be declared as wire. z The negative value should be sign-extended. z The port size and number of a module should match anywhere it is referred.
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