2009 IEEE International SOI Conference

Foster City, California, USA 5 – 8 October 2009

IEEE Catalog Number: ISBN:

CFP09SOI-PRT 978-1-4244-4256-0

TABLE OF CONTENTS

SESSION 1 PLENARY FDSOI for Low Power CMOS..........................................................................................................................................1 G. Shahidi

Review of FinFET Technology.........................................................................................................................................3 M.Jurczak, N.Collaert, A.Veloso, T.Hoffmann, S.Biesemans

A Guided Tour of Electronic Design Automation (EDA) for Design of Silicon on Insulator (SOI) SoCs................7 K. Kranen

SESSION 2 NOVEL LAYER TRANSFER APPLICATIONS Silicon-on-Glass (SiOG) Substrate Technology: Process and Materials Properties...................................................9 J. S. Cites, J. G. Couillard, K. P. Gadkaree

Submicron Single Crystal Si TFTs on a Large Glass Substrate...............................................................................N/A Y. Takafuji, Y. Fukushima, K. Tomiyasu, M. Takei, M. Moriguchi, Y. Ogawa, T. Itoga, H. Kobayashi, Y. Watanabe, E. Kobayashi, S. R. Droes, A.T. Voutsas, J. Hartzell

Demonstration of Low Temperature CMOS Devices on SiOG and SOI Substrates................................................11 C. Kosik Williams, J.G. Couillard, J. Senawiratne, R.G. Manley, P.M. Meller, C.G. Shea, A.M. McCabe, K.D. Hirschman

From Silicon Direct Wafer Bonding to Surface Nano-Patterning: a Way to Innovative Substrate Elaboration.......................................................................................................................................................................13 F. Fournel, A. Bavard, J. Eymery

High-Efficiency Solar Cell Embedded in SOI Substrate for ULP Autonomous Circuits.........................................17 O. Bulteel, R. Delamare, D. Flandre

Thermal Actuation of High Frequency Micromechanical Resonators.......................................................................19 A. Rahafrooz, A. Hajjam, S. Pourkamali

Overview of SOI Technologies in China........................................................................................................................21 M.Chen, Y.B.Wang

SESSION 3 SRAM, 1T DRAM, & IMAGERS SRAM Cell Design Considerations for SOI Technology..............................................................................................25 T-J King Liu, C. Shin, M. H. Cho, X. Sun, B. Nikolić, B.-Y. Nguyen

Investigation of Static Noise Margin of FinFET SRAM Cells in Sub-Threshold Region.........................................29 M.-L. Fan, Y.-S. Wu, V. P.-H. Hu, P. Su, C.-T. Chuang

Analyze of Temporal and Random Variability of a 45nm SOI SRAM Cell..............................................................31 Y. Laplanche

Impact of FinFET Technology on 6T-SRAM Performance........................................................................................33 S. O’uchi, T. Nakagawa, T. Matsukawa, Y.X. Liu, K. Endo, T. Sekigawa, K. Sakamoto, H. Koike, M. Masahara

SRAM Yield Enhancement with Thin-BOX FD-SOI..................................................................................................35 C. Shin, M. H. Cho, Y. Tsukamoto, B.-Y. Nguyen, B. Nikolić, T.-J. King Liu

Analysis of Sense Margin and Reliability of 1T-DRAM Fabricated on Thin-Film UTBOX Substrates.................37 N. Collaert, M. Aoulaiche, M. Rakowski, B. De Wachter, K. Bourdelle, B.-Y. Nguyen, F. Boedt, D. Delprat, M. Jurczak

Effect of Source/Drain Asymmetry on the Performance of Z-RAM® Devices..........................................................39 N. R. Mohapatra, R. van Bentum, E. Pruefer, W. P. Maszara, C. Caillat, Z. Chalupa, Z. Johnson, D. Fisch

Wafer Stacking: Key Technology for 3D Integration..................................................................................................41 C. Lagahe-Blanchard, B. Aspar

SESSION 4 POSTERS Design and Fabrication of SOI-Based MEMS for Mechanical Memory Storage......................................................45 A. Parent, C.-M. Tassetti, J. Haussy, A. Tissot

Engineering Silicon-On-Insulator (SOI) Substrates for Hybrid Orientation Technologies (HOT)........................47 T. Signamarcheix, B. Biasse, A-M. Papon, E.Nolot, B.Ghyselen, L. Clavelier

Thermal Sensing Performance of Lateral SOI PIN Diodes in the 90 – 400 K Range...............................................49 M. de Souza, B. Rue, D. Flandre, M. A. Pavanello

LDD Depletion Effects in Thin-BOX FDSOI Devices with a Ground Plane.............................................................51 R. Yan, R. Duane, P. Razavi, A. Afzalian, I. Ferain, C.W. Lee, N. Dehdashti-Akhavan, K. Bourdelle, B.Y. Nguyen, J.P. Colinge

Fabrication of Compressively-Strained GeOI Substrates Using the Smart CutTM Technology..............................53 E. Augendre, L. Sanchez, J.-M. Hartmann, W. Van Den Daele, S. Favier, E. Guiot, B. Ghyselen, K.. Bourdelle, S. Cristoloveanu, T. Billon, L. Clavelier

LDMOS Transistors on Si-on-SiC Hybrid Substrates Having Crystalline or Poly-Crystalline SiC Electrical and Thermal Characterization......................................................................................................................55 Ö. Vallin, L.-G. Li, H. Norström, U. Smith, J. Olsson

Transconductance Ramp Effect in High-k Triple Gate sSOI nFinFETs...................................................................57 J. A. Martino, P. G. D. Agopian, N. Collaert, E. Simoen, C. Claeys

Germanium MOS Transistors on Sapphire and Alumina Platforms.........................................................................59 P. T. Baine, H. S. Gamble, B. M. Armstrong, S. J. N. Mitchell, D. W. McNeill, P. V. Rainey, Y. H. Low, Y. W. Low, D. Tantraviwat

Novel Architecture for Inertial Grade SOI MEMS Inertial Sensors..........................................................................61 A. A. Aziz, A.-H. Sharaf, M. Serry, S. Sedky

Effect of Substrate Rotation on the Analog Performance of Triple-Gate FinFETs..................................................63 M. A. Pavanello, J. A. Martino, E. Simoen, N. Collaert, C. Claeys

A New Technique for Localized Formation of SOI Active Regions............................................................................65 B. Veeramachaneni, J. Winans, P.M. Fauchet, K. Witt, K.D. Hirschman

An Internally Amplified Signal SOI Nano-bridge Biosensor for Electrical Detection of DNA Hybridization.......67 K. B. Parizi, N. Melosh, Y. Nishi

Quantum Confinement Effect in Short-Channel Gate-All-Around MOSFETs and Its Impact on the Sensitivity of Threshold Voltage to Process Variations................................................................................................69 Y.-S. Wu, P. Su

SESSION 5 SOI DESIGN SOI Design for a High-Performance IO Interface........................................................................................................71 K. Chang, T. Wu, K. Kaviani, J-H Chun

Physical IP Design for Advanced SOI Technologies....................................................................................................75 Y. Laplanche, J-L Pelloie, C. Frey, M. Rien

Ultra-Low-Power High-Noise-Margin Logic with Undoped FD SOI Devices...........................................................79 D. Bol, J. De Vos, D. Flandre, J.-D. Legat

Multiple Independent Gate FET Ring Oscillators with Dynamic Frequency Tuning..............................................81 D. G. Wilson, B. N. Meek, K. J. DeGregorio, D. R. Hackler

Enhanced Performance of SERDES Current-Mode Output Driver Using 0.13 μm PD SOI CMOS......................83 D. Kamel, M. Dessouky, D. Flandre

SESSION 6 SOI APPLICATIONS Silicon-on-Sapphire, A Replacement for Gallium Arsenide?......................................................................................85 G.. P. Imthurn

Channel Engineering of SOI MOSFETs for RF Applications....................................................................................88 C. L. Chen, J. M. Knecht, J. Kedzierski, C. K. Chen, P. M. Gouker, D-R. Yost, P. Healey, P. W. Wyatt, C. L. Keast

DC and RF Temperature Behavior of Deep Submicron Graded Channel MOSFETs.............................................90 M. Emam, A. Kumar, J. Ida, F. Danneville, D. Vanhoenacker-Janvier, J.-P. Raskin

45 GHz Silicon MESFETs on a 0.15 μm SOI CMOS Process.....................................................................................92 W. Lepkowski, S.J. Wilk, T.J. Thornton

SESSION 7 3D TECHNOLOGY Three Dimensional Integration – Memory Applications.............................................................................................94 S.S. Iyer

Radiation Effects in MIT Lincoln Laboratory’s 3DIC Technology............................................................................99 P. M. Gouker, P. W. Wyatt, D-R. Yost, C. K. Chen, J. M. Knecht, C. L. Chen, C. L. Keast

Results on Aligned SiO2/SiO2 Direct Wafer-to-Wafer Low Temperature Bonding for 3D Integration...............101 A. Garnier, M. Angermayer, L. Di Cioccio, P. Gueguen, T. Wagenleitner

SESSION 8 FDSOI TECHNOLOGY FD-SOI MOSFETs for the Low-Voltage Nanoscale CMOS Era..............................................................................103 K. Itoh, N. Sugii, D. Hisamoto, R. Tsuchiya

Comparison of Ultra-Low-Power and Static CMOS Full Adders in 0.15 μm FD SOI CMOS..............................107 D. Kamel, D. Bol, F.-X. Standaert, D. Flandre

Platinum Silicide Metallic Source and Drain Process Optimization for FDSOI pMOSFETs................................109 V. Carron, F. Nemouchi, Y. Morand, T. Poiroux, M. Vinet, S. Bernasconi, O. Louveau, D. Lafond, V. Delaye, F. Allain, S. Minoret, L. Vandroux, T. Billon

Expanding Opportunities of Ultra Low Power and Harsh Applications with Fully Depleted (FD) SOI..............111 J. Ida, K. Tani, M.Ohono, M.Yanagihara, Y. Igarashi, K. Sakamoto

Modeling of Electron Tunneling in SOI-MOSFET and Its Influence on Device Characteristics..........................113 T. Hayashi, N. Sadachika, T. Murakami, D. Sugiyama, S. Yukuta, S. Kusu, K. Johguchi, M. Miyake, H. J. Mattausch, M. Miura-Mattausch, S. Baba, J. Ida

New Method to Extract Interface States Density at the Back and the Front Gate Interfaces of FDSOI Transistors from CV-GV Measurements.......................................................................................................115 L. Brunet, X. Garros, F. Andrieu, G. Reimbold, E. Vincent, A. Bravaix, F. Boulanger

SESSION 9 SUBSTRATE TECHNOLOGY SOI Substrate Readiness for 22/20 nm and for Fully Depleted Planar Device Architectures................................117 D. Delprat, F. Boedt, C. David, P. Reynaud, A. Alami-Idrissi, D. Landru, C. Girard, C. Maleville

Thermal Considerations for Advanced SOI Substrates Designed for III-V/Si Heterointegration........................121 N. Yang, M. T. Bulsara, E. A. Fitzgerald, W.K. Liu, D. Lubyshev, J.M. Fastenau, Y. Wu, M. Urteaga, W. Ha, J. Bergman, B. Brar, C. Drazek, N. Daval, L. Benaissa, E. Augendre, W.E. Hoke, J.R. LaRoche, K.J. Herrick, T.E. Kazior

Investigation of Ion Implantation Induced Electrically Active Defects in p-Type Silicon......................................123 J. Senawiratne, J. S. Cites, J. G. Couillard, J. Moll, C. A. Kosik Williams, P. G. Whiting

PD-SOI MOSFETs: Interface Effect on Point Defects and Doping Profiles............................................................125 E.M. Bazizi, A. Pakfar, P. F. Fazzini, F. Cristiano, C. Tavernier , A. Claverie, A. Burenkov, P. Pichler

SESSION 10 NANOWIRES & ADVANCED DEVICES The SiGe Heterojunction Source PNPN n-MOSFET with SSOI for Low Power Application...............................127 H-Y Chang, N. Venkatagirish, A. Tura, R. Jhaveri, J. Woo

Optimal Design and Performance Assessment of Extremely-Scaled Si Nanowire FET on Insulator...................129 C.-Y. Chen, Y.-B. Liao, M.-H. Chiang, K. Kim, W.-C. Hsu, S.-Y. Cheng

Investigation of Bias-Dependent Series Resistances and Barrier Height in Double Gate Schottky MOSFETs.......................................................................................................................................................131 J. Bhandari, M. Vinet, T. Poiroux, J. M. Sallese, B. Previtali, S. Deleonibus, A. M. Ionescu

Variable-Barrier Tunneling SOI Transistor (VBT)...................................................................................................133 A. Afzalian, N. Dehdashti, I. Ferain, C.W. Lee, R. Yan, P. Razavi, J.P Colinge

High Temperature Performance of OTA with Non–Ideal Double Gate SOI MOSFETs.......................................135 A. Kranti, G. A. Armstrong

SESSION 11 LATE NEWS SOI Gated Resistor: CMOS without Junctions..........................................................................................................137 J.P. Colinge, C.W. Lee, A. Afzalian, N. Dehdashti, R. Yan, I. Ferain, P. Razavi, B. O’Neill, A. Blake, M. White, A.M. Kelleher, B. McCarthy, R. Murphy

A-RAM: Novel Capacitor-Less DRAM Memory........................................................................................................139 N. Rodriguez, S. Cristoloveanu, F. Gamiz

First Demonstration of Heat Dissipation Improvement in CMOS Technology Using Silicon-OnDiamond (SOD) Substrates...........................................................................................................................................141 J.-P. Mazellier, J. Widiez, F. Andrieu, M. Lions, S. Saada, M. Hasegawa, K. Tsugawa, L. Brevard, J. Dechamp M. Rabarot, V. Delaye, S. Cristoloveanu, L. Clavelier, S. Deleonibus, P. Bergonzo, O. Faynot

Superior -Directed Mobility to -Directed Mobility in Ultrathin Body (110) nMOSFETs...........................................................................................................................................................143 K. Shimizu, T. Saraya, T. Hiramoto

SESSION 12 HOT TOPICS ARM 1176 Implementation in SOI 45nm Technology and Silicon Measurement..................................................145 R. Pottier, J. Tong, C. Hawkins, R. Kundu, J-L Pelloie

Electronic Design Automation (EDA) Flow for Development of an ARM Processor-Based Silicon-on-Insulator (SOI) SoC.....................................................................................................................................149 Kevin Kranen

Timing and Signal Integrity Analysis in a Cell Based SOI Design...........................................................................151 D. K. Griyage, S. Lokanandham, M. Jacobs

Author Index