Xilinx ISE Simulator Tutorial V 14.4
Modified by: Hoang Nguyen on June 11, 2015 Prepared by: Bayan Nimer on February 1, 2012 Instructor: Hakduran Koc
Xilinx ISE Simulation Tutorial
Contents 1. Introduction .......................................................................................................................................... 3 2. Basic Software Requirements ............................................................................................................. 4 3. ISE Project Navigator.......................................................................................................................... 5 4. Creating New Project........................................................................................................................... 6 5. Creating VHDL Source Files ............................................................................................................ 10 6. Editing VHDL Source Code .............................................................................................................. 14 7. Synthesizing VHDL Code .................................................................................................................. 15 8. Simulation of Design .......................................................................................................................... 17 9. Simulation Printouts .......................................................................................................................... 31 Appendix: Installing Xilinx WebPack .................................................................................................. 34
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Xilinx ISE Simulation Tutorial
1. Introduction Xilinx is a powerful software tool that is used to design, synthesize, simulate, test and verify digital circuit designs. The designer (you in this case) can describe the digital design by either using the schematic entry tool or a hardware description language. In this tutorial, we will create VHDL design input files – the hardware description of the logic circuit, compile VHDL source files, create a test bench and simulate the design to make sure of the correct operation of the design (functional simulation). The purpose of this tutorial is to give new users an exposure to the basic and necessary steps to implement and examine your own designs using ISE environment. In this tutorial, we will design one simple module (OR gate); however, in the future, you will be designing such modules and completing the overall circuit design from these existing files. A VHDL input file in the Xilinx environment consists of: Entity Declarations: module name and interface specifications (I/O) – list of input and output ports; their mode, which is direction of data flow; and data type. Architecture: defines a component’s logic operation. As you will learn (or have learned) in this course, there are different styles for the architecture body: o Behavioral – set of sequential assignment statements o Data Flow – set of concurrent assignments o Structural – set of interconnected components A combination of these could be used, but in this tutorial we will use Dataflow. In its simplest form, the architectural body will take the following format, regardless of the style: architecture architecture_name of entity_name is begin … -- statement end architecture_name;
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Xilinx ISE Simulation Tutorial
2. Basic Software Requirements • • •
After creating an account, install Xilinx software: ISE 14.7 from the website at http://www.xilinx.com/support/download/index.htm For a step by step process of downloading and installing Xilinx ISE WebPack (student version), go to the appendix at the end of tutorial. For extra help with the installation, go to: http://www.xilinx.com/support/documentation/dt_ise.htm
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Xilinx ISE Simulation Tutorial
3. ISE Project Navigator In this section, we introduce the reader to the main components of an “ISE Project Navigator” window, which allows us to manage our design files and move our design process from creation, to synthesis, to simulation phase. 1
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Figure 1: Xilinx Project Navigator window
1. Toolbar: provides fast access to frequently used menu commands. 2. Design Panel: consists of the following three areas A. View Pane – allows for only viewing source files that are associated with the selected design phase (e.g. testbench source files can only be viewed in “Implementation” view). B. Hierarchy Pane – allows for viewing source files that you created and added to your project. You can double click a source file to open for editing in the workspace. You can expand the level of hierarchy by clicking (+) icon or collapse by clicking (-) icon. C. Process Pane – determines and shows only the processes available to run for the selected source file. Similarly, they can be expanded and collapsed using (+) and (-) icons, respectively. 5
Xilinx ISE Simulation Tutorial 3. Transcript Window – displays output messages from processes you run. 4. Workspace – used to view and edit source files, multiple files can be opened simultaneously and the name of each file will be shown in a separate tab in the bottom of workspace window to enable you to switch between different files.
4. Creating New Project In this Project, we will be designing, synthesizing and simulating a 2-input “or gate”, where “a” and “b” are our inputs and “c” is our output. The truth table (as we all know) is given below (used to verify our design). a (1st Input) b (2nd Input) c (Output) 0 0 0 0 1 1 1 0 1 1 1 1 Table 1: Truth Table for an OR Gate •
In order to start ISE, double click the desktop icon: Or click: Start All Programs Xilinx Design Suite 14.4 ISE Design Tools 64-bit Project Navigator You will be presented with “Tip of The Day”, just click “OK”
Figure 2: Start of Xilinx Navigator
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Xilinx ISE Simulation Tutorial •
Create a new project by selecting: 1. File New Project, the following window will appear
Figure 3: Creating new project using “New Project Wizard”
2. In the “Name” field enter a short name for your project that correctly describes what you are designing (For now we will use “ORgate”). Also, make sure that your project name: o Starts with a letter o Contains only alphanumeric characters and underscores o Cannot contain two consecutive underscores. 3. Click the Browse icon (pointed by the arrow in the Figure above) in order to select the desired location to which you would like to save your project. 4. In the “Top-level source type” field, make sure that HDL is selected – this is selected if the top level design to be used is in VHDL or Verilog, which can include lower level modules such as HDL files, schematics or different types. 5. Click “Next” 7
Xilinx ISE Simulation Tutorial 6. In the “Project Settings” page shown below, ensure that the following options are set because they effect the types and processes that will be available for your design: o “Product Category” All o “Family” Spartan3E o “Device” XC3S500E o “Package” FT256 o “Speed” -5 o “Top-Level Source Type” HDL (automatically selected) o “Synthesis Tool” XST (VHDL/Verilog), which is a technology to synthesize VHDL, Verilog, or mixed language designs to create “Xilinxspecific netlist” files. o “Simulator” ISim (VHDL/Verilog), allows for running integrated simulation process as part of your ISE design flow. o “Preferred Language” VHDL
Figure 4: Changing properties of your project
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Xilinx ISE Simulation Tutorial 7. Leave the remaining fields as their default settings. 8. Click “Next” and you will be presented with a summary of your new project as shown in Figure 5.
Figure 5: Summary of your new project information
In order to open an existing project in Xilinx, select File Open Project to show the lists of projects available in a certain directory, choose the project you want and check “OK”
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Xilinx ISE Simulation Tutorial 9. Click “Finish” and you will exit the “New Project Wizard” and be taken back to the original “ISE Project Navigator” window, but a new project hierarchy is generated with the “ORgate” design file displayed in the “Hierarchy Pane” as shown in Figure 6.
Figure 6: “ISE Project Navigator” after creating a new project
5. Creating VHDL Source Files The “Create New Source Wizard” will enable you to create a VHDL source input file (.vhd) for a combinational logic design that will contain information about the design of the 2-input “or gate”…. (Any other text editor can be used to do so)
1. Click on the “New Source” icon , which is to the left of the “Hierarchy Pane.” This can also be done by right clicking on “ORgate” source file in the “Hierarchy Pane” and clicking “New Source,” as shown in Figure 7. This will take us to the “New Source Wizard” as shown Figure 8.
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Xilinx ISE Simulation Tutorial Create New Source
Add Source
Add Copy of Source
Figure 7: Creating a new source
Figure 8: “New Source Wizard”
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Xilinx ISE Simulation Tutorial 2. Select “VHDL Module” as a source file type to be added to the project since our files will contain VHDL design code, so our files will have “.vhd” extension. 3. In the “File name” field, enter a name of the entity for which you are creating input and output ports for. Remember to follow the conventions mentioned earlier (in Section 4, step 2) for naming the project. In this case, enter “ORgate”. 4. For the “Location” field, click the browse icon to navigate to the appropriate folder, which should be the same one used for creating the project. 5. Make sure that the “Add to project” checkbox is selected to automatically add this source to your project so that you don’t need to add it to the project again manually. 6. Click “Next”, the wizard will take you to the “Define Module” page as shown below, where I/O of the module (OR gate) will get defined. As you can see, the entity name is there, but can be changed if you want and the architecture name is “Behavioral” by default.
Figure 9: Define VHDL source window
7. “Direction” field is used to describe the mode, which is how data is transferred through the port. We are concerned with 3 modes: in – data flowing into the port; out – data flowing out of the port; inout – data flowing into and out of the port (bidirectional). Since we have 2 inputs and 1 output, in the first 3 fields under port name, we type “a”, “b” and “c” and set the “Direction” fields as “in” for the first two fields and “out” for the third field (c). 12
Xilinx ISE Simulation Tutorial 8. Click “Next” to view and verify the summary of the information about the new source created. If any changes are to be made, just click cancel.
Figure 10: New source information window
9. After making sure that the description of the module is correct, click “Finish.” The source file will be now displayed in “ISE Project Navigator” as shown below; the workspace window will be used as a text editor to make necessary changes to the source file. All the input and output ports that we specified will be displayed.
Figure 11: VHDL source code editor window in the Project Navigator
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Xilinx ISE Simulation Tutorial
6. Editing VHDL Source Code Now we have an “ORgate.vhd” file in the ISE text editor, where only entity declarations that we have created using the “New Source Wizard” are available (You can make changes to ports if needed). We can change the architecture name to “Dataflow” since that is the style we will be using. We are missing the architectural body. In the statement part, we will write one statement that describes how our or gate works, in the following manner: Target (output) Signal
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