COE758 ‐ Xilinx ISE 9.2 Tutorial 1 Creating Simple Project g p j
Start Xilinx ISE software, and press OK on “Tip of the Day” to get to a screen as shown above as shown above 2
Create new project by selecting File‐>New Project New window will open New window will open. 3
Project location – select the directory for the projects Project Name – select project name. Notice how directory with same Project Name select project name Notice how directory with same project name is added in the Project Location text field. Press Next>
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In the Device Properties selection of the device and package is done. In the Device Properties selection of the device and package is done. Family: Spartan3E Device: XC3S500E Package: FG320 S d 5 Speed: ‐5 Preferred Language: VHDL Keep the rest of the settings and press Next>
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In this window you can either add new source , or leave it for later as it is done in this tutorial done in this tutorial. Press Next> several times until finish and press Finish on the last window. 6
When new project is created source files can be added. Right click on the device and select New Source device and select New Source. New Wizard window is opened 7
Select VHDL Module and enter the name of the vhdl source file. Press Next> Press Next> 8
In this window input and output signals are specified. Notice that for led and switch signals Bus checkbox is selected and size of Notice that for led and switch signals Bus checkbox is selected and size of the bus is specified. Press Next>
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Last window in the wizard shows summary of the source including inputs and outputs for that module and outputs for that module. Press Finish to add source file to project. 10
When source file is added ISE tool window should look as above Next step is to add actual processing source code Next step is to add actual processing source code. 11
Sample VHDL program library IEEE; use IEEE.STD_LOGIC_1164.ALL; use IEEE.STD_LOGIC_ARITH.ALL; use IEEE.STD_LOGIC_UNSIGNED.ALL;
Library definitions
entity tutorial is Port ( clk : in STD_LOGIC; led : out STD_LOGIC_VECTOR (7 downto 0); switch : in STD_LOGIC_VECTOR (3 downto 0)); end tutorial;
Input/Output definitions
architecture Behavioral of tutorial is signal counter: std_logic_vector(29 downto 0);
counter definition
begin process(clk) begin if(clk'Event and clk='1') then if(switch(0)='1') then counter