VLF Test Frequency Source   

BAA RAG  VLF Frequency Source    Objective:  A simple source that can be used to set up VLF receivers on any one of the commonly used  frequencies:  • For use with type designs – a square wave is acceptable  • Pre‐set frequencies only  • +/‐ 100Hz accuracy  • Minimal component count  • Hand‐held    Principle of operation:  PIC serial data outputs (UART/EUART) are driven by a configurable Baud Rate Generator which is  configured independently of the PIC’s main oscillator source.  By continually feeding the value 0x55  into the serial output buffer we can generate a square wave at the TX pin.  Unlike toggling one of the  general purpose port pins, once we have loaded this byte we can leave the UART to get on with  generating the individual Marks and Spaces as a background task, leaving ample time to get ready to  load the next byte.     

Last  STOP  bit

START bit

1

0

1

0

1

0

0x55  (clocked out as LSB first)

1

0

STOP  bit

Next  START  bit

     

Frequency of square wave = ½ Baud rate (1Hz = ‘0’ followed by a ‘1’) 

  Because absolute accuracy is not an issue, we can use the internal chip oscillator function,  dispensing with the need for a crystal.    Limitations:  The frequency of the generated square wave is not continually variable but depends on the value  loaded into the Baud Rate Generator.  Many options are not precisely the same as the required  frequency, but are close enough to set up receivers prior to final fine tuning.  Using a higher  frequency oscillator setting on the PIC decreases the step size increasing the chances of an exact  match.  The prototype device uses an 8MHz oscillator but other PICs can provide a 32MHz internal  oscillator setting.          © Paul Hyde 2010   

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VLF Test Frequency Source         

   

 

 

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20

       

 

 

PIC 16F690

     

     

 

            The principle can be extended to cover more than four frequencies by adding 7‐segment displays to  indicate the frequency directly, and UP and DOWN buttons to cycle around them.    Paul Hyde  21st October 2010     

© Paul Hyde 2010   

 

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VLF Test Frequency Source    ;****************************************************************** ; ; Filename: VLF_Generator.asm ; Date: 12th June 2010 ; File Version: v1 ; ; Author: Paul Hyde ; Company: BAA RAG ; ******************************************************************* ; ; Files Required: P16F690.INC ;****************************************************************** ; ; Notes: ; The Hex byte 0x55 is repeatedly loaded into the UART TX buffer ; and clocked out, generating a stream of interleaved marks & ; spaces. ; ; One of 4 pre-defined values is loaded into the Baud Rate ; Generator to determine the tx data rate. A different LED is ; lit to indicate each frequency. ; ; A momentary-make pushbutton is used to cycle around the four ; different frequencies. ; ******************************************************************* list p=16f690 #include

; list directive to define processor

__CONFIG _CP_OFF & _CPD_OFF & _BOR_OFF & _PWRTE_ON & _WDT_OFF & _INTRC_OSC_NOCLKOUT & _MCLRE_OFF & _FCMEN_OFF & _IESO_OFF

; ***** FIXED DEFINITIONS #define BUTTON PORTA,3 ; Press button to cycle around four frequencies FREQ1 FREQ2 FREQ3 FREQ4

EQU EQU EQU EQU

.50 .47 .45 .42

; ; ; ;

19.6 20.9 22.1 23.4

kHz kHz kHz kHz

for for for for

8 8 8 8

MHz MHz MHz MHz

Fosc Fosc Fosc Fosc

; NB: Output frequency will be half the baud rate (1 Hz = 10) ;***** VARIABLE DEFINITIONS CBLOCK 0x020 FREQ_PARAM:4 LED_OUTPUT:4 PNTR INNER OUTER ENDC ORG goto

; ; ; ;

0x000 main

init ; ----- initialise system bsf STATUS,RP0 bcf STATUS,RP1 movlw 0x70 iorwf bsf clrf clrf

; ; ; ; ;

OSCCON OSCCON,SCS PIE1 PIE2

----- initialise I/O ports For PIC16F690 PORT A PORTB RA0 ICSPDATA RA1 ICSPCLK

© Paul Hyde 2010   

Four values to set Baud rate Four LED output patterns Pointer to current selected frequency Counters for debounce delay

; processor reset vector ; go to beginning of program

; Select Bank 1 ; Set up for 8MHz operation (already config for internal osc)

; Disable all interrupts

PORTC RC0 LED1 RC1 LED2

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VLF Test Frequency Source    ; ; ; ; ; ;

;

RA2 RA3 Vpp/BUTTON RA4 RA5

RB4 RB5 RB6 RB7 UART TX

bcf clrf bsf bsf clrf bsf bcf movlw movwf bcf

STATUS,RP0 PORTA BUTTON STATUS,RP1 ANSEL STATUS,RP0 STATUS,RP1 b'11111111' TRISA STATUS,RP0

clrf bsf movlw movwf

PORTB STATUS,RP0 b'11111111' TRISB

bcf clrf bsf movlw movwf

STATUS,RP0 PORTC STATUS,RP0 b'11110000' TRISC

; ----- clear flags and counters? bcf STATUS,RP0 clrf PNTR clrf INNER

; ----- Load fixed patterns movlw FREQ_PARAM movwf FSR movlw FREQ1 movwf INDF incf FSR movlw FREQ2 movwf INDF incf FSR movlw FREQ3 movwf INDF incf FSR movlw FREQ4 movwf INDF incf FSR movlw 0x01 movwf INDF incf FSR movlw 0x02 movwf INDF incf FSR movlw 0x04 movwf INDF incf FSR movlw 0x08 movwf INDF

RC2 LED3 RC3 LED4 RC4 RC5 RC6 RC7

; Select Bank 0 ; ; ; ;

Set BUTTON as high Select Bank 2 set for digital inputs Select Bank 1

; Set all pins as input ; Select Bank 0

; Select Bank 1 ; All inputs

; ; ; ;

Select Bank 0 Set LEDs to off Select Bank 1 Set LED pins as output

; Select Bank 0

; load the first address ; SPBRG value for 1st frequency

; SPBRG value for 2nd frequency

; SPBRG value for 3rd frequency

; SPBRG value for 4th frequency

; Port pattern for LED1

; Port pattern for LED2

; Port pattern for LED3

; Port pattern for LED4

; ----- initialise UART ; Configure UART generator to use formula RATE = Fosc/4(SPBRG+1) bsf STATUS,RP0 ; Select Bank 1 bsf BAUDCTL,BRG16 ; Select 16-bit generator mode bcf TXSTA,SYNC ; Set for asynch operation bsf TXSTA,BRGH ; Select High Speed operation bcf bsf movf

© Paul Hyde 2010   

STATUS,RP0 RCSTA,SPEN FREQ_PARAM,W

; Select Bank 0 ; Enable the serial port ; Set initial baud rate to FREQ1

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VLF Test Frequency Source    bsf movwf bsf

STATUS,RP0 SPBRG TXSTA,TXEN

; ----- initialise display bcf STATUS,RP0 movf LED_OUTPUT,W movwf PORTC retfie

; Select Bank 1 ; Enable transmission

; Select Bank 0 ; Load starting display ; Initialisation complete

main call

init

state_chk bcf bcf btfss goto movlw movwf bttn_chk btfsc goto

STATUS,RP1 STATUS,RP0 PIR1,TXIF bttn_chk 0x55 TXREG BUTTON state_chk

; Action a button press movlw .40 movwf OUTER dwn_dly call btfsc goto decfsz goto

short BUTTON state_chk OUTER dwn_dly

; Select Bank 0 ; Is the TX buffer empty? ; Fill it ; Has the button been pressed?

; Set up debounce (INNER = 256)

; 256*3*0.5us = 0.38ms approx ; Button bounced to 1 - start again

; Action command on button up, so repeat process up_chk btfss BUTTON ; Output stream could fail here, but no matter goto up_chk movlw movwf up_dly call btfss goto decfsz goto

.40 OUTER

; Reload counter

short BUTTON up_chk OUTER up_dly

; Button bounced to 0 - start again

incf

PNTR,F

; Increment pointer

movlw movwf movlw andwf addwf movf movwf

LED_OUTPUT FSR 0x03 PNTR,W FSR INDF,W PORTC

; Load new LED pattern

movlw movwf movlw andwf addwf movf

FREQ_PARAM FSR 0x03 PNTR,W FSR INDF,W

; Load new Frequency

bsf movwf

STATUS,RP0 SPBRG

; Bank 1

goto

state_chk

© Paul Hyde 2010   

; Keep PNTR within 0 to 3 ; Add the offset ; Get the new port pattern ; Switch LEDs

; Keep PNTR within 0 to 3 ; Add the offset ; Get the new SPBRG value

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VLF Test Frequency Source    ; ----- subroutines short decfsz goto btfss return movlw movwf return

END

INNER short PIR1,TXIF 0x55 TXREG

; Is the TX buffer empty? ; Fill it

; directive 'end of program'

  

© Paul Hyde 2010   

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