Verdi3 Automated Debug Platform ™

F UNCTIONAL CL O S U R E S O L U T I O N S

SpringSoft’s Verdi3™ software is an open platform for debugging digital designs with powerful technology that helps you: • Comprehend complex and unfamiliar design behavior • Automate difficult and tedious debug processes • Unify diverse and complicated design environments

Third Generation Debug Platform The Verdi3 generation platform builds on these core values with unprecedented personalization, customization and interoperability to maximize your debug productivity. You can speed debug of your large, complex designs, tailor the debug environment for the way you work, and directly integrate custom and third-party programs into your flows.

Faster, smaller and more efficient infrastructure:

Flexible graphical user interface for personalization:

• Multi-threaded database boosts performance by more than 45%

• Fast access to source files, videos and user-defined documents

• Compact format reduces file size by more than 30%

• Personalize window layout to fit your debug needs

• Parallel simulation dumping for 30% productivity gain

• Different working modes for different debug purposes • Centralized spotlight to search commands, preferences and documents

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Verdi3™ Automated Debug Platform F UNCTIONAL CL O S U R E S O L U T I O N S

Seamless VIA integration for customized flows:

Core Features

• Rich array of VIA programs to tailor Verdi3 deployment for user flows

The Verdi3 platform provides you with fundamental debug features:

• Customizable menu/toolbars enable VIA functions in Verdi3 user interface

• Full-featured Waveform Viewer to display and analyze activity over time

• Direct launch of VIA-enabled third-party tools/ scripts from debug environment

• High performance Fast Signal Database (FSDB) 5.0 format with multi-threaded technology for access to FSDB data two times faster than previous version • Powerful Waveform Comparison Engine to quickly isolate differences between FSDB files • Source Code Browser to easily traverse between source code and hierarchy • Flexible schematics and block diagrams that display logic and connectivity using familiar symbols • Intuitive bubble diagrams that reveal the operation of finite state machines

Advanced Features The Verdi3 platform also enables you to perform advanced debug operations:

Users can personalize the layout and debug modes  of Verdi3 environment.

Cut Debug Time in Half The Verdi3 debug platform lets you focus on tasks that add more value to your designs by cutting your debug time, typically by over 50%, with debug automation technology that: • Automates behavior tracing and analysis • Extracts, isolates, and displays pertinent logic in flexible design views • Reveals operation and interaction between design, power intent, assertions and testbench

Complete Debug Environment The Verdi3 Automated Debug Platform brings together all of the advanced technology and capabilities you need to debug with support for the broad range of languages and methodologies used to design and verify complex ICs and SoCs.

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• Automatic tracing of signal activity across many clock cycles with powerful behavior analysis engine • Temporal flow views provide a combined display of time and structure to help you rapidly understand cause-and-effect relationships • Transaction-based debug with flexible transaction and message support to design debug and analysis at higher levels of abstraction • Assertion-based debug with built-in support for assertions facilitates quick traversal from assertion failure to related design activity • SystemVerilog testbench debug with: > Specialized views of testbench code, including declaration-based hierarchy browsing and navigation, class inheritance and relationship comprehension, and tracing capabilities > Message logging capability, coupled with advanced visualization techniques, for complete picture of testbench activity and verification environment > Full-featured interactive simulation control to step through complex testbench code for more detailed analysis

Verdi3™ Automated Debug Platform F UNCTIONAL CL O S U R E S O L U T I O N S

Personalized Graphical User Interface

Broad Language and Methodology Support

The Verdi3 platform provides Qt-based GUI and flexible usage models with:

The Verdi3 platform enables debug of:

• Welcome Page for access to information and debug modes > Release notes, application notes and command reference documents > Pre-defined modes for different debug tasks, such as hardware debug, testbench debug, power-aware and property debug > Saved sessions with screenshots and text notes to restore/continue work

• Design components described in Verilog, VHDL, and SystemVerilog • Automated testbench environments using SystemVerilog Testbench (SVTB) • Assertions using SystemVerilog Assertions (SVA)

Open Architecture and Unified Methodology

> Major modules like nWave, nSchema and TFV can be configured as standalone window

The Verdi3 platform is designed so that you can take full advantage of your verification and debug methodology. The system is built on SpringSoft’s open Design Knowledge Architecture for compiling, extracting and preserving relevant information into databases that are optimized for efficient debug. It operates consistently across multiple domains — verification tools, design/verification languages, and abstractions — to unify your debug process, reduce learning curves and save time as you move to new design projects.

> One-click access to multiple source files within single window

Design Knowledge Architecture

> Training videos that demonstrate how to use key features > Customizable user links for sharing documents and web page • Window management system to personalize layout of debug environment > All components can be docked or undocked from major window

> Customizable toolbar, menu and hot keys for natural fit with debug tasks • Spotlight Search for fast, efficient navigation of commands, manuals and preference settings

• Knowledge Engine Compilers extract design knowledge contained in HDL code, testbenches, and assertions • Knowledge Database (KDB) stores crucial design knowledge to facilitate debug and understanding of your design • Fast Signal Database (FSDB) captures and stores results from simulators, emulators, and formal tools that produce time/value sequences • Application Programming Interfaces (APIs) provide open access to both databases and commandand-control mechanisms, enabling you to easily integrate the Verdi3 system with other verification tools and design environments

Verdi3 users can quickly access and traverse multiple source files in a single window. www.springsoft.com

Verdi3™ Automated Debug Platform F UNCTIONAL CL O S U R E S O L U T I O N S

Interoperability and Customization The open architecture and interoperability of the Verdi3 platform also enables you to leverage your investment with integration of other commercial and proprietary verification tools. Its continuously expanding ecosystem provides out-of-the-box support for a wide range of commonly used tools, including: • Simulators • Emulators and accelerators • Model checkers and other formal analysis engines You can further maximize the effectiveness of your Verdi3 deployment with custom automation programs that leverage the power of its underlying design knowledge infrastructure for data mining and manipulation applications. Seamless integration with SpringSoft’s VIA (Verdi Interoperability Apps) platform provides everything you need to quickly create and integrate Open Source scripts/utilities with the Verdi3 software that are designed to work reliably in your flow.

Debug and Analysis Across Multiple Abstraction Levels The Verdi3 platform allows you to seamlessly debug throughout your system-level to gate-level methodology flow. It provides additional support for verification and analysis at the implementation level with the Analyzer Design Implementation Analysis module, a single environment for analyzing troublesome design errors related to clocks, clock trees, and timing.

Debug and Analysis Across Multiple  Abstraction Levels

Debug of Power-Aware Design Intent The Verdi3 Power-Aware Debug Module accelerates comprehension of power intent and automates the process of visualizing, tracing, and analyzing the source of power-related errors. It simplifies the verification of low-power SoC designs with automation technologies that help you: • Visualize power intent with UPF/CPF • Comprehend impact of power intent on HDL design • Automate debug to determine whether unexpected design behavior is caused by functional logic or power-related errors

The Verdi3 Automated Debug Platform Saves You Time SpringSoft’s award-winning debug software cuts your debug time in half by automating the process of comprehending how complex designs work and enabling you to personalize and customize your debug environment. With over 400 customers and 60 EDA partners, it has become the industry’s de facto standard debug platform and the cornerstone of our family of functional closure products that make it easier to do more verification in less time.

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Verdi3™ Automated Debug Platform F UNCTIONAL CL O S U R E S O L U T I O N S

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