Three-phase soft-switched PWM inverter for motor drive application J. Shukla and B.G. Fernandes Abstract: A novel soft-switched inverter topology in which three mutually coupled inductors at a time are involved in the resonance process is proposed. By the introduction of magnetic coupling between three resonant inductors, the zero-voltage instants for the inverter can be generated by one auxiliary switch. Also, the resonant energy can be recycled, and the maximum voltage stress on the auxiliary circuit diode components is confined to the DC-link clamp voltage level. The DC link can be clamped to 1.1–1.3 times the DC-source value. This is unlike the soft-switched inverter in which two mutually coupled inductors are at a time are involved in a resonance process [14], wherein the clamping diode experiences voltage stress of the order of 11 per unit when clamping the DC-link voltage at 1.1 per unit. The proposed inverter also provides pulse-width modulated operation. An analysis of this novel quasi-resonant DC-link inverter topology is presented to reveal its softswitching characteristics. Simulation and laboratory experiments are performed to validate the analysis.
1
Introduction
Quasi-resonant inverters offer several advantages compared with resonant DC-link inverters [1–3] with regard to resonant link design and control, device rating requirements and use of pulse width modulation (PWM). Over the years, extensive research work has been carried out in the field of quasi-resonant DC-Link (QRDCL) PWM inverters [4–17]. The QRDCL inverter schemes generate zero-voltage (ZV) instants in the DC link at controllable instants that can be synchronised with any PWM transition command, thus ensuring a ZV switching condition of inverter devices. As a result, these inverters can be operated at high switching frequencies with high efficiency. Among the different types of QRDCL inverter scheme reported in the literature, the category of inverters in which an inductor is connected between the DC link and the DC source are particularly suited for high-frequency and highpower applications [10–17]. This is owing to the fact that these inverters do not have a high-frequency resonant switch in the main power path of the inverter. However, higher DC-link voltage stress [11], a high auxiliary switching device count [13] and the requirement of a separate lowvoltage DC source to clamp the DC link [15–17] are the main limitations of these schemes. One of the QRDCL inverter topology falling into this category is the passively clamped QRDCL (PCQRDCL) inverter reported in [14]. This topology (shown in Fig. 1a) can be considered to be a state-of-the-art QRDCL scheme satisfying most of the essential requirements, such as low clamp factor, simple resonance control, guaranteed zerolink voltage condition, PWM capability, use of only one auxiliary switch and recycling of resonant energy. It was shown that, by the introduction of magnetic coupling r The Institution of Engineering and Technology 2007 doi:10.1049/iet-epa:20050539 Paper first received 31st August 2005 and in final revised form 25th May 2006 The authors are with the Electrical Engineering Department, Indian Institute of Technology – Bombay, Powai, Mumbai-400076, India E-mail:
[email protected],
[email protected]
between two resonant inductors, the zero-voltage instants can be generated by only one auxiliary switch. Also, the DC link can be clamped at 1.1–1.3 per unit, and resonant energy can be recycled. The only drawback of this scheme was the high reverse voltage requirement of the clamp diode. The voltage-blocking capability of this diode is of the order of 11 per unit for a clamping factor of 1.1 per unit. This problem can be solved by use of a separate, low-voltage DC source. However, realisation of this low-voltage DC source is itself a problem. In the case of a battery-operated inverter, the clamp diode can be connected to a separate low-voltage battery group. In the absence of a battery source, the realisation, of a separate, low-voltage DC source becomes difficult. Another possible solution could be to use a DC–DC regulator or a simple R-C parallel circuit to maintain low voltage (refer to Fig. 1b). The use of a DC–DC regulator increases the component count and control complexity. Also, if the DC–DC regulator is not capable of feeding the processes resonant energy back to the DC source, then this energy is dissipated in resistor. This reduces overall efficiency of the inverter. An optimum strategy in which DC–DC regulator maintains a separate low voltage for clamping purposes and also feeds back the clamp energy to the DC source has yet not been reported in the literature. Hence, the objective of this paper is to design a QRDCL inverter circuit using one auxiliary switch, in which the maximum voltage stress in all semiconductor diodes is confined to the DC-link clamp voltage level ðVcÞ. Also, the resonant energy associated with the clamping action is recovered without the use of an extra switching circuit. Such a QRDCL inverter scheme is shown in Fig. 2, in which three mutually coupled inductors are used to achieve the above features. Only one auxiliary switch is used to generate zero-voltage instants for the inverter switching devices. 2
Principle of operation
Through the introduction of magnetic coupling between three resonant inductors (L1, L2 and L3), as shown in Fig. 2, the zero-voltage instants for the inverter can be
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93
i3 +
L1
i1
L2 +
D3
S
IO
L3
Sa
Sb
Sc
VC S’a
C
L2
+
+
S2
IO
L1 i2
Vs i3
D3 i1
i2
S’b
S2
S’c
Sa
Sb
Sc
S’b
S’c
+
Vs C
VC S’a
D2
D2
IM
IM a
Fig. 1
b
Inverters
a Passively clamped QRDCL inverter with mutually coupled inductors proposed in [14] b Quasi-resonant inverter using separate low-voltage DC source for clamping purpose [14]
Fig. 2 Proposed quasi-resonant DC-link inverter using three coupled inductors
D1
i1
VC
F
+
CF
L1 +
L2
i2
Vs CR S2
Fig. 3
+
VC
D R
D3
Io L3
i3
D2
Simplified equivalent circuit of proposed QRDCL inverter
generated by one auxiliary switch. Also, the current in the auxiliary inductor L2 can now reverse during the resonant cycle. Thus switch S2 can be turned off under the ZV condition. Clamping is provided by a large filter capacitor CF, which acts as a low-voltage DC source whose average current in steady state is zero. The entire resonant energy associated with the clamping circuit is recycled. This can be easily observed from the waveform of current iCF flowing through CF, as shown in Fig. 4. At steady state, the area enclosed by its discharging current (area A1) is equal to the area enclosed by its charging current (area A2). The voltage across CF ðvCF Þ attains a value equal to ðK 1ÞVs, where K is the clamping factor and lies in the range of 1.1–1.3. This DC voltage across CF is analogous to a separate lowvoltage DC source, as seen in a few QRDCL schemes reported in the literature [14–17]. Assuming that the inverter is feeding an inductive load (which can be represented by a constant current source), the steady-state DC voltage across 94
Fig. 4
Resonant link waveforms
CF depends on the values of L1, L2, L3 and CR and the coupling coefficients of mutually coupled inductors k12 , k23 and k13 . IET Electr. Power Appl., Vol. 1, No. 1, January 2007
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3
Analysis and modes of operation
Operation of the proposed QRDCL inverter can be explained by reference to Figs. 2–5. The various modes of circuit operation are described as follows.
as follows:
v CR ð t t 1 Þ ¼
Vs L1 þ L2 þ 2M12
½ðL2 þ M12 Þ þ ðL1 þ M12 Þ cos oðt t1 Þ ð3Þ
3.1 Mode 0 ðt0 t t1 Þ: pseudo steadystate mode (S2, D1, D2 and D3 off) During this mode, the inverter is said to be in pseudo steady-state mode. The resonant circuit formed by L1 and CR oscillates. The voltage vCR across capacitor CR alternates between Vc¼ KVs and ð2 KÞVs. Also, the inductor current i1 oscillates around the inverter input current (represented magnitude of this by a constant current source Io ), and the p ffiffiffiffiffiffiffiffiffiffiffi ripple is ðVs VcÞ=o1 L1 , where o1 ¼ 1= L1 CR . The DClink voltage vCR settles to Vs owing to the finite resistance of the resonant components. This mode of operation ends at time t1 , when S2 is turned on under the ZV condition to reduce the DC-link voltage vCR to zero. If we neglect the resistance of the circuit, the state equations of this mode are given by iL1 ðt t0 Þ ¼ ððVs VcÞ=R01 Þ sinðo1 ðt t0 ÞÞ þ Io ð1Þ vCR ðt t0 Þ ¼ Vs ðVs VcÞ cosðo1 ðt t0 ÞÞ ð2Þ pffiffiffiffiffiffiffiffiffiffiffiffiffi pffiffiffiffiffiffiffiffiffiffiffi where R01 ¼ L1 =CR and o1 ¼ 1= L1 CR . Initial conditions for this mode are vCR ðt0 Þ ¼ Vc and iL1 ðt0 Þ ¼ Io .
3.2 Mode 1 ðt1 t t2 Þ: link voltage reduces sinusoidally (S2 on; D1, D2 and D3 off) With S2 on, the resonance between L1, L2 and CR causes CR to discharge. Current flowing through L1 decreases sinusoidally, and that flowing through L2 increases sinusoidally. When voltage across CR ðvCR Þ becomes equal to the sum of vCF and the voltage induced in L3, D3 turns on, and this mode of operation ends. The equations for link voltage and currents during this mode can be derived
Fig. 5
i1 ðt t1 Þ ¼ Io þ
Vs oðL1 þ L2 þ 2M12 Þ
ðL1 þ M12 ÞðL2 þ M12 Þ sin o ð t t Þ oðt t1 Þ 1 2 L1 L2 M12 ð4Þ i 2 ðt t 1 Þ ¼
Vs oðL1 þ L2 þ 2M12 Þ " # ðL1 þ M12 Þ2 o ðt t 1 Þ þ sin oðt t1 Þ 2 L2 L2 M12
ð5Þ pffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffi 2 , ffiffiffiffiffiffiffiffiffiffiffiffiffi L12 ¼ ðL1 L2 M12 where, o ¼ 1= L12 CRp Þ=ðL1 þ L2 þ M12 Þ and M12 ¼ k12 L1 L2 . Initial conditions for this mode are vCR ðt1 Þ ¼ Vs, i1 ðt1 Þ ¼ Io , and i2 ðt1 Þ ¼ 0. The duration of this mode is given as 1 A cos1 ðt2 t1 Þ ¼ ð6Þ o B where A ¼ Vc þ
ððM23 þ M13 Þ ðL2 þ M12 ÞÞVs L1 þ L2 þ 2M12
2 VsðM23 ðL1 þ M12 Þ M13 ðL1 þ M12 ÞðL2 þ M12 Þ
B¼
2 ÞÞ ðL1 þ M12 ÞðL1 L2 M12 2Þ ðL1 þ L2 þ 2M12 ÞðL1 L2 M12
Equivalent circuits during various modes of operation
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3.3 Mode 2 ðt2 t t3 Þ: link voltage continues to decrease sinusoidally (S2 and D3 on; D1 and D2 off) A resonant circuit consisting of mutually coupled inductors L1, L2, L3 and CR is formed. Capacitor CR continues to discharge. This mode of operation ends when CR discharges to zero. The equations governing this mode are Z t di1 di2 di3 1 þ M12 M13 þ ði1 ðtÞ L1 dt dt dt CR 0 þi3 ðtÞ i2 ðtÞ Io Þdt ¼ Vs ð7Þ Z t di2 di1 di3 1 þ M21 M23 ði1 ðtÞ þ i3 ðtÞ L2 dt dt dt CR 0 i2 ðtÞ Io Þdt ¼ 0 ð8Þ Z t di3 di1 di2 1 M31 M32 þ L3 ði1 ðtÞ dt dt dt CR 0 þi3 ðtÞ i2 ðtÞ Io Þdt ¼ vCF ð9Þ pffiffiffiffiffiffiffiffiffiffiffiffiffi pffiffiffiffiffiffiffiffiffiffiffiffiffi where M13 ¼ k13 L1 L3 , M23 ¼ k23 L2 L3 , M12 ¼ M21 , M23 ¼ M32 , and M13 ¼ M31 . Initial conditions for this mode are i1 ¼ i1 ðt2 Þ, i2 ¼ i2 ðt2 Þ, i3 ¼ 0 and vCR ¼ vCR ðt2 Þ. It was found that this mode of operation occurs for a negligible small interval of time. From Fig. 4, it can be observed that the duration of this mode is very small compared with the time taken by the DC-link voltage to reduce to zero from source voltage value (which itself is small). Thus the change in currents i1 , i2 and i3 during this mode is negligibly small and can be neglected. Also, as the area enclosed by current iCF during this mode is negligible, the contribution of this mode towards steady-state DC-voltage build-up across CF is neglected. A situation in which three mutually coupled inductors are involved in a resonance process with CR occurs twice during the entire circuit operation. One such situation occurs during this mode, and another occurs during mode 4 of operation (discussed later). During mode 4 of operation, such a situation lasts for a longer duration and, hence, is not neglected.
3.4 Mode 3 ðt3 t t4 Þ: zero link voltage condition (S2 on and D2 off; inverter freewheeling diodes on; D3 on; D1 off) During this interval, the freewheeling diodes in the inverter legs represented by D start conducting. Link voltage is clamped at 0 V, and the inverter devices can be turned on/off under zero-voltage condition. A linearly increasing discharge current iCF flows out of the positive electrode of capacitor CF. Current flowing through L1 increases linearly, and that flowing through L2 decreases linearly. Owing to magnetic coupling between L1 and L2, current flowing through freewheeling diodes across the PWM inverter switches decreases linearly. This mode of operation ends when current flowing through the freewheeling diodes reduces to zero. The equation for link voltage and currents can be derived as v CR ð t t 3 Þ ¼ 0
ð10Þ
i1 ðt t3 Þ ¼ i1 ðt2 Þ 2 ðt t3 Þ ðL2 M13 M12 M23 ÞvCF þ L2 L3 M23 Vs þ D ð11Þ i 2 ðt t 3 Þ ¼ i 2 ðt 2 Þ þ
96
ðt t3 Þ½ðL1 M23 M12 M13 ÞvCF þðM13 M23 L3 M12 ÞVs D ð12Þ
i3 ðt t3 Þ ¼ i3 ðt2 Þ 2 ðt t3 Þ L1 L2 M12 vCF þ ðL2 M13 M12 M23 ÞVs þ D ð13Þ 2 2 where D ¼ L1 L2 L3 L3 M12 L2 M13 þ 2M12 M13 M23 2 L1 M23 . Initial conditions for this mode are i1 ¼ i1 ðt2 Þ, i2 ¼ i2 ðt2 Þ, i3 ðt2 Þ ¼ 0 and vCR ¼ 0. It should be noted that the initial conditions for currents ði1 ; i2 and i3 Þ are their respective values at the end of mode 1 (the effect of mode 2 is neglected), and that of vCR is zero. The duration of this mode is given as
TZero ¼ ðt4 t3 Þ ¼
ði2 ðt2 Þ þ Io i1 ðt2 Þ i3 ðt2 ÞÞ D ð14Þ vCF C þ Vs E
where C ¼ L2 M13 M12 M23 þ M13 M12 L1 M23 þ L1 L2 2 2 M12 , and E ¼ L2 L3 M23 þ L3 M12 M13 M23 þ L2 M13 M12 M23 . The expression for the area enclosed by current iCF ð¼ i3 Þ during this mode is given as 2 2 ðt4 t3Þ L1 L2 vCF M12 vCF þ L2 M13 Vs iCF ;area;M3 ¼
M12 M23 VsÞ 2D
ð15Þ
3.5 Mode 4 ðt4 t t5 Þ: capacitor CR charges: stage 1 (S2 on then off; D2 off then on; D3 on; D1 off) During this mode of operation, CR charges owing to the resonance caused between mutually coupled inductors L1, L2, L3 and CR . Capacitor CF continues to discharge. The state equations for this mode are the same as that of mode 2, except for the initial conditions. If circuit parameters and initial conditions are used, the analytical solution of the mathematical equations governing this mode becomes difficult to solve manually. However, if the numerical values of a few circuit parameters are known a priori, these equations can be solved with ease. Software packages such as Mathematica can be used as an aid to solve the equations. As an example, if numerical value of circuit parameters such as Vs ¼ 600, Io ¼ 50, L1 ¼ 281 mH, L2 ¼ 29 mH, L3 ¼ 43:8 mH, k12 ¼ 0:9, k13 ¼ 0:6, k23 ¼ 0:5, CR ¼ 22 nF are used, with symbolic notations for vCF , i1 ðt4 Þ, i2 ðt4 Þ, i3 ðt4 Þ, the state equations and the expression for area enclosed by iCF are given in Appendix 9. Note that, when the above equations are solved, the capacitor voltage vCF and initial conditions for currents at the start of this mode ði1 ðt4 Þ; i2 ðt4 Þ; i3 ðt4 ÞÞ are kept as symbolic notations. This helps to solve the circuit from the previous mode to the next mode of operation, and to prove the concept of steady-state DC-voltage build-up across CF, on which the entire circuit operation is based (discussed in the following Section). If (29) is plotted with respect to time, there will be two zero-crossings or solutions (see Fig. 4). This implies that i2 reverses its direction, making the antiparallel diode of switch S2 ðD2 Þ conduct for a short interval. When D2 is conducting, S2 is turned off under zero-voltage and zero-current switching conditions. This mode of operation ends when D2 turns off.
3.6 Mode 5 ðt5 t t6 Þ: capacitor CR charges: stage 2 (S2, D1 and D2 off; D3 on) During this mode of operation, a resonant circuit consisting of L1, L3 and CR is formed. Voltage across CR continues to increase. This mode ends when the sinusoidally decreasing discharge current iCF decreases to zero. At this instant, IET Electr. Power Appl., Vol. 1, No. 1, January 2007
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D3 turns off. The equations governing this mode are given as Z t di1 di3 1 M13 þ ði1 ðtÞ þ i3 ðtÞ Io Þdt ¼ Vs ð16Þ L1 dt dt CR 0 di3 di1 1 M13 þ L3 dt dt CR
Z
t
ði1 ðtÞ þ i3 ðtÞ Io Þdt ¼ vCF ð17Þ
0
The state equations during this mode are derived based on the same arguments made in the previous mode of operation. The initial conditions during this mode are: vCR ¼ vCR ðt5 Þ, i1 ¼ i1 ðt5 Þ, i2 ¼ i2 ðt5 Þ and i3 ¼ i3 ðt5 Þ. The state equations and the expression for area enclosed by iCF during this mode are given in Appendix 9.
3.8 Mode 7 ðt7 t t8 Þ: clamping action (S2, D2 and D3 off; D1 on) During this mode of operation, the DC-link voltage vCR is clamped at Vs þ vCF ð¼ KVsÞ. Current flowing through L1 ð¼ i1 Þ is fed to CF by diode D1. This current decreases linearly. This mode of operation ends when i1 becomes equal to inverter load current Io . After this mode of operation, the DC link returns to mode 0 of operation. The link current and voltage equations are iL1 ðt t7 Þ ¼
ðVs VcÞ ðt t7 Þ þ iL1 ðt7 Þ L1
vCR ðt t7 Þ ¼ Vs þ vCF
ð21Þ ð22Þ
The duration of this mode is given as
3.7 Mode 6 ðt6 t t7 Þ: capacitor CR charges: stage 3 (S2, D1, D2 and D3 off)
ðt8 t7 Þ ¼
During this mode of operation, a resonance circuit consisting of L1 and CR is formed. Voltage across CR continues to increase. Current flowing through L1 decreases sinusoidally. This mode ends when the voltage across CR reaches the clamp voltage level KVsð¼ Vs þ vCF Þ. The link current and voltage equations are
ðIo i1 ðt7 ÞÞL1 ðVs ðVs þ vCF ÞÞ
ð23Þ
The expression for the area enclosed by current iCF during this mode is given as iCF ;area;M7 ¼ 0:5ðt8 t7 Þði1 ðt7 Þ Io Þ 4
ð24Þ
Link design and control scheme
iL1 ðt t6 Þ ¼ Io þ ði1 ðt6 Þ Io Þ cosðo1 ðt t6 ÞÞ þ
Vs vCR ðt6 Þ sinðo1 ðt t6 ÞÞ R01
ð18Þ
vCR ðt t6 Þ ¼ ði1 ðt6 Þ Io ÞR01 sinðo1 ðt t6 ÞÞ ðVs vCR ðt6 ÞÞ cosðo1 ðt t6 ÞÞ þ Vs
ð19Þ
The duration of this mode is given as qffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffi1 0 2ab þ ð2abÞ2 4ðb2 c2 Þða2 c2 Þ 1 A ðt7 t6 Þ ¼ tan1 @ 2ðb2 c2 Þ o1 ð20Þ where a ¼ ðVs vCR ðt6 ÞÞ, b ¼ ði1 ðt6 Þ Io ÞR01 and c ¼ vCF .
Fig. 6
The design of QRDCL topology with three coupled inductors shown in Fig. 2 involves the selection of parameters L1, L2, L3, CR , M12 , M23 and M13 to the satisfy the desired link waveform specifications such as dv=dt, di=dt, value of K, peak currents in L1, L2, L3 and TZero . The design process for the proposed QRDCL circuit topology is iterative in nature, wherein a simulation study or calculations based on (1)–(24) are required to adjust the link parameters and to verify that the design specifications are met. The following design guidelines are recommended for the design of the topology. Initially, suitable values for L1 and CR are chosen. Inductance L1 consists of the sum of DC-source inductance and externally connected inductance between the DC source and the DC link. It prevents a significant rise in
Plot of vCF against iCF ;area;average , TZero and zero-voltage turn-off time available for S2
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97
source current above load current value Io when the DC-link voltage reduces below Vs. Hence, L1 in the range of 100–500 mH is selected. Capacitance CR consists of stray capacitance across the PWM inverter DC-busbar terminals and externally connected resonant capacitor. Generally, CR in the range of 10–100 mH is selected. Inductances L2 and L3 and coupling coefficients k12 , k23 and k13 are chosen in the following range: L2 ¼ 0:1 L1 , L3 ¼ 1:5 L2 , k12 ¼ maximum possible (usually k12 in the range of 0.85–0.95 can be obtained), k13 ¼ 0:6k12 and k23 ¼ minimum possible (usually k23 in the range of 0.4–0.5 can be obtained). Practical considerations limit the minimum value of k23 that can be obtained. Once all circuit parameter values are chosen based on the above-mentioned guidelines, the circuit equations for various modes of operation are executed to check whether essentially required specifications are met (such as the steady-state DC-voltage build-up across CF, which decides the clamping factor K of the inverter DC-link voltage). Capacitor CF is chosen such that constant voltage with negligible ripple is maintained across it. As the average value of the charging and discharging current flowing through CF is negligibly small (of the order of 0.25–0.5 A), an empirical value in the range
Fig. 7
of 500–5000 times the value of CR is sufficient to give satisfactory performance. Thus, under steady-state conditions, when steady DC voltage builds up across CF, the following condition must be satisfied: iCF ;area;average ¼ iCF ;area;M7 ðiCF ;area;M3 þ iCF ;area;M4 þ iCF ;area;M5 Þ ¼ 0
ð25Þ
where, iCF ;area;M7 is the area enclosed by iCF during mode 7. When the average area enclosed by the current through CF ð¼ iCF ;area;average Þ is calculated, a suitable value for vCF 0:1Vs is assumed, and (15), (32), (36), (24) and (25) are evaluated. This process is repeated by either the increasing (if iCF ;area;average 40) or decreasing (if iCF ;area:average o0) of the value of vCF until the value of iCF ;area;average becomes zero. The value of vCF at which iCF ;area:average becomes zero is the value of the steady-state voltage across CF . The proposed circuit with the parameters given in mode 4 is solved using MATLAB, and the plot of vCF against iCF ;area;average is shown in Fig. 6. It can be observed that the steady-state voltage attained across CF is 121 V. Figure 6 also shows the plot of the zero DC-link voltage period and zero-voltage turn-off period available for S2.
a
b
c
d
Simulation results
a M12 is increased from 81.5 mH to 85.5 mH in steps of 2 mH b M13 is increased from 66.56 mH to 74.56 mH in steps of 4 mH c M23 is increased from 17.81 mH to 21.81 mH in steps of 2 mH d CR is increased from 22 nF to 28 nF in steps of 3 nF 98
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For the same circuit, the effect of change in various circuit parameters (M12 , M13 , M23 , CR , L1, L2 and L3) was studied using a SABER simulator. The simulated waveforms for each individual parameter change are shown in Figs. 7 and 8, respectively. In this study, each circuit parameter was given an incremental change (while other parameters were kept constant), and the results were plotted. These results are enumerated in Table 1 and can help in fine-tuning the circuit parameters until the required specifications are met. For example, if the zero-voltage turnoff switching property for S2 is not satisfied during mode 4 of operation, then M12 should be given an incremental change until this property is satisfied. It is found that average current stress on additional switching devices such as S2, D1 and D3 are negligibly small. From the simulation study on the proposed circuit with the parameters given in mode 4, the average values of current flowing through S2, D1 and D3 are found to be 0.46 A, 0.3 A and 0.26 A, respectively, and their peak values of currents flowing are found to be 24 A, 2.5 A and 8 A, respectively (see Fig. 4). Thus S2, D1 and D3 are selected based on their
a
c
Fig. 8
Table 1: Effect of parameter variation on circuit performance Circuit parameter
Zero-voltage time period Tzero
Clamp voltage Available level ¼ ðVs þ vCF Þ zero-voltage turn-off period for S2
k12 m
decreases
negligible change
increases
k13 m
negligible change
decreases
increases
k23 m
negligible change
increases
negligible change
CR m
increases
decreases
decreases
L1 m
increases
decreases
decreases
L2 m
decreases
marginal increase
marginal increase
L3 m
negligible change
increases
negligible change
b
d
Simulation results
a L1 is increased from 281 mH to 321 mH in steps of 20 mH b L2 is increased from 29 mH to 49 mH in steps of 10 mH c L3 is increased from 43.8 mH to 73.8 mH in steps of 15 mH d During regeneration by taking Io ¼ 50 A IET Electr. Power Appl., Vol. 1, No. 1, January 2007
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99
peak current rating and the maximum voltage they need to block. The maximum voltage that S2 needs to block is during mode 7 of operation and is given as di1 Vmax;blocking;S2 ¼ Vs þ vCF M12 ð26Þ dt mode 7 The value of M12 ðdi1 =dtÞ during mode 7 of operation is negative and is of the order of 30–40 V for the circuit parameters given in mode 4. It can be easily verified from Fig. 4 that the value of ðdi1 =dtÞmode 7 357143 A s1 , which gives the product M12 ðdi1 =dtÞmode 7 ¼ 29 V ( for M12 ¼ 81:24 mH). Thus the maximum voltage stress on S2 is marginally higher than DC-link clamp voltage level VC ð¼ Vs þ vCF Þ. This increased voltage stress on S2 beyond
PWM Command Generator (Phase A)
Sa Q D To Phase A Flip Switches Flop Q CLK Sb
PWM Command Generator (Phase B)
Q D Flip Flop Q CLK
D
Sc D
Thus the maximum reverse voltage across D3 always remains marginally less than the DC-link clamp voltage level. It can be observed from Fig. 4 that the maximum reverse voltage across diode D1 occurs during mode 3 and is equal to the DC-link clamp voltage VC ð¼ Vs þ vCF Þ. The block diagram of the control circuit for soft-switched PWM inverter control is shown in Fig. 9. Depending upon the PWM inverter modulation strategy, the PWM command generator generates the switching signals for the inverter devices. The change in the conducting state of any inverter switch is first detected by the edge detector, which generates a turn-on signal to the auxiliary switch S2. This initiates the resonant cycle. The pulse width of the signal applied to the gate of S2 is equal to sum of the time required for the DC-link voltage to reach zero and TZero . To synchronise the change in the conducting state of the inverter devices with the zero link voltage instant, three
To Phase B Switches Sd
Se D D Q To Phase C Flip Switches Flop Q CLK Sf
PWM Command Generator (Phase C)
V
the DC-link clamp voltage level can be considered negligibly small. The maximum reverse voltage appearing across diode D3 also occurs during mode 7 of operation and is given as di1 Vmax;reverse;D3 ¼ Vs M13 ð27Þ dt mode 7
Link Detector
Edge Detector
Mono Shot
To Auxiliary Switch S2
Fig. 9 Control circuit for synchronising inverter switching with zero DC-link voltage instants
Fig. 10
Simulated plots of vCF and iCF during starting
Table 2: List of SABER templates used for simulating various circuit components and power dissipated in them for different values of inverter switching frequencies Circuit component
SABER template
Template properties/ comments
Power dissipated with SPWM, 5 kHz
Power dissipated with SPWM, 6 kHz
Power dissipated with SPWM, 7 kHz
L1 (281 mH, air core)
l
r ¼ 220 mO
9.1 W
9.81 W
10.9 W
L2 (29 mH, air core)
l
r ¼ 80 mO
0.52 W
1.86 W
1.91 W
L3 (43.8 mH, air core)
l
r ¼ 120 mO
0.18 W
0.45 W
0.55 W
Switch S2
irg4ph50u
Inbuilt Saber Template Analogy Inc.
4.5 W
9W
10.5 W
Diode D1
mur10150e
Inbuilt Saber Template Analogy Inc.
0.21 W
0.33 W
0.6 W
Diode D3
mur10150e
Inbuilt Saber Template Analogy Inc.
0.84 W
2.59 W
4W
Inverter switches
irg4ph40u
Inbuilt Saber Template Analogy Inc.
48 W
52 W
60 W
Free-wheeling diodes across inverter switches
dp
Inbuilt Saber Template Analogy inc.
5.2 W
5.7 W
6.2 W
68.55 W
81.74 W
94.66 W
Total
Load and source parameters are: RL ¼ 19.68 O, LL ¼ 63.94 O, Vs ¼ 600 V, Power factor ¼ 0.7, Output power ¼ 3.6 kW 100
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D-type flip-flops are used. The switching signals generated by the three-phase PWM command generator drive the D-input pins of the flip-flops, and the output pins ðQ and QÞ drive the corresponding top and bottom switches of the Table 3: Inverter efficiency for three different switching frequencies SPWM carrier frequency, kHz
Average switching frequency of S2, kHz
% efficiency
5
30
98.09
6
36
97.72
7
42
97.37
Fig. 11
Experimental results
a DC-link voltage vCR (top trace, 200 Vper division), S2 gate driver input signal (middle trace, 10 V per division) and current through L2 (bottom trace 16 A per division) Time: 5 ms per division b DC-link voltage (top trace 300 V per division), current through L2 (middle trace, 10 A per division), and current through L1 (bottom trace, 10 A per division) Time: 5 ms per division
PWM inverter. When the link voltage reaches zero, the zero-voltage detector outputs a signal that is used to clock the D-type flip-flops. Thus it synchronises the change in the conducting state of the inverter devices with the zero link voltage instants, so that the conducting state is changed only at zero-voltage condition. 5
Simulation results
A simulation study of the proposed circuit with parameters given in the mode 4 was performed to verify the analysis and to predict the performance under various load conditions. Simulation results for Io ¼ 50 A are shown in Fig. 4. It is observed that the fall time of the link voltage is about 533 ns. The zero link voltage condition, which is utilised for soft-switching of the inverter poles, is maintained
Fig. 12
Experimental results
a Current through L2 (top trace, 10 A per division), current through L1 (middle trace, 10 A per division) and current through CF (bottom trace, 10 A per division) Time: 5 ms per division b DC-link voltage (top trace, 300 V per division), current through L1 (middle trace, 5 A per division) and current through CF (bottom trace, 5 A per division) Time: 20 ms per division
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101
for about 686 ns. The rise time for the DC-link voltage to reach clamp voltage level after a brief zero-voltage period is 3.6 ms. The proposed circuit behaves identically when load regenerates (Io in Fig. 3 reversed in direction). A simulation study was carried out during regeneration with Io ¼ 50 A (see Fig. 8d). Figure 10 shows the waveforms of the current through CF and its voltage during starting. It can be observed that vCF settles at 100 V, giving a clamp factor of K ¼ 1.16. The on-time of S2 is 1.5 ms. So that the theoretical efficiency of the inverter at difference switching frequencies can be estimated, the proposed circuit was simulated using actual SABER templates for various components. The inverter was assumed to be feeding an RL load at power factor of 0.7,
Fig. 13
Table 4: List of motor parameters Motor parameter
Value
Rated voltage
400 V
Rated line-current
7.8 A
Stator connection type
Star connected 3F 4 pole
Frequency
50 Hz
Rs
1.1 O
Rr
0.9 O
Xsl
1.8 O
xrl
1.8 O
XM
68 O
Experimental results
a DC-link voltage vCR (top trace, 250 V per division), inverter line-to-line voltage (middle trace, 250 V per division) and current through L1 ði1 Þ (bottom trace, 8 A per division) Time: 20 ms per division b Waveforms at fundamental frequency of 50 Hz: DC-link voltage vCR (top trace, 500 V per division), inverter line-line voltage (middle trace, 500 V per division), and motor phase current (bottom trace, 16 A per division) c Waveforms at fundamental frequency of 60 Hz: inverter line–line voltage (top trace, 300 V per division) and motor phase current (bottom trace, 10 A per division) Time: 5 ms per division 102
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fundamental frequency of 50 Hz and modulation index of 1. The per-phase load parameters, DC-source value and SABER templates used for the simulation study are given in Table 2. As L1, L2 and L3 were chosen to be air core inductors, a linear inductor template with finite resistance was used for simulation. If actual SABER templates are used, the average power dissipated in each circuit component can be determined from the simulation results. These results are given in Table 2. Once the total power dissipation in the entire circuit has been found, the efficiency can be calculated. The efficiency of the inverter for three different switching frequencies is given in Table 3. It should be noted that the calculated efficiencies of the proposed soft-switched inverter, as listed in Table 3, are based on simulation results. 6
Experimental results
So that the simulated results could be validated, a laboratory prototype was built and tested under various load conditions. The circuit parameters used for the experimental study are given in the mode 4 description of circuit operation. Other circuit parameters are: Vs ¼ 300 V, CF ¼ 5 mF, and the on-time of S2 ¼ 2.5 ms. Figures 11a–12b show the recorded waveforms under no-load condition. Figure 11a shows vCR , the gate signal of S2, and the current through L2, and Fig. 11b shows vCR and currents through L2 and L1. The clamp factor K achieved was 1.3. Figure 12a shows the currents through L1, L2 and L3, respectively, and Fig. 12b shows vCR , L1 current and current through CF. It can be observed from Fig. 11a, that the fall time of the link voltage is approximately 800 ns. The zero link voltage condition, which is utilised for soft-switching of inverter poles, is maintained approximately for 700 ns. The DC-link voltage rises is three distinct steps to reach clamp voltage level after a brief zero-voltage period. The time taken for the DC-link voltage to reach clamp voltage level after a brief zero-voltage period is approximately 5.5 ms. It can be observed that there is fairly good match of simulated waveforms (Fig. 4) and those obtained from the prototype. In the experimental set-up there are stray inductances and capacitances that cause deviation from the simulation results. To demonstrate the PWM capability, a three-phase sine-triangle PWM command generator was implemented to control the six inverter switches. The output of the soft-switched inverter is directly connected to threephase induction motor whose parameters are given in Table 4. The sine-triangle PWM (SPWM) technique is used control the output voltage of the inverter. The frequency of the carrier wave is maintained at 6 kHz. The measured waveforms are shown in Figs. 13a–c. Figure 13a shows the link voltage vCR , inverter line–line voltage and current through L1. Figure 13a clearly shows that the change in line–line voltage is synchronised with the zero-voltage instants of the DC link. The load current is sinusoidal, and the performance of the link is found to be satisfactory. 7
Conclusions
In this paper, a new circuit topology for a QRDCL softswitching PWM inverter is proposed. It is a simple softswitching topology that is easy to implement and control. The proposed circuit uses one additional switch to create zero-voltage instants in the DC link. The maximum voltage stress on auxiliary circuit diodes is confined to the DC-link clamp voltage level. Also, the resonant energy associated
with clamping is recycled. The proposed inverter configuration is a solution to the problem of maintaining a separate low-voltage DC source using a low-power DC-toDC converter for clamping the DC link. It is shown that the extra resonant energy can be recycled, while the voltage stress on the clamping diode is maintained equal to the DClink clamp voltage level. The introduction of magnetic coupling between three resonant inductors can minimise the device count. Various modes of operation and link waveforms were analysed to reveal the soft-switching characteristics. Simulation and experimental studies were carried out to verify the proposed concept.
8
References
1 Divan, D.M.: ‘The resonant dc link inverter – a new concept in static power conversion’. IEEE-IAS Annual Conf. Rec., 1986, pp. 648–656 2 Divan, D.M., and Skibinski, G.: ‘Zero switching loss inverters for high power applications’. IEEE-IAS Annual Conf. Rec., 1987, pp. 627–634 3 Merterns, A., and Divan, D.M.: ‘A high frequency resonant dc link inverter using IGBTs’. IPEC Tokyo, Japan, 1990, pp. 152–160 4 He, J., and Mohan, N.: ‘Parallel resonant dc link circuit – a novel zero switching loss topology with minimum voltage stresses’, IEEE Trans. Power Electron., 1991, 6, pp. 687–694 5 He, J., Mohan, N., and Wold, B.: ‘Zero voltage switching PWM inverter for high frequency DC-AC power conversion’, IEEE Trans. Ind. Appl.., 1993, 29, pp. 959–968 6 Jung, and Cho, G.: ‘Novel type soft switching PWM converter using a new parallel resonant DC link’. IEEE-IAS Conf., 1991, pp. 241–247 7 Malesani, L., Tenti, P., Tomasin, P., and Toigo, V.: ‘High efficiency quasiresonant dc link three-phase power inverter for full-range PWM’, IEEE Trans. Ind. Appl., 1995, 31, pp. 141–148 8 Choi, J.W., and Sul, S.K.: ‘Resonant link bidirectional power conversion – Part-I: Resonant circuit’, IEEE Trans. Power Electron., 1995, 10, pp. 479–484 9 Wang, K., Jiang, Y., Dudovsky, S., Hau, G., Boroyevich, D., and Lee, F.C.: ‘Novel dc-rail soft switching three-phase voltage source inverter’, IEEE Trans Ind. Appl., 1997, 23, pp. 509–516 10 Divan, D.M., Malesani, L., Tenti, P., and Toigo, V.: ‘Asynchronised resonant dc link converter for soft switched PWM’, IEEE Trans. Ind. Appl., 1993, 29, pp. 940–948 11 Lai, J.S., and Bose, B.K.: ‘High frequency quasi-resonant DC voltage notching inverter for AC motor drives’. Proc. IEEE Conf., 1990, pp. 1202–1207 12 Vassilios, G., and Ziogas, P.D.: ‘An optimum modulation strategy for a novel notch commutated three phase PWM inverter’, IEEE Trans. Ind. Appl., 1994, 30, pp. 52–61 13 Hui, S.Y.R., Gogani, S., and Zhang, J.: ‘Analysis of a quasi-resonant circuit for soft-switched inverters’, IEEE Trans. Power Electron., 1996, 11, pp. 106–114 14 Chen, S., and Lipo, T.A.: ‘A novel soft switched PWM inverter for AC motor drives’, IEEE Trans. Power Electron., 1996, 11, pp. 653–659 15 Jafar, J.J., and Fernandes, B.G.: ‘A new quasi-resonant DC-link PWM inverter using single switch for soft switching’, IEEE Trans. Power Electron., 2002, 17, p. 1010 16 Jafar, J.J., and Fernandes, B.G.: ‘A quasi-resonant DC-link PWM inverter for induction motor drive’. In IEEE-IAS Annual Conf. Rec., 1999, pp. 1997–2002 17 Jafar, J.J., and Fernandes, B.G.: ‘A novel quasi-resonant DC-link PWM inverter for induction motor drive’. In IEEE-PESC Conf. Rec., 1999, pp. 482–487
9 Appendix
9.1 State equations during mode 4 of circuit operations i1 ðt t4 Þ ¼ 23:2556 þ 0:534888i1 ðt4 Þ þ 0:465112i2 ðt4 Þ þ 1:08022i3 ðt4 Þ þ 0:0078125ðt t4 Þ2 þ cos½373683ðt t4 Þð11:363 þ 0:22726i1 ðt4 Þ 0:22726i2 ðt4 Þ 1:21087i3 ðt4 ÞÞ þ cos½3:72354 106 ðt t4 Þð11:8926þ0:237852i1 ðt4 Þ 0:237852i2 ðt4 Þ þ 0:130654ðt4 ÞÞ þ sin½373683ðt t4 Þ ð3:54682 0:106768 vCF Þ þ sin½3:72354 106 ðt t4 Þ ð2:63439 þ 0:00224885 vCF Þ þ 41561:1ðt t4 Þ vCF ð28Þ
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103
i2 ðt t4 Þ ¼ 26:7444 þ 0:534888i1 ðt4 Þ þ 0:465112i2 ðt4 Þ þ 1:08022i3 ðt4 Þ þ cos½373683ðt t4 Þð6:68997 þ 0:133799i1 ðt4 Þ 0:133799i2 ðt4 Þ 0:712902i3 ðt4 ÞÞ
9.2 State equations during mode 5 of circuit operations i1 ðt t5 Þ ¼ 12:0485 þ 0:759029i1 ðt5 Þ 0:240971i3 ðt5 Þ
þ cos½3:72354 106 ðt t4 Þð33:4344 0:668688i1 ðt4 Þ
þ 1:31032 106 ðt t5 Þ 0:045118 vCR ðt t5 Þ
þ 0:668688i2 ðt4 Þ 0:367315i3 ðt4 ÞÞ þ sin½373683ðt t4 Þ
0:000976563ðt t5 Þ2 2183:84ðt t5 Þ vCF
ð2:088190:0628597 vCF Þ þ sin½3:72354 106 ðt t4 Þ ð7:406220:00632232 vCF Þ þ 41561:1ðt t4 Þ vCF
þ cos½1:62534 106 ðt t5 Þð0:240971i1 ðt5 Þ
ð29Þ i3 ðt t4 Þ ¼ cos½373683ðt t4 Þð8:50709 0:170142i1 ðt4 Þ
þ 0:240971i3 ðt5 Þ 12:0485Þ þ sin½1:62534 106 ðt t5 Þð1:24596 0:00861631 vCR ðt5 Þ þ 0:0065397 vCF Þ
ð33Þ
þ 0:170142i2 ðt4 Þ þ 0:90654i3 ðt4 ÞÞ þ cos½3:72354 106 ðt t4 Þð8:50709 þ 0:170142i1 ðt4 Þ 0:170142i2 ðt4 Þ
i3 ðt t5 Þ ¼ 37:9515 0:759029i1 ðt5 Þ þ 0:240971i3 ðt5 Þ
þ 0:0934603i3 ðt4 ÞÞ þ sin½373683ðt t4 Þð2:65539
1:31032 106 ðt t5 Þ þ 0:045118 vCR ðt t5 Þ
6
þ 0:0799336 vCF Þ þ sin½3:72354 10 ðt t4 Þ ð1:88445 þ 0:00160866 vCF Þ
ð30Þ
þ 0:000976563ðt t5 Þ2 þ 2183:84ðt t5 Þ vCF þ cos½1:62354 106 ðt t5 Þð0:759029i1 ðt5 Þ
vCR ðt t4 Þ ¼ 45:4545 106 ð6:96892 109
þ 0:759029i3 ðt5 Þ 37:9515Þ þ sin½1:62534
ð459:557 13:8338 vCF Þ 2:09814 109
106 ðt t5 Þ ð3:92462 0:0271404 vCR ðt5 Þ þ 0:0205993 vCF Þ
ð1526:41 þ 1:30302 vCF ÞÞ þ 45:4545 106
ð34Þ
ð2:09814 109 ð6890:76 137:815ði1 ðt4 Þ i2 ðt4 ÞÞ 75:703i3 ðt4 ÞÞ sin½3:72354 106 ðt t4 Þ
vCR ðt t5 Þ ¼ vCR ðt5 Þ þ 0:0136554ð10589:3
2:09814 109 cos½3:72354 106 ðt t4 Þ
73:2297 vCR ðt5 Þ þ 55:5806 vCF Þ þ 45:4545
ð1526:41 þ 1:30302 vCF Þ þ 6:96892 109
106 ð0:00016276ðt t5 Þð4:36557 1011
7
ð2:54897 10 i1 ðt4 Þðt t4 Þ þ 4:77932 108 i2 ðt4 Þðt t4 Þ þ 373683ðt t4 Þ
þ ðt t5 Þ2 Þ 3:00418 1010 ð102400 2048i1 ðt5 Þ
3
þ 459:557 cos½373683ðt t4 Þ þ 1472:29 sin½373683ðt t4 Þ 29:4457i1 ðt4 Þ sin½373683ðt t4 Þ þ 29:4457i2 ðt4 Þ sin½373683ðt t4 Þ þ 156:891i3 ðt4 Þ sin½373683ðtt4 Þ13:8338 cos½373683ðtt4 ÞvCF ÞÞ ð31Þ The expression for the area enclosed by current iCF ð¼ i3 Þ during mode 4 is given as
2048i3 ðt5 ÞÞ sin½1:62543 106 ðt t5 Þ 3:00418 1010 cos½1:62534 106 ðt t5 Þ ð10589:3 73:2297 vCR ðt5 Þ þ 55:5806 vCF ÞÞ
ð35Þ
The expression for the area enclosed by current iCF ð¼ i3 Þ during mode 4 is given as
iCF ;area;M4 ¼ 4:56936 108 ð50 i1 ðt4 Þ þ i2 ðt4 Þ
iCF ;area;M5 ¼ 3:00418 1010 ð77724:6 1554:49i1 ðt5 Þ
0:549308i3 ðt4 ÞÞ sin½3:72354 106 ðt t4 Þ
1554:49i3 ðt5 ÞÞ sin½1:62534 106 ðt t5 Þ þ 3:00418
4:55311 107 ð15:6069 0:469806 vCF Þ
1010 ð8037:62 55:5834 vCR ðt5 Þ þ 42:1837 vCF Þ
þ 4:56936 108 ð11:0758 þ 0:00945482 vCF Þ
ð1 cos½1:62534 106 ðt t5 ÞÞ
ð1 cos½3:72354 106 ðt t4 ÞÞ þ 4:55311 107
þ 0:0000813802ðt t5 Þð466347 9326:95i1 ðt5 Þ þ 2961:05i3 ðt5 Þ 8:05061 109 ðt t5 Þ
ðcos½373683ðt t4 Þð15:6069 0:469806 vCF Þ þ sin½373683ðt t4 Þð50 i1 ðt4 Þ þ i2 ðt4 Þ þ 5:32814i3 ðt4 ÞÞÞ
104
þ 277:205 vCR ðt t5 Þ þ 2ðt t5 Þ2 þ 1:34175 ð32Þ
107 ðt t5 Þ vCF Þ
ð36Þ
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