The Technology behind PlayStation®2 Paul Holman
Sony Computer Entertainment Europe VP of Technology
In this presentation ¾ Sony Computer Entertainment Overview ¾ Technical aspects of PlayStation 2 ¾ The Future for PlayStation ….
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Who Am I ? SCEI R&D Group HQ (Japan)
SCEI R&D (Japan) Architecture OS and Library Dev. Support (Japan)
SCEA Business & Technology
SCEE Technology Group (UK)
SCEA R&D (USA)
Tech. Information
Technology Development
Dev. Environment
Network Development
Network Technology
Computer Graphics
Dev. Support (USA)
Dev. Support (UK)
Man Machine I/F Simulation
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SCEI BB Business Div.
Strategy Planning Network Business System Dev.
Sony Computer Entertainment “Europe”
Launch - Apr 96 Technology Group
May 96 - Apr 97
May 97 - Apr 98 4
May 98-Apr 99
May 99- Jan 02
PlayStation 2
European Launched 24 November 2000
Where are we now ? September 2002 – 40 million PS2s shipped worldwide (12+ million to SCEE region) BUT … sales are seasonal – vast majority in Christmas season Sales are running at 2.4x original PlayStation at the same point of lifecycle
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Manufacturing Technology
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A peek inside the factory ….
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EE (Main Processor) – Joint Fab with Toshiba in Ohita (0.18µ)
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SCE Nagasaki - 0.18µ process for GS (Graphics Chip)
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And what about the software ?
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Disc manufacturing (CD and DVD) ¾ All Disc manufacturing carried out by Sony DADC in Salzburg, Austria ¾ Includes proprietary copy control solutions ¾ PS2 discs are serialized ¾ “Just-in-time” ordering
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The Technology inside the machine …
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Technical Aspects of PlayStation 2 ¾ The PlayStation 2 Development Environment ¾ System Architecture ¾ The Emotion Engine (EE) ¾ The Graphics Synthesiser (GS) ¾ The IO Processor (IOP)
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Professional Development Environment The TOOL
TV TV Controllers Controllers Linux Linux Box Box
¾ Use the Linux-based tools that come with the TOOL ¾ With a Linux box you can either: ¾ develop and compile on the Linux Box ¾ use the Linux Box purely for compilation and develop in your favourite Windows Editor
LAN LAN PC PC
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Developing at home – PS2 Linux ¾ PlayStation 2 branded USB keyboard & mouse ¾ 10/100 Ethernet Adapter ¾ 40GB Hard Disk ¾ Monitor cable ¾ 2 x install DVD’s ¾ Linux ¾ Hardware Manuals ¾ Tools, Examples
¾ Simple EULA ¾ Launched: 22 May ’02 ¾ € 249 (excl. VAT and Shipping) from http://www.linuxplay.com/ Technology Group
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Here comes the science bit ...
System Architecture
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PlayStation2 ¾ 128-bit CPU core “Emotion Engine” ¾ GS “Graphics Synthesizer” ¾ SPU2 “Dynamic Sound Processor” ¾ I/O Processor (USB, i.Link) ¾ DVD/CD ROM disc system
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The Emotion Engine - Specs ¾ CPU Core ¾ System Clock ¾ Bus Bandwidth ¾ Main Memory ¾ Floating Point Calculation ¾ 3D Geometry Performance ¾ Image Processor Unit
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128 bit CPU 300MHz 3.2GB/sec 32MB (Direct Rambus) 6.2 GFLOPS 66 Million polygons/sec MPEG2
Floating Point Vector Performance … 160
M vector/sec
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Geometry & Perspective Transformation
1/Distance
120
Distance
100
Geometry Transformation
80 60 40 20 0
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P2 (400 Mhz)
P3 (500 Mhz)
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EE (300 Mhz)
Pixel Fill Rate
GS
2.4
0.9
Infinite Reality 2
36x
0.37
Voodoo 3 (3500) Riva TNT
0.25
Octane
0.24 0.2
Power VR2
0.07
PlayStation 0
0.5
1
1.5
G pix/sec Technology Group
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2
2.5
System Architecture RAM RAM
Emotion Emotion Engine Engine (EE) (EE)
Graphic Graphic Synthesiser Synthesiser (GS) (GS)
RAM RAM
I/O I/O Processor Processor (IOP) (IOP)
Sound Sound Processor Processor (SPU2) (SPU2)
EXTERNAL DEVICES
ROM ROM Technology Group
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CD/DVD CD/DVD
VIDEO OUT
AUDIO OUT
Emotion Engine architecture Overview
FPU FPU COP1 COP1
CPU CPU Core Core
INTC INTC
VU0 VU0
VU1 VU1
COP2 COP2
EFU
GIF GIF
128bit Main Bus
Timer Timer
DMAC DMAC
IPU IPU
DRAMC DRAMC
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SIF SIF
IOP
GS
Emotion Engine architecture CPU Core ¾ ¾ 128 128bit bitCPU CPU VU1 VU0 ¾ 300 MHz clock VU1frequency COP1 VU0 ¾ 300 MHz clock frequency COP1 CPU GS CPU GIF GIF ¾ 32 memory Core ¾COP2 32Mb Mbmain main memory Core EFU COP2 ¾ ¾ MIPS MIPSIII IIIwith withsome someMIPS MIPSIV IVand and INTC INTC multimedia multimediaextensions extensions 128bit ¾ -wayMain ¾ 64 64bit bitinstructions, instructions,22-way Bus superscalar superscalar Timer IPU DRAMC SIF Timer DMAC DMAC¾ IPUbit DRAMC instructions SIF ¾ 128 128 bitmultimedia multimedia instructions FPU FPU
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IOP
Emotion Engine architecture CPU Core
FPU FPU COP1 COP1
INTC INTC
CPU CPU Core Core
¾ -Cache ¾ 16Kb 16KbII-Cache VU1 VU0 ¾ 8Kb -Cache VU1 VU0 ¾ 8KbDD-Cache ¾ 16Kb ¾COP2 16Kbscratchpad scratchpad EFU COP2
GIF GIF
128bit Main Bus
Timer Timer
DMAC DMAC
IPU IPU
DRAMC DRAMC
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SIF SIF
IOP
GS
Emotion Engine architecture Floating Point Unit (FPU)
FPU FPU COP1 COP1
CPU CPU Core Core
INTC INTC
VU0 VU0
VU1 VU1
COP2 COP2
EFU
GIF GIF
128bit Main Bus
COP1 COP1for forthe theCPU CPU Timer Timer
DMAC DMAC
IPU IPU
DRAMC DRAMC
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SIF SIF
IOP
GS
Emotion Engine architecture Timer
FPU FPU COP1 COP1
INTC INTC
CPU CPU Core Core
VU0 VU0
VU1 VU1
EFU ¾ ¾ 44independent independenttimers timers ¾ ¾ Driven Driveneither either
GIF GIF
COP2 COP2
128bit Main ¾¾ by the bus clock (1/16 or 1/256 Bus by the bus clock (1/16 or 1/256
Timer Timer
DMAC DMAC
intervals) intervals) ¾ external HH-BLNK -BLNK IPU DRAMC ¾ external IPU DRAMC
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SIF SIF
IOP
GS
Emotion Engine architecture DMA Controller (DMAC)
FPU FPU¾ Vital to maximising the EE’s VU1 VU0 VU1performance to maximising the EE’s performance COP1 VU0 COP1 ¾ Vital CPU CPU GIF GIF ¾ Handles data transfers between main ¾ Handles data transfers between main Core Core COP2 EFU memory each memoryand andCOP2 eachprocessor/scratchpad processor/scratchpad INTC INTC 128bit Main Bus
Timer Timer
DMAC DMAC
IPU IPU
DRAMC DRAMC
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SIF SIF
IOP
GS
Emotion Engine architecture Vector Units (VU0 & VU1)
FPU FPU COP1 COP1
INTC INTC
CPU CPU Core Core
VU0 VU0
VU1 VU1
COP2 COP2
EFU
GIF GIF
¾ ¾ Used Usedfor formathematical mathematicaloperations operations ¾ ¾ FMACs FMACsfor foraddition additionand andmultiplication multiplication Timer DMAC IPU DRAMC SIF ¾ for and operations Timer DMAC IPU root DRAMC SIF ¾ FDIV FDIV fordivision division andsquare square root operations ¾ -in memory ¾ Built Built-in memoryfor formicroprograms microprograms ¾ ¾ VIFs VIFslink linkthe theVUs VUs to to the the rest rest of ofthe thesystem system DRAM Technology Group
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IOP
128bit Main Bus
GS
Emotion Engine architecture Vector Unit 0 (VU0)
FPU FPU COP1 COP1
INTC INTC
CPU CPU Core Core
VU0 VU0
VU1 VU1
COP2 COP2
EFU
GIF GIF
128bit Main Bus
¾ , 11FDIV ¾ 44FMACs FMACs, FDIV ¾ ¾ COP2 COP2for forthe theCPU, CPU,executing executingmacroinstructions macroinstructions Timer DMAC IPU DRAMC SIF ¾ VUMem (data), (instructions) Timer DMAC IPUMicroMem DRAMC SIF ¾ 44Kb Kb VUMem (data),44Kb Kb MicroMem (instructions) ¾ ¾ Useful Usefulfor forcomplex complexoperations operationslike likephysics physicsetc. etc. DRAM Technology Group
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IOP
GS
Emotion Engine architecture Vector Unit 1 (VU1)
FPU FPU COP1 COP1
INTC INTC
CPU CPU Core Core
VU0 VU0
VU1 VU1
COP2 COP2
EFU
GIF GIF
128bit Main Bus
¾ ¾ No Nodirect directpath pathto toCPU CPUcore, core,but butdirect directpath pathto toGIF GIF ¾ ¾ 16 16Kb KbVUMem VUMem(data), (data),16 16Kb KbMicroMem MicroMem(instructions) (instructions) Timer DMAC ¾ for Timer DMAC IPU IPU DRAMC DRAMC SIF SIF ¾ Useful Useful fortransformations transformations
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IOP
GS
Emotion Engine architecture Image Processing Unit (IPU) ¾ ¾ Image Imagedata datadecompression decompressionprocessor processor FPU FPU ¾ Decodes MPEG2 streams ¾ Decodes MPEG2VU0 streams VU1 VU1 COP1 VU0 COP1 CPU CPU ¾ MacroBlock Decode ¾ MacroBlock Core Core Decode COP2 EFU COP2 ¾ Vector Quantization ¾ Vector Quantization INTC INTC ¾ ¾ Transparency TransparencyControl Control
Timer Timer
DMAC DMAC
IPU IPU
DRAMC DRAMC
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GIF GIF
128bit Main Bus
SIF SIF
IOP
GS
System Architecture RAM RAM
Emotion Emotion Engine Engine (EE) (EE)
Graphic Graphic Synthesiser Synthesiser (GS) (GS)
RAM RAM
I/O I/O Processor Processor (IOP) (IOP)
Sound Sound Processor Processor (SPU2) (SPU2)
EXTERNAL DEVICES
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CD/DVD CD/DVD
VIDEO OUT
AUDIO OUT
GS specifications ¾ Clock Frequency ¾ Embedded DRAM ¾ Total memory bandwidth ¾ Pixel fill rate
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150 Mhz 4MB 1.2Gb/sec 2.4GPixel/sec
System Architecture RAM RAM
Emotion Emotion Engine Engine (EE) (EE)
Graphic Graphic Synthesiser Synthesiser (GS) (GS)
RAM RAM
I/O I/O Processor Processor (IOP) (IOP)
Sound Sound Processor Processor (SPU2) (SPU2)
EXTERNAL DEVICES
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Disc CD/DVD Drive Disc CD/DVD Drive
VIDEO OUT
AUDIO OUT
IOP ¾ Contains an R3000 (PlayStation CPU+) ¾ 2 clock frequencies ¾ 2 Mb IOP memory ¾ Interfaces to the EE for ¾ controllers ¾ memory devices ¾ SPU 2 ¾ CD/DVD unit ¾ USB/IEEE1394 Technology Group
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System Architecture RAM RAM
Emotion Emotion Engine Engine (EE) (EE)
Graphic Graphic Synthesiser Synthesiser (GS) (GS)
RAM RAM
I/O I/O Processor Processor (IOP) (IOP)
Sound Sound Processor Processor (SPU2) (SPU2)
EXTERNAL DEVICES
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CD/DVD CD/DVD
VIDEO OUT
AUDIO OUT
SPU 2 ¾ 2 DSP cores, 48 Channels ¾ 2Mb sound memory ¾ Output to DAC or Optical digital output
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Standard Peripherals ¾ PS one peripherals compatible (most) ¾ “DualShock2” as standard controller ¾ Large capacity “memory card” (8Mb) ¾ USB and i.Link (aka IEEE 1394) devices (non proprietary interfaces) ¾ “broadband unit” (40GB HDD and network adaptor)
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USB Applications ¾ Digital Camera (e.g. via “Picture Paradise” software or “eyetoy” game ) ¾ Microphone (e.g. speech recognition and communication software in “SOCOM: US Navy Seals”) ¾ Scanner, Printer (Japan titles) ¾ Keyboards, Mouse (Yabasic, PS2 Linux)
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And what happens next …
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Products based upon the “Cell Processor” ¾ A chip triumvirate of IBM, Sony and Toshiba has pledged $400 million to the project and sent engineers to a joint development centre in Austin, Texas ¾ “We are working for the third-generation (PlayStation) with this very aggressive and crazy goal… Moore's Law is too slow for us." Shin’ichi Okamoto (SCE CTO) Technology Group
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Questions?
On the web: http://www.technology.scee.net/ E-mail:
[email protected] Technology Group
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