2015 26th Annual SEMI Advanced Semiconductor Manufacturing Conference (ASMC 2015)

Saratoga Springs, New York, USA 3-6 May 2015

IEEE Catalog Number: ISBN:

CFP15ASC-POD 978-1-4799-9931-6

TABLE OF CONTENTS

Nanoparticle Reduction in Cu CMP for 20nm Node and Beyond ..................................................................................... 1 D. Jeanjean, O. Robin, R. Sramek, S. Mermoz, G. Ducotey, S. Gaillard, Y. Chen, F. Pitard, L. Nicoud, B. Brown

Correlation of Non-Visual Defects at Post Copper CMP to Yield Critical Physical Defects at Next Metallization Layer ............................................................................................................................................................... 6 M. Specht, H. Franke, O. Luxenhofer, K. Mai, W. Usry, R. Newcomb

Using the Low Frequency Component of the Background Signal for Sige and Ge Growth Monitoring ..................... 10 S. Halder, A. Schulze, P. Leray, M. Caymax, G. Bast, G. Simpson, N. Ulea, M. Polli

Defect Reduction for 20nm High-k Metal Gate Technology ............................................................................................ 14 V. Chabois, J. Lebreton, M. Savoye, E. Labonne, A. Labourier, B. Dumont, C. Lenox, M. Hoff

Inspection Challenges for Triple Patterning at Sub-14 nm Nodes with Broadband Plasma Inspection Platforms .............................................................................................................................................................................. 19 S. Halder, V. Truffert, D. Heuvel, P. Leray, S. Cheng, G. McIntyre, K. Sah, J. Brown, P. Parisi, M. Polli

Managing the Economic Constraints of Foundies and Fabless Enterprises ................................................................... 23 C. Weber, J. Yang

Production Control in Semiconductor Manufacturing with Time Constraints.............................................................. 29 R. Sadeghi, S. Dauzere-Peres, C. Yugma, G. Lepelletier

Shortening of Cycle Time in Semiconductor Manufacturing Via Meaningful Lot Sizes............................................... 34 D. Eberts, S. Keil, F. Peipp, R. Lasch

Use of Simulation Studies to Overcome Key Challenges in the Fab Automation of a 300 mm Power Semiconductor Pilot Line Comprising Thin-Wafer Processing....................................................................................... 42 G. Scheider, T. Wagner, M. Kraft

Bridging the Gap – Integrating APC Constraints and WIP Flow Optimization to Enhance Automated Decision Making in Semiconductor Manufacturing ......................................................................................................... 48 M. Stehli, D. Zschabitz, T. Jahnig

Collapse-Free Patterning of High Aspect Ratio Silicon Structures for 20nm NAND Flash Technology...................... 53 V. Iyengar, S. Chandrasekaran, D. Weddington, M. Nettles, O. Eagle, S. Tey, T. Parry

Standby Leakage Current Reduction in a 180nm EEPROM Process Technology ........................................................ 58 S. Menon, M. Agam

A Case Study On Sever Yield Loss Caused by Wafer Arcing in BEOL Manufacturing............................................... 64 H.-J. Lee, H.-S. Yu, S.-C. Lee, C.-K. Yang, S.-E. Chang, K.-F. Lo, X.-G. Lin, N.-T. Lian, T. Yang, K.-C. Chen

Effect Of Top Corner Rounding in BEOL To Yield In Advanced Technologies ........................................................... 68 E. Ramanathan, M. Silvestre, A. Mahalingam, N. Garg, S. Siddhartha, C. Ordonio, J. Schaller

Integrated Metrology’s role in Gas Cluster Ion Beam Etch............................................................................................. 72 T. Kagalwala, R. Dasaka, M. Aquilino, A. Cepler, C. Kang, N. Yellai

Methodology to Estimate TSV Film Thickness Using a Novel Inline “Adaptive Pattern Registration” Method.................................................................................................................................................................................. 78 S. Manikonda, D. Zhang, R. Giridharan, A. Bello, J. Song

Optical Step Height and Trench Depth Measurement ..................................................................................................... 84 F. Heider, G. Janisch, M. Kern, K. Weinzierl, B. Troger, M. Meyer

Through Silicon Via Process Characterization by Integrated Inspection/Metrology Solutions in Visible and Infrared Domain .............................................................................................................................................. 90 N. Devanciard, S. Rey, T. Magis, S. Minoret, C. Beitia, D. Alliata, D. Marx, P. Bachiraju, D. Hart, J. Thornell, R. Dudley

Effective Wet Clean Method to Eliminate Unwanted Growth SiGe Defect in FinFET ................................................. 96 J. Li, J. Prasad, B.-G. Min, Z. Sun

450mm SEMI Physical Interface Standards: Architecture and Efficiency..................................................................... 99 M. Haddadin, S. Radloff

Advanced Contamination Control Methods for Yield Enhancement ........................................................................... 105 H. Richter, A. Leibold, R. Altmann, B. Doffek, J. Koebl, M. Pfeffer, A. Bauer, G. Schneider, D. Cheung

Optical Properties Determination of Fully Depleted Silicon on Insulator (FDSOI) Substrates by Ellipsometry ....................................................................................................................................................................... 109 L. Schneider, F. Abbate, D. Cunff, E. Nolot, A. Michallet

Using a Visible BI to Construct Lean Manufacturing within Big Data......................................................................... 115 S. Chiu, H. Lin, J. Hsu, C. Chiu

Application of a 3-Step Kaizen Strategy for Improvement of WIP Flow in a Semiconductor Fab ............................ 119 S. Comulada, J. Mendola

Automatic Metrology Algorithm Identification Using Pattern Matching..................................................................... 124 D. Fischer, K. Akid, D. Abdelhaliem, I. Abed, J. Lebritton, J. Opitz, N. Dragiewicz, C. McGinty, E. Lavigne

Big Data Emergence in Semiconductor Manufacturing Advanced Process Control ................................................... 130 J. Moyne, J. Samantaray, M. Armacost

Blowback Filtration for CVD Vacuum Pump Protection............................................................................................... 136 J. Ruth, G. Heser, M. Wagner

Challenges in Integrating Embedded Non Volatile Memory with Floating Poly and ONO in Base Line Process ................................................................................................................................................................................ 141 M. Agam, S. Menon, P. Cosmin, T. Yao, P. McGrath, B. Ruiz, B. Baylis, E. Ameele, K. Rolofson, R. Young

Device Specific Characterization of Yield Limiting Pattern Geometries by Combining Layout Profiling with High Sensitivity Wafer Inspection ........................................................................................................... 146 J.-C. Denmat, L. Tetar, P. Fanton, E. Yesilada, P.-J. Goirand, N. Narasimhan, P. Parisi, V. Ramachandran, S. Kekare

Effect of Defectivity Reduction in Spacer and Junction Modules on RMG Defectivity............................................... 150 A. Sehgal, S. Kuchibhatla, B. Krishnan, D. Bhattacharyya, J. Wan, H.-C. Peng, S. You

Effective Wet Clean Method to Eliminate Unwanted Growth SiGe Defect in FinFET ............................................... 152 J. Li, J. Pradad, B.-G. Min, Z. Sun

Emerging Atomic Layer Deposition (ALD) Processes For Low Thermal Budget Flexible Electronics ..................... 155 D. Gregory, G. Marshall, E. Eisenbraun

Energy Conservation Mode Signalling Standardization ................................................................................................ 158 G. Crispieri, M. Czerniak

High Aspect Ratio Etch Yield Improvement by A Novel Polymer Dump Thickness Metrology ................................ 161 J. Ye, G. Ega, S. Thompson

Impact of Molybdenum Contamination on Stacking Faults in Epitaxial Silicon ......................................................... 167 M. McCormick, P. Porath

Improved Ion Implant Exhaust Management for Reduced Energy and Capital Costs ............................................... 169 J. Sweeney, K. Olander, S. Ballance

Inspection Step Modeling for Defect Source Tool Identification Using Defectivity Control ....................................... 173 M. Chakaroun, R. Messouci, M. Chakaroun, J. Pinaton, M. Djeziri, M. Ouladsine

Local Wafer Temperature Non-uniformity Correction with Laser Irradiation .......................................................... 179 P. Rao

Managing Fab UHP N2 By Measuring Trace Moisture.................................................................................................. 185 D. Barth, M. Wagner, M. Bolkenius, J.-L. Cloarec

Modeling and Dispatching Refinement for Implantation to Reduce the Probability of Tuning Beam ...................... 190 K.-T. Yang, L. Ke, T. Shen

Optical Properties Determination of Fully Depleted Silicon on Insulator (FDSOI) Substrates by Ellipsometry ....................................................................................................................................................................... 195 L. Schneider, F. Abbate, D. Cunff, E. Nolot, A. Michallet

Post TSV Etch Cleaning Process Development using SAPS Megasonic Technology ................................................... 201 F. Chen, X. Zhang, X. Wang, X. Tao, S. Yang, D. Wang, V. Vartanian, B. Sapp

ProGuctivity Challenges in PVD Processing in 300mm Pilot Lines for Power Semiconductors.................................. 204 A. Rastogi, N. Morin, C. Jones, S. Burgess, R. Trowell, C. Widdicks, I. Moncrieff, M. Ehmann, S. Schmidbauer

Quick Process Troubleshooting by Using Advanced SEM ADC System ...................................................................... 209 C. Hsieh, C. Yang, S. Gao, J. Chen, W. Chen, H. Chen, A. Cheng

Rapid Non-Destructive Detection Of Sub-Surface Cu in Silicon-On-Insulator Wafers by Optical Second Harmonic Generation........................................................................................................................................... 212 V. Koldyaev, M. Kryger, J. Changala, M. Alles, D. Fleetwood, R. Schrimpf, N. Tolk

Real-Time Information Base as Key Enabler for Manufacturing Intelligence and “Industrie 4.0”........................... 216 G. Luhn, K. Bartl, D. Habich, J. Postel, T. Stevens, M. Zinner

Spatial Risk Assessment on Circular Domains: Application to Wafer Profile Monitoring......................................... 223 E. Padonou, O. Roustant, J. Blue, H. Duverneuil

Trace Analysis of Hydrogen Peroxide Contamination ................................................................................................... 228 M. Lydon, J. Ritter, J. Comeau

Track Process Monitoring Via Laser Scattering Imaging.............................................................................................. 232 L. Meli, R. Kwong, C. Murray, K. Petrillo, A. Hubbard, P. Dhagat, S. Macnish, C. Palamadai

Yield Improvement in Dense EEPROM by Bit Mapping and Experimental Design................................................... 237 M. Agam, S. Menon, P. Cosmin

Using a Visible Bi to Construct Lean Manufacturing Within Big Data........................................................................ 241 S. Chiu, H. Lin, J. Hsu, C. Chiu

The Merits of High Landing Energy for E-beam Inspection ......................................................................................... 245 O. Patterson, R. Hafer, X. Tang, S.-C. Lei

Application of Backscattered Electron Imaging for Process Development in Advanced Technology Nodes................................................................................................................................................................................... 251 M. Lei, K. Wu, H. Nguyen, M. King, H. Xiao, D. Spivak, J. Brown, O. Moreau, P. Macdonald

Novel Method for Detecting Bitline Contact Misalignment Using Quantitative Analysis of HighAspect Ration SEM Images .............................................................................................................................................. 255 H. Ang, K. Lim, Q. Deng, K. Tan, W. Lim, J. Zhang, R. Porat, K. Chng, S. Wee, K. Cheng, G. Gichon, R. Mizrahi

E-beam Inspection Throughput Acceleration Via Targeted Critical Area Inspection ................................................ 260 O. Patterson, R. Topaloglu, R. Hafer, S.-C. Lei, X. Tang

Enabling Future Generation High-Speed Inspection Through a Massively Parallel E-beam Approach................... 266 M. Malloy, B. Bunday, S. Wurm, B. Thiel, T. Kemen, D. Zeidler, A. Eberle, T. Garbowski, G. Dellemann, J. Peters

Using Fractal Dimensions as Performance Indicators for Manufacturing Systems .................................................... 272 G. Grau, D. Pabst, M. Stehli

An Empirical Approach to Accurate Single Wafer Wet Etch Simulation .................................................................... 276 M. Singh, P.-J. Huang, P.-C. Yu, J. Shih

Segmentation of the Expected Duration of Maintenance Activities in Semiconductor Fabs....................................... 280 I. Regev, D. Benson-Karhi

Semiconductor Green Fabrication Innovative Energy Efficient Design and Operational Optimization of Chilled Water System.................................................................................................................................................... 286 J. Shyu, L. Zhu, T. Anadani, Y. Wang, H. Fung, C. Chang

Conceptual Product Planning........................................................................................................................................... 290 R. Bannister, J. Bickford, H. Johnson

Semiconductor Equipment Assessment – An Enabler for Production Ready Equipment .......................................... 296 M. Pfeffer, L. Pfitzner, A. Bauer

Validation of High Efficiency ICP Source Performance for Advanced Resist Ashing ................................................ 301 V. Nagorny, V. Vaniapura, V. Surla

Selective Isotropic Wet Etching of TiN and TaN for High k Metal Gate Structure..................................................... 305 D. Bhattacharyya, S. Kuchibhatla, A. Schgal, Y. Shen, H. Wang, J. Prasad

Wafer Topology Effect on the Etching Saturation Behaviors in NF3/NH3 Remote Plasmas ....................................... 309 K.-F. Lo, F.-H. Hsu, X.-G. Lin, H.-Ji Lee, N.-T. Lian, T. Yang, K.-C. Chen

Predictive Data Analytics and Machine Learning Enabling Metrology and Process Control for Advanced Node IC fabrication ......................................................................................................................................... 313 N. Rana, Y. Zhang, D. Wall, B. Dirahoui

On-product Performance Improvement Via Advanced Litho-Cluster Control Using Integrated Metrology and Multi-layer Overlay Target..................................................................................................................... 320 K. Bhattacharyya, M. Maassen, E. Schmitt-Weaver, R. Tijssen, J. Chen, G. Hung

CPE Run-to-Run Overlay Control for High Volume Manufacturing........................................................................... 324 L. Subramany, W. Chung, K. Gutjhar, M. Garcia-Medina, C. Sparka, L. Yap, O. Demirer, R. Karur-Shanmugam, B. Riggs, V. Ramanathan, J. Robinson, B. Pierson

CD Metrology for EUV Lithography and Etch............................................................................................................... 329 H. Johanesen, A. Kenslea, M. Williamson, M. Knowles, L. Kwakman, J. Puymbroeck, D. Felder, S. Levi, N. Nishry, O. Adan, I. Englard, S. Gov, O. Cohen, I. Turovets

In-line Inspection of DRC Generated Hotspots............................................................................................................... 336 A. Srivastava, H. Nguyen, T. Hermann, R. Kirsch, R. Kini

Monitoring Process-induced Focus Errors Using Highresolution Flatness Metrology................................................ 340 B. Morgenfeld, T. Brunner, K. Nummy, D. Stoll, N. Jing, H. Lin, P. Vukkadala, P. Herrera, R. Ramkhalawon, J. Sinha

Process Induced Wafer Geometry Impact on Center and Edge Lithography Performance for Sub 2X nm Nodes ............................................................................................................................................................................ 345 S. Tran, W. Ng, M. Johnson, D. Kewley, V. Subramony, S. Veeraraghavan, M. Chang, J. Sinha

Printability Study of Reticle Defects on Wafer Using Reticle Defect Review on E-beam Review Tools .................... 351 C. Cho, R. Taylor, A. Mungmode, D. Fan, D. Spivak, J. Camp, H. Xiao

MEMS Manufacturing Solutions ..................................................................................................................................... 356 J. Fukui, M. Osanai, S. Mizoroke, H. Khorram

Backside and Edge Cleaning of III-V on Si Wafers for Contamination Free Manufacturing .................................... 362 A. Vert, T. Orzali, T. Dyer, R. Hill, P. Satyavolu, E. Barth, R. Gaylord, S. Hu, S. Vivekanand, J. Herman, U. Rana, V. Kaushik

Particle Free Handling of Substrates ............................................................................................................................... 367 H. Samadi, M. Pfeffer, R. Altmann, A. Leibold, T. Gumprecht, A. Bauer

Optimized Salicide Clean To Reduce Post Fill Defectivity............................................................................................. 372 S. Singh, P. Muralidhar, S. Jayaseelan, Y. Hu, S. Scott

Eliminating Arsenic Containing Residue that Create Killer Defects in 20 nm HVM .................................................. 375 A. Sehgal, S. Kuchibhatla, B. Krishnan, J. Wan, H.-C. Peng, H. Zhan, J. Liu

Yield Improvement in 2x Node Technology by Introducing Backside Cleaning.......................................................... 379 N. Garg, B. Rajagopalan, S. Scott, R. Hoech

Predictive Maintenance in Semiconductor Manufacturing ........................................................................................... 384 J. Iskandar, J. Moyne, K. Subrahmanyam, P. Hawkins, M. Armacost

Advanced Process Control (APC) and Real Time Dispatch (RTD) System Integration for Etch Depth Control Process in 300mm Fab......................................................................................................................................... 390 G. Agrawal, S. Loh, A. Shebi

A Study of Feed-forward Strategies for Overlay Control in Lithography Processes Using CGS Technology ......................................................................................................................................................................... 395 D. Anberg, D. Owen, B.-H. Lee, S. Shetty, E. Bouche

Critical Sensitivity of Flash Gate Dimension Spread on Electrical Performances for Advanced Embedded Memory ........................................................................................................................................................... 401 E. Agharben, A. Roussy, M. Bocquet, M. Bileci, S. Begouin, A. Marchadier

Improving Reliability Through Nitrogen Purge of Carriers.......................................................................................... 405 R. Roijen, A. Amanda, J. Ayala, L. Morgenfeld, G. Rosa

Hammer Test to Detect BEOL Process Marginalities on Via Chains in Advanced Nodes.......................................... 408 A. Mahalingam, M. Silvestre, E. Ramanathan, C. Ordonio, J. Schaller

Vertical Natural Capacitor Time Dependent Dielectric Breakdown (TDDB) Improvement in 28nm ....................... 411 M. Silvestre, Z. Wenyi, K. Selvam, E. Ramanathan, C. Ordonio, J. Schaller, L. Hyup, C. Capasso, P. Justison

Composite Attribute Method and Software to Interlock Semiconductor Product Design and Manufacturing Yield ......................................................................................................................................................... 416 J. Bickford, L. Rolfing, C. Sullivan, C. They, E. Wolf, J. Yoder, P. Niekrewicz

Deep Trench Capacitor in Three Dimensional Through Silicon Via Keepout Area for Electrostatic Discharge Protection ......................................................................................................................................................... 421 N. Habib, M. Muhammad, J. Bickford, J. Safran, A. Ginawi, F. Towler

Enhanced Etch Process for TSV & Deep Silicon Etch.................................................................................................... 426 Q. Xu, A. Paterson, J. McChesney, R. Dover, Y. Yamaguchi, A. Eppler

Precision Wafer Bonding Process for Future Cost-Effective 3DICs ............................................................................. 429 I. Sugaya, H. Mitsuichi, H. Maeda, T. Tsuto, H. Nakahira, M. Okada, K. Okamoto

Yield Enhancement and Mitigating the Si-Chipping and Wafer Cracking in Ultra-Thin 20um-Thick 8- and 12-Inch LSI Wafer ................................................................................................................................................. 435 M. Murugesan, T. Fukushima, J. Bea, K. Lee, M. Koyanagi

Remote Plasma Processing for Reduction of CuOx before Damascene Electroplating ............................................... 440 T. Spurlin, J. Reid

Modelling of the Electrochemical Etch Stop with High Reverse Bias Across Pn-junctions ........................................ 445 R. Szwarc, L. Frey, H. Weber, T. Erlbacher, M. Rommel, I. Moder, A. Bauer

300mm Wafer Level Sulfur Monolayer Doping for III-V Materials ............................................................................. 451 W.-Y. Loh, R. Lee, R. Tieckelmann, T. Orzali, B. Sapp, C. Hobbs, S. Rao, K. Fuse, M. Sato, N. Fujiwara, L. Chang, H. Uchida

Multiple Epitaxial Si Film Deposition by APCVD for Power Semiconductors ............................................................ 455 M. Kunle, J. Baumgartl, K. Koren, O. Fielder Author Index