SKA STATION BEAMFORMER CONCEPT DESCRIPTION Document number .................................................................. WP2‐040.120.010‐TD‐001 Revision ........................................................................................................................... 1 Author .................................................................................................................. M Jones Date ................................................................................................................. 2011‐03‐29 Status ............................................................................................... Approved for release Name
Designation
Affiliation
Date
Signature
Additional Authors Kristian Zarb Adami, Stef Salvini, Andrew Faulkner, Vassily Khlebnikov, Chris Shenton Submitted by: K Zarb Adami
UOXF
2011‐03‐26
2011‐03‐29
Approved by: W. Turner
Signal Processing Domain Specialist
SPDO
WP2‐040.120.010‐TD‐001 Revision : 1
DOCUMENT HISTORY Revision
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First draft release for internal review
1
29 March 2011
First Issue
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Word 2003
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03i‐wp2‐040.120.010‐td‐001‐1‐StationBFM‐concept‐description‐2003
ORGANISATION DETAILS Name Physical/Postal Address
SKA Program Development Office Jodrell Bank Centre for Astrophysics Alan Turing Building The University of Manchester Oxford Road Manchester, UK M13 9PL +44 (0)161 275 4049 www.skatelescope.org
Fax. Website
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TABLE OF CONTENTS 1 INTRODUCTION ............................................................................................. 9 1.1
Purpose of the document ....................................................................................................... 9
2 REFERENCES .............................................................................................. 10 3 OVERVIEW OF STATION PROCESSING ............................................................... 12 3.1 3.2 3.3 3.4 3.5
SKA System Description ........................................................................................................ 12 Justification for Station Processing ....................................................................................... 13 SKA‐1 Data Rate .................................................................................................................... 13 SKA‐1 Operation Count ......................................................................................................... 13 Station Block Diagram ........................................................................................................... 14
4 STATION PROCESSING .................................................................................. 16 4.1 Channelisation ...................................................................................................................... 16 4.2 Beamforming Schemes ......................................................................................................... 21 4.3 Digital Beamforming ............................................................................................................. 23 4.3.1 Frequency‐Space Beamforming .................................................................................... 24 4.3.2 Space‐Frequency Beamforming .................................................................................... 26 4.3.3 Wideband Digital Time‐Aligning ................................................................................... 27
STAGGERED NARROWBAND BEAMFORMING ............................................................ 28 4.3.4 Hierarchical Beamforming ............................................................................................ 29 4.3.4.1 Simulations of hierarchical beamforming schemes .................................................. 29 4.4
Beamforming Technology Comparison ................................................................................. 31
5 ALL‐DIGITAL PHASE SHIFT BEAM FORMING ALGORITHMS ..................................... 34 5.1 Single Level Beam Forming ................................................................................................... 35 5.1.1 DFT beam forming ......................................................................................................... 35 5.1.2 Gridding + FFT beam forming ....................................................................................... 36 5.2 Hierarchical, Two‐Level Beam Forming ................................................................................ 36 5.2.1 DFT Algorithms .............................................................................................................. 36 5.2.2 Gridding + FFT Algorithms ............................................................................................. 37 5.3 Beamforming Processing Structure ...................................................................................... 37
6 DATA RATES .............................................................................................. 39 7 WIDE FOV VS. GAIN TRADEOFF: A POSSIBLE ALTERNATIVE .................................... 39 7.1
Antennas Calibration............................................................................................................. 41
8 SKA‐1 SYSTEM SIMULATION ......................................................................... 41 9 COMPARISON OF DIGITAL PROCESSING SOLUTIONS ............................................. 44
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10
Digital processing devices ..................................................................................................... 44
CALIBRATION AND GRACEFUL DEGRADATION ................................................... 47
10.1 Calibration process................................................................................................................ 48 10.1.1 Design time calibration ................................................................................................. 48 10.1.2 Commissioning calibration ............................................................................................ 48 10.1.3 Pre‐observation calibration .......................................................................................... 48 10.1.4 Calibration during observations .................................................................................... 48
11
RISK REGISTER ........................................................................................ 49
12
COST AND POWER ESTIMATES ..................................................................... 50
13
RESOURCE ALLOCATION AND NON‐RECURRING EXPENDITURE ............................. 51
14
CONCLUSIONS ......................................................................................... 52
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LIST OF FIGURES Figure 2: The role of station processing in relation to the other system components ........................ 14 Figure 1: A possible distribution of the processing architectures throughout the station. ................. 14 Figure 3: Successive splitting of the input bandwidth into channels of finer resolution ..................... 16 Figure 4: Polyphase filter bank followed by an N‐point DFT (implemented in an FPGA) through an FFT .................................................................................................................................................... 17 Figure 5: The dynamic range due to the different input sample bit‐widths (courtesy of A Parsons and D Werthimer) .............................................................................................................................. 18 Figure 6: Dynamic Range of Polyphase filter bank due to the length of FIR‐Filter (Courtesy of A Parsons and D Werthimer) ......................................................................................................... 19 Figure 7: Dynamic Range of Polyphase Filter bank due to the Bit‐Width of the filter co‐efficients (Courtesy of A Parsons and D Werthimer) ................................................................................. 20 Figure 8: Output of a Polyphase filter bank showing a spectral dynamic range of ≈70dB ................... 21 Figure 9: The Beamforming operation .................................................................................................. 22 Figure 10: Digital processing system ..................................................................................................... 24 Figure 11: Frequency‐Space Beamformer ............................................................................................ 25 Figure 12: Space‐Frequency Beamformer ............................................................................................ 26 Figure 13: Linear Interpolation based fractional delaying .................................................................... 28 Figure 14: Hierarchical beamforming. Layout of station beams in a Tile beam is illustrated on the left. The stepped nature of beamforming for off‐centre beams is illustrated on the right. ............. 30 Figure 15: Effect on station beams offset from the tile beam simulation using OSKAR ...................... 30 Figure 16: Two‐level hierarchical beamforming ................................................................................... 37 Figure 17: Single‐level beamforming (direct station beam forming) .................................................... 38 Figure 18: Partitioning the station ........................................................................................................ 40 Figure 19: Single‐station inner‐level beamforming .............................................................................. 41 Figure 20: Full SKA‐1 simulated sky image ............................................................................................ 43 Figure 21: Multi‐level computational structure: 4 2x2 tiles; 1 tile beam, split into 4 station beams .. 50
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LIST OF TABLES Table 1: Proposed station layout and specifications within the SKA [From Memo 130] ..................... 12 Table 2: Operation count for the various beamforming schemes ........................................................ 29 Table 3: Comparison between RF and Digital Beamforming Architectures ......................................... 34 Table 4: Assumption made for digital beamforming architectures ...................................................... 35 Table 5: Comparison of Procesing architectures .................................................................................. 47 Table 6: Cost and Power Estimates of a Station Processor .................................................................. 51 Table 7: NRE effort for station processing ............................................................................................ 52
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LIST OF ABBREVIATIONS AA.................................. Aperture Array ADC ............................... Analogue-to-Digital Converter AI ................................... Arithmetic Intensity ASIC .............................. Application-Specific Integrated Circuit CoDR............................. Conceptual Design Review CMAC ............................ Complex Multiplication and ACcumulation CPU ............................... Central Processing Unit CUDATM ......................... Compute Unified Device Architecture (NVIDIA 2009) DFT ............................... Discrete Fourier Transform DiFX .............................. Distributed FX correlator (Deller et al. 2007) DRAM ............................ Dynamic Random Access Memory DRM .............................. Design Reference Mission DSP ............................... Digital Signal Processing eMERLIN ....................... extended Multi-Element Radio-Linked Interferometer Network eVLA.............................. Extended Very Large Array FFT ................................ Fast Fourier Transform FLOPS........................... Floating Point Operations per second FPGA............................. Field Programmable Gate Array FoV ................................ Field of View GMRT ............................ Giant Meter-wave Radio Telescope GPGPU ......................... General-Purpose Graphics Processing Unit GPU............................... Graphics Processing Unit HPC ............................... High-Performance Computing IF ................................... Intermediate Frequency LO.................................. Local Oscillator LOFAR .......................... LOw-Frequency ARray MPI ................................ Message Passing Interface (MPI Forum 2009) MWA.............................. Murchison Wavefield Array NRE ............................... Non-Recurring Engineering PEP ............................... Project Execution Plan PrepSKA........................ Preparatory Phase for the SKA RF.................................. Radio Frequency SEMP ............................ Systems Engineering Management Plan SRS ............................... Systems Requirement Specification SIMD ............................. Single Instruction Multiple Data SKA ............................... Square Kilometre Array SKADS .......................... SKA Design Studies
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SPDO ............................ SKA Program Development Office TBD ............................... To be decided VLBA ............................. Very Long Baseline Array WIDAR .......................... Widefield Interferometric Digital ARchitecture (correlator implementation)
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Introduction
The aim of this document is to give a mid‐to‐high‐level description of the processing requirements for a single station. Included in this processing architecture is:
the channelisation of the input bandwidth into finer channels;
the beamforming of antennas to reduce the field‐of‐view for correlation;
Whilst the aim of this document is not to provide a definitive architecture for implementing the channelization and beamforming operations carried out in the station, it is meant to highlight the feasibility of each architecture so that these may be compared and contrasted. Throughout the document, we will keep the architecture generally technology agnostic, but we will include a section that discusses the trade‐offs between Analogue Beamforming, and various technologies for the implementation of digital beamforming including ASIC(s), FPGA(s) and GPU (based on Nvidia products). Due to evolution of the technology architectures throughout the time interval between the writing of this document and the implementation of SKA Phase‐1 (2016‐2019) 2019 (Garrett et al. 2010, Dewdney et al. 2010), we will make reference to the digital signal processing (DSP) technology roadmap (Turner 2011) and supply recommendations based on this forecast.
1.1 Purpose of the document This document is to reside within a larger host of documents that describe the signal processing chain from the antenna to the imaging architecture as part of the SKA Signal Processing Design Review (CoDR). It provides a top‐down and bottom‐up description of the station processing that is required. In accordance with general Systems Engineering principles, it will include:
a top‐level system block diagram including channelization and various beamforming schemes (integer time‐delay, fractional time‐delay and phase‐shift beamforming);
a comparison in terms of cost and power estimates of each of the various schemes;
a series of recommendations on the implementation of the various schemes;
a discussion of the manufacturability and reliability of each of the various schemes.
System parameters for SKA Phase 1 have been drawn from Garrett et al. (2010), Dewdney et al. (2010) and the SKA Phase 1 Design Reference Mission (DRM) while the Systems Requirement Specification (SRS) is being created.
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References [1] SKA Science Case [2] The Square Kilometre Array Design Reference Mission: SKA‐mid and SKA‐Lo v 0.4 [3] Science Operations Plan [4] System Interfaces [5] Environmental requirements (natural and induced) [6] SKA strategies and philosophies [7] Risk Register [8] Requirements Traceability [9] Logistic Engineering Management Plan (LEMP) [10] Risk Management Plan (RMP) [11] Document Handling Procedure [12] Project Dictionary [13] Strategy to proceed to the next phase [14] WP3 SKA array configuration report [15] WP3 SKA site RFI environment report [16] WP3 Troposphere measurement campaign report [17] SKA Science‐Technology Trade‐off Process (WP2‐005.010.030‐MP‐004) [18]A. Faulkner, et al., Aperture Arrays for the SKA: the SKADS White Paper, January 2010. [19] E. de Lera‐Acedo et al., System Noise Analysis of an Ultra Wide Band Aperture Array: SKADS Memo T28. [20] SKA Monitoring and Control Strategy WP2‐005.065.000‐R‐001 Issue Draft E [21]“The Square Kilometre Array”, Peter E. Dewdney, Peter J. Hall, Richard T. Schilizzi, and T. Joseph L. W. Lazio, Proceedings of the IEEE Vol. 97,No. 8, August 2009 [22] Thompson, A. R., Moran, J. M., and Swenson, G. W. “Interferometry and Aperture Synthesis in Radio Astronomy” (second edition), Wiley, 1986. [23] System Engineering Management Plan (SEMP) WP2‐005.010.030‐MP‐001Reference 3 [24] SKA System Requirement Specification (SRS) [25] SKA IP Policy Document [26] International Technology Roadmap for Semiconductors (ITRS), available at www.itrs.net. [27]Garrett, M.A., et al. (2010), A Concept Design for SKA Phase 1 (SKA1), Memo 125 [28]Dewdney, P., et al. (2010), SKA Phase 1: Preliminary System Description, Memo 130 [29]Turner, W., (2011), Technology Roadmap Document for SKA Signal Processing, WP2‐ 040.030.011‐TD‐001 [30]System Engineering Management Plan (SEMP), WP2‐005.010.030‐MP‐001 [31]SKA System Requirement Specification (SRS) [32]Thompson, A. R., Moran, J. M., and Swenson, G. W. (2001), Interferometry and Aperture Synthesis in Radio Astronomy, second ed., Wiley (New York) [33]Deller, A.T., et al. (2007), DiFX: A Software Correlator for Very Long Baseline Interferometry using Multiprocessor Computing Environments, PASP, 119, 318 [34]MPI Forum (2009), MPI: A Message‐Passing Interface Standard, Version 2.2 [35]Roy, J., et al. (2010), A real‐time software backend for the GMRT, ExA, 28(25) [36]Romein, J.W., et al. (2009), Astronomical Real‐Time Streaming Signal Processing on a BlueGene/P Supercomputer.
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WP2‐040.120.010‐TD‐001 Revision : 1 [37]De Souza, L., Bunton, J.D., Campbell‐Wilson, D., Cappallo, R., Kincaid, B., 'A Radioastronomy Correlator Optimised for the Virtex‐4 SX FPGA', IEEE 17th International Conference on Field Programmable Logic and Applications, Amsterdam, Netherland, Aug 27‐29, 2007 [38]L. D'Addario, "ASIC‐BASED PROCESSING FOR MINIMUM POWER CONSUMPTION ‐‐ CONCEPT DESCRIPTION FOR PHASE 1," dated 2011‐03‐02. Available on SKA Wiki, Signal Processing section, CoDR document 3 [39]Harris, C., et al. (2008), GPU accelerated radio astronomy signal convolution, Exp Astron, 22, 129 [40]van Nieuwpoort, R.V., and Romein, J.W. (2009), Using Many‐Core Hardware to Correlate Radio Astronomy Signals, SKADS DS3‐T2 Deliverable Document [41]Wayth, R.B., Greenhill, L.J., and Briggs, F.H. (2009), A GPU‐based real‐time software correlation system for the Murchison Widefield Array prototype, PASP, 121, 857 [42]NVIDIA (2009), NVIDIA CUDATM Programming Guide, Version 2.3.1 [43]Alexander, P., et al. (2010), SKA Data Flow and Processing, in Wide Field Astronomy & Technology for the Square Kilometre Array, ed. Torchinsky, S., et al.
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Overview of Station Processing
3.1 SKA System Description As described in the Preliminary System Description (Memo 130), SKA Phase‐1 will be composed of a central core of stations with a few stations dispersed over baselines of up to 100km from the central core as is shown in table 1. As can be seen from table 1, the aim is to have 50% of the stations within the core and the remaining 50% of the stations distributed with a tapered density distribution out to 100km. In this document it is assumed that each station is identical, even though in practice this assumption is not necessary. Table 1 (adapted from http://wiki.skatelescope.org/bin/view/SignalProcessing/WebHome), gives a top‐level description of each station within both Phase‐1 and Phase‐2 of the SKA and highlights the evolution between Phase‐1 and Phase‐2. Number of Stations Number of antenna per station
Phase 2
Phase 1 50 11,200
250 11,200
Core (radius