SD, GPIO, NAND U4-B

A21

SD1_DAT0

SD1_D1

C20

SD1_DAT1

SD1_D2

E19

SD1_DAT2

SD1_D3

F18

SD1_DAT3

SD2_CMD SD2_CLK

F19

SD2_CMD

C21

SD2_CLK

SD2_D0

A22

SD2_DAT0

SD2_D1

E20

SD2_DAT1

SD2_D2

A23

SD2_DAT2

SD2_D3

B22

SD2_DAT3

SD3_CMD

B13

SD3_CMD

SD3_CLK

D14

SD3_D0

E14

SD3_D1

F14

SD3_DAT1

SD3_D2

A15

SD3_DAT2

SD3_D3

B15

SD3_DAT3

RGMII_MDIO

ENET_CRS_DV U21 ENET_REF_CLK V22 ENET_RX_ER

W23

ENET_TX_EN

V21

ENET_RXD0

W21

ENET_RXD1

W22

ENET_TXD0

U20

ENET_TXD1

W20

RGMII_REF_CLK

WIFI_IRQ

UART4_TXD UART4_RXD

SD3_CLK

KEY_COL1

U7

UART5_TXD

SD3_DAT0

KEY_ROW1

U6

UART5_RXD

KEY_COL2

W6

CAN_1_TXD

KEY_ROW2

W4

CAN_1_RXD

KEY_COL3

U5

KEY_ROW3

T7

KEY_COL4

T6

CAN_2_TXD

KEY_ROW4

V5

CAN_2_RXD

GPIO_0

T5

AUD_MCLK

GPIO_1

T4

GPIO_2

T1

USB_OTG_ID RED_LED#

GPIO_3

R7

GPIO_4

R6

GPIO_5

R4

DIO_1

GPIO_6

T3

DIO_2

GPIO_7

R3

GPIO_8

R5

GPIO_9

T2

DIO_3

SD3_DAT4 SD3_DAT5 SD3_DAT6

UART1_TXD EMMC_RESET#

F13

SD3_DAT7

D15

SD3_RST

E16

SD4_CLK

B17

SD4_CMD

D18

SD4_DAT0

B19

SD4_DAT1 SD4_DAT2

UART2_TXD UART2_RXD

GPIO_16

R2

DIO_4

SD4_DAT4

GPIO_17

R1

DIO_5

C19

SD4_DAT5

GPIO_18

P6

B20

SD4_DAT6

GPIO_19

P5

D19

SD4_DAT7

C16

NANDF_CS2

A17

B11

MLB_CP

NANDF_CS3

D16

A11

MLB_CN

NANDF_ALE

A16

NANDF_CLE

C15

B9

MLB_SP

NANDF_WP

E15

A9

MLB_SN

NANDF_RB0

B16

A10

MLB_DP

NANDF_D0

A18

B10

MLB_DN

NANDF_D1

C17

NANDF_D2

F16

NANDF_D3

D17

NANDF_D4

A19

NANDF_D5

B18

NANDF_D6

E17

NANDF_D7

C18

R76 4.99K

FPGA_24MHZ_CLK FPGA_IRQ

E18

F15

R75 4.99K

I2C_2_DAT

SD4_DAT3

NANDF_CS1

3.3V

I2C_2_CLK

A20

NANDF_CS0

Et he rne t

RGMII_INT#

V6

E13

UART2_CTS#

RGMII_MCLK

V23

W5

UART1_RXD

F17

V20

KEY_COL0

C13

LCD_PWM

ENET_MDC ENET_MDIO

KEY_ROW0

NVCC_GPIO

D13

NVCC_ENET

SD1_D0

NVCC_SD2

SD1_CLK

NVCC_NANDF

e MMC (3.3V)

SD1_CMD

D20

NVCC_SD3

SD Ca rd (3.3V)

B21

SD1_CLK

NVCC_SD4

WiFi (1.8V)

SD1_CMD

NVCC_SD1

i.MX6Q

DIO_7

MX6_SINGLE_CORE_BGA624

Te chnologic Sys t e ms Tit le : Re v:

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Ma y 21, 2014

TS-4900 MX6 SBC

A

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She e t

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7

Cont rol U4-C

3

3.3V

RN3-C

6

i.MX6Q - CONTROL

3.3K ONOFF

NVCC_JTAG

D12 CPU_RESET# C11

2

BOOT_MODE_0

RN3-B

7

C12

POR

BOOT_MODE0

1

BOOT_MODE_1

RN3-A

8

F12

BOOT_MODE1

E12

TEST_MODE

3.3K

E11 RN4-B

2

3.3V

RN3-D 3.3K

RN4-C

3

5

G5

JTAG_TDO

G6

JTAG_TRST

C2

JTAG_MOD

H6

CLK1_N

C7

CLK1_P

D7

CPU_JTAG_TMS CPU_JTAG_TDI CPU_JTAG_TDO CPU_JTAG_TRST#

TAMPER

C137

.22 uF

7

PCIE_CLK_M PCIE_CLK_P

C138

3.3K

4

JTAG_TDI

CPU_JTAG_TCK

VDD_SNVS_IN

3.3K

JTAG_TCK H5 C3

JTAG_TMS

6

F11

PMIC_STBY_REQ

D11

PMIC_ON_REQ

CLK2_N

C5

CLK2_P

D5

XTALO

B7

XTALI

A7

.22 uF

3.3K

4

RN4-D

5

C9

RTC_XTALO

D9

RTC_XTALI

3.3K Y1

C43

24.0 MHz C45

32KHZ_1V

15 pF MX6_SINGLE_CORE_BGA624

15 pF

OFF_BD_RESET# 1 RN4-A 3.3K 8

Te chnologic Sys t e ms Tit le : Re v:

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TS-4900 A

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7

EIM

LCD

U4-A U4-D

i.MX6Q - EIM

i.MX6Q - DISP; CSI

CSI0_PIXCLK

FPGA_RESET# FPGA_DONE

N2

CSI0_VSYNC

P3

CSI0_DATA_EN CSI0_DAT4

AUD_TXD

P2

CSI0_DAT5

AUD_FRM

N4

CSI0_DAT6

AUD_RXD

N3

SPI_2_CLK

N6

CSI0_DAT7 CSI0_DAT8

SPI_2_MOSI SPI_2_MISO

N5

CSI0_DAT9

M1

CSI0_DAT10

SPI_2_CS#

M3

CSI0_DAT11

M2

CSI0_DAT12

DIO_6

L1 M4

CSI0_DAT13 CSI0_DAT14

M5

CSI0_DAT15

FPGA_SPI_CS#

L4

CSI0_DAT16

UART4_CTS#

L3

CSI0_DAT17

M6

CSI0_DAT18

L6

CSI0_DAT19

DI0_PIN4

P25

ETH_PHY_RESET

DI0_PIN15

N21

LCD_DE

CSI_D2M

E2

CSI_D2P

F2 F1

NVCC_MIPI

E1

CSI_D3M CSI_D3P

R80 D4

EN_USB_5V

EIM_A17

G24

OFF_BD_RESET#

EIM_A18

J22

DIO_14

EIM_A19

G25

EN_LCD_3.3V

EIM_A20

H22

EIM_A21

H23

DIO_16 DIO_12

P21

LCD_D03

DISP0_DAT4

P20

LCD_D04

EIM_A22

F24

DIO_18

DISP0_DAT5

R25

LCD_D05

EIM_A23

J21

DIO_19

DISP0_DAT6

R23

LCD_D06

EIM_A24

F25

DIO_20

DISP0_DAT7

R24

LCD_D07

H19

R22

LCD_D08

EIM_A25

DISP0_DAT8 DISP0_DAT9

T25

LCD_D09

EIM_D16

C25

SPI_1_CLK

F21

SPI_1_MISO

DISP0_DAT10

R21

LCD_D10

EIM_D17

DISP0_DAT11

T23

LCD_D11

EIM_D18

D24

SPI_1_MOSI

DISP0_DAT12

T24

LCD_D12

EIM_D19

G21

SPI_1_CS1#

DISP0_DAT13

R20

LCD_D13

EIM_D20

G20

DISP0_DAT14

U25

LCD_D14

EIM_D21

H20

DISP0_DAT15

T22

LCD_D15

EIM_D22

E23

LCD_D16

EIM_D23

D25

EIM_D24

F22

UART3_TXD

EIM_D25

G22

UART3_RXD

EIM_D26

E24

EIM_D27

E25

I2C_1_CLK

EIM_D28

G23

I2C_1_DAT

T21

DISP0_DAT17

U24

LCD_D17

DISP0_DAT18

V25

LCD_D18

DISP0_DAT19

U23

LCD_D19

DISP0_DAT20

U22

LCD_D20

DISP0_DAT21

T20

LCD_D21 LCD_D22

EIM_D29

J19

LCD_D23

EIM_D30

J20

EIM_D31

H21

EIM_EB2

E22

EIM_EB3

F23

LCD_D[00: 23]

EIM_BCLK N22 M25

DSI_CLK0M H3 DSI_CLK0P H4

EIM_WAIT

DSI_D0M G2 DSI_D0P G1 DSI_D1M H2 DSI_D1P H1 R81 DSI_REXT

G4 6.04K

MX6_SINGLE_CORE_BGA624

H25

DISP0_DAT3

CSI_REXT

6.04K

EIM_A16

DISP0_DAT2

W24

CSI_D1P

BUS_CS# GREEN_LED#

LCD_D02

DISP0_DAT23

CSI_D1M

J23

P23

DISP0_DAT22

D2

EIM_CS1

DISP0_DAT1

CSI_CLK0P

D1

EIM_CS0

LCD_D01

CSI_CLK0M

CSI_D0P

BUS_DIR

H24

P22

F3

E3

K20

LCD_D00

V24

CSI_D0M

EIM_RW

P24

F4

E4

BUS_ALE# DIO_15

DISP0_DAT0

DISP0_DAT16

NVCC_MIPI

DIO_0

NVCC_LCD

N1

NVCC_CSI

AUD_CLK

LCD_VSYNC

NVCC_EIM1

CSI0_MCLK

P1

DI0_PIN3

N20

EIM_LBA K22 EIM_OE J24

NVCC_EIM0

P4

DIO_9

LCD_CLK LCD_HSYNC

NVCC_EIM2

DIO_8

DI0_DISP_CLK N19 DI0_PIN2 N25

SPI BOOT

BUS_BHE#

DIO_13 BUS_WAIT#

EIM_EB0

K21

EN_SD_POWER#

EIM_EB1

K23

DIO_10

EIM_DA0

L20

MUX_AD_00

EIM_DA1

J25

MUX_AD_01

EIM_DA2

L21

MUX_AD_02

EIM_DA3

K24

MUX_AD_03

EIM_DA4

L22

MUX_AD_04

EIM_DA5

L23

MUX_AD_05

EIM_DA6

K25

MUX_AD_06

EIM_DA7

L25

MUX_AD_07

EIM_DA8

L24

MUX_AD_08

EIM_DA9

M21

MUX_AD_09

EIM_DA10

M22

MUX_AD_10

EIM_DA11

M20

MUX_AD_11

EIM_DA12

M24

MUX_AD_12

EIM_DA13

M23

MUX_AD_13

EIM_DA14

N23

MUX_AD_14

EIM_DA15

N24

MUX_AD_15

MUX_AD_[00: 15]

MX6_SINGLE_CORE_BGA624

Te chnologic Sys t e ms Tit le : Re v:

Da t e Ma y 21, 2014

TS-4900 LCD s igna ls A

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7

Micro SD Ca rd Socke t 1

3

G

S

2 3.3V

D

Q3

1

R30 36.5K

RN2-A

8

3.3K CN3 C160

EN_SD_POWER# SD2_D0 SD2_D1 SD2_D2 SD2_D3

SD2_CMD

7 8 1 2

3

DATA_0

VDD

DATA_1 DATA_2 GND

5

6

DATA_3 FRM1 COMMAND FRM2

SD2_CLK

4

CLK

FRM3 FRM4

9 10 11 12

CONN_MICRO_SD

e MMC 4GB U3

K2

SD3_D0

DATA_0

VCC VCC

N2

SD3_D1

K3

SD3_D2

N3

SD3_D3

DATA_1

VCC VCC

DATA_2 DATA_3

VCC VCC VCC

N8 K8 N9 K9

DATA_4

VCC

DATA_5

VCCQ VCCQ

DATA_6 DATA_7

VCCQ VCCQ VCCQ VCCQ

P5

SD3_CMD

P6

SD3_CLK

M5

EMMC_RESET#

COMMAND

VCCQ VCCQ

CLK

RESET#

GND GND

Gre e nlia nt E3 E2

PD#

PU

WP#

PU

GND GND GND GND GND

D2 D4 D3

SCI_IN

GND GND

SCI_OUT SCI_CLK

GND GND GND

E4

GND VDD_I

GND GND

C218 10 uF

GND

F2

3.3V

F3 F4 F5

C104 .22 uF

C103 .22 uF

C102 .22 uF

C101 .22 uF

C100 .22 uF

C51 10 nF

F6 F7 F8 F9 H3 H8 L2 L4 L7 L9 P3 P8

G2 G3 G4 G5 G6 G7 G8 G9 H2 H9 L3 L8 M4 M7 P2 P9

EMMC_MICRON_4GB_BG100

Te chnologic Sys t e ms

Da t e

Tit le :

TS-4900 SD ca rd, e MMC

Re v:

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De s igne r

Ma y 21, 2014

She e t

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of 7

SPI Boot Fla s h U18 6

SPI_1_CLK

5

SPI_1_MOSI

2

SPI_1_MISO

3

3.3V

7 R68 1

SPI_1_CS1#

CLK

8

VCC

3.3V

DIN_DQ0

C184 .22 uF

DOUT_DQ1 WP# _DQ2 HOLD# _DQ3

4

GND CS#

402 FLASH_N25Q064_8MB_SOIC

SPI_FLASH_CS#

64 byt e s of OTP

SATA U4-F

1.2V VDD_SOC_CAP

i.MX6Q - SATA C367 .1 uF G13

VDD_HIGH_CAP

2.5V

G12

SATA_VP

SATA_RXP B14 SATA_RXM A14

SATA_RX_P

SATA_TXM B12 SATA_TXP A12

SATA_TX_M

SATA_RX_M

SATA_TX_P

SATA_VPH SATA_REXT

C14

C368 .1 uF MX6_SINGLE_CORE_BGA624

R44 200

Te chnologic Sys t e ms Tit le :

TS-4900 Fla s h, SATA

Re v:

A

De s igne r

Da t e

Ma y 21, 2014

She e t

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of 7

iCE40 FPGA H3

I2C_1_DAT

C1

I2C_1_CLK

J12 E12

J3

UART2_CTS#

P4

UART4_CTS#

M7 C7

IO_B3

IO_B0

IO_B3

IO_B0

IO_B1

IO_B0

IO_B1

IO_B0

P2 N1

UART2_RXD

M1

UART4_TXD

P1

UART4_RXD

IO_B0 IO_B2 IO_B0 IO_B2 IO_B0 IO_B0

P8 H1

PUSH_SW#

F4

P3 K12 L6

E3 C12

BT_EN

J6

C5

IO_B3 VCC_B3 IO_B3 VCC_B3 IO_B3 VCC_B3 IO_B3

1.8V

A1

Ba nk 0

BT_TXD

A3

M5

VCC_B2

IO_B2 IO_B1

BT_RTS

A7

F9

BT_CTS

H14

IO_B3

IO_B0

IO_B3

IO_B0

IO_B2

IO_B0

C4

A8

1.8V

F6

C9

VCC_B1

IO_B1

VCC_B1

IO_B1

IO_B1/ GB

VCC_B0

D11

IO_B1 IO_B1

D9

L11

SPI_VCC

K11 M3 L9

IO_B1

IO_B3/ GB IO_B0 IO_B3

H4 N14 F3

1.2V

IO_B0 IO_B2 IO_B0

C10

IO_B1

D4

D7

IO_B1 1

6

A10

IO_B1

IO_B2 2

Silicon

IO_B1 IO_B2

4

IO_B1/ GB

5

3

A14

IO_B2

IO_B0

IO_B1

IO_B0

IO_B2

IO_B0

IO_B2

IO_B0

DIODE_MMBD4448_SOT363

D10

VPP_2V5 IO_B1

C118 .22 uF

IO_B3

C6

IO_B3

A4

C372 .1 uF

C373 .1 uF

C374 .1 uF

C375 .1 uF

L4 R36 1.2K

R39 1.2K

G3 K4 L5

IO_B3 IO_B1 IO_B0

IO_B3

IO_B0/ GB

IO_B1

IO_B0

IO_B3

C11

F8

1.2V

A6

G6

A12

H9

IO_B2

IO_B1

IO_B3

IO_B1

IO_B3

IO_B1

IO_B2

IO_B3

J7

J11

VCC_CORE VCC_CORE

P11 M11

SPI_2_MISO

P12

SPI_2_CLK

P13

FPGA_SPI_CS#

IO_B3/ GB

C143 .22 uF

C152 .22 uF

C376 .1 uF

C377 .1 uF

C378 .1 uF

C379 .1 uF

L10

FPGA_RESET#

K14

CN2-54

VCC_CORE

IO_B1 IO_B1

NC

H11

A13

G4

M8

C204 10 uF

SPI_SI

IO_B2

VPP_FAST

G12 F12 D12

CN2-78 CN2-80 CN2-86 CN2-88

C14 D14 E14 F14

CN2-94 CN2-96 CN2-98 CN2-100

B1 P14 D4 L1

FPGA_IRQ

IO_B3

C381 .1 uF

IO_B2 IO_B1 IO_B1

L7

SPI_CLK

P10 E4 P7

REBOOT

G1

B14 E11 M9 D3

PLL_VCC_0

SPI_SO

SPI_SS#

G14

R37 1.2K

K3 M6 L12 F11

PLL_GND_0

Config PLL_VCC_1

M10

H12

VCC_CORE

3.3V FPGA_DONE

M12

VCC_CORE

R42 75

G11

IO_B2/ GB

IO_B3 SPI_2_MOSI

M4

D5

J4 C371 .1 uF

MUX_AD_15

D6

IO_B2 L14

CN1-87

Ba nk 0

IO_B2/ GB

IO_B3 P5

C3

VCC_B0

C380 .1 uF

3.3V

FPGA_24MHZ_CLK

J1

CN1-63 CN1-67

VCC_B2

BT_RXD

A2

D1 E1

IO_B3

IO_B0 L8

K1

3.3V

IO_B2

IO_B0 P9

WL_EN

A5

J9

IO_B3

IO_B0/ GB UART2_TXD

A11

C8

1.2V

U17

C_DONE C_RESET#

LATTICE_ICE40_4KLUT_CS132

4 3

M14

RN5-D 3.3K

2 RN5-C 3.3K

RN5-B 3.3K

NC PLL_GND_1

5

GND

1

6 RN5-A 3.3K

7

J14

GND A9

GND F1

GND F7

GND G7

GND G8

GND G9

GND H6

GND H7

GND H8

GND J8

GND L3

D8

GND P6

8 3.3V

All pins ha ve prog. PU re s is t or Schmit t Trig. on a ll Input s 10 MHz min clock for PLL No Int e rna l clock

Te chnologic Sys t e ms Tit le :

TS-4900 iCE40 FPGA

Re v:

A

De s igne r

Da t e

Ma y 21, 2014

She e t

6

of 7

Two 100-pin Off-boa rd Conne ct ors Mus t ha ve 10 nF Ca pa cit or

All signals driving DIO on CN1 &

EXT_RESET# is a n Input us e d t o re boot t he CPU Do not drive a ct ive high

Le ft

for a ll "quie t " s igna ls

3.3V on CN2, or remain at 0V until the CN2 3.3V rail is > 3.0V

"5V" pins s upply a ll powe r t o t he module Apply 4.5V t o 5.5V t o t he s e pins

ve ry ne a r CN2 a nd GND

! CN2 must be powered by the

(be t we e n diff pa irs )

Right

(us e ope n dra in)

CN1

OFF_BD_RESET# is a n Out put

LCD_D09 LCD_D10 LCD_D11 LCD_D12 5V LCD_D13 C146 .22 uF

C148 .22 uF

LCD_D14 LCD_D15 LCD_D16 LCD_D17 LCD_D18 LCD_D19 LCD_D20 5V LCD_CLK LCD_HSYNC LCD_VSYNC LCD_DE LCD_PWM SPI_FLASH_CS# SPI_1_CS1# CN1-63 DIO_10 CN1-67 CAN_2_RXD CAN_2_TXD PUSH_SW# DIO_12 DIO_13 DIO_14 DIO_15 DIO_16 CN1-87 DIO_18 DIO_19 DIO_20 BUS_WAIT# BUS_BHE#

2

3

4

5

6

7

8

EXT_RESET#

MDI_0_P MDI_0_M

EN_USB_5V SD2_D2

Giga bit Et he rne t

SD2_D3

9

10

NC NC

12

13

14

15

16

NC

17

18

19

20

21

22

23

24

25

26

27

28

29

30

31

32

33

34

35

36

37

38

39

40

41

42

43

44

45

46

47

48

49

50

51

52

53

54

55

56

57

58

59

60

61

62

63

64

65

66

MUX_AD_14

67

68

MUX_AD_13

69

70

MUX_AD_12

71

72

MUX_AD_11

73

74

MUX_AD_10

75

76

MUX_AD_09

77

78

MUX_AD_08

79

80

MUX_AD_07

81

82

MUX_AD_06

83

84

MUX_AD_05

85

86

87

5V LCD_D08

1

11

OFF_BD_RESET#

us e d t o re s e t a ll pe riphe ra ls

CN2

ETH_CT MDI_1_P

1

2

3

4

5

6

7

8

ETH_ACT_LED ETH_LINK_LED RED_LED# GREEN_LED#

9

10

11

12

13

14

15

16

MDI_2_P

17

18

MDI_2_M

19

20

21

22

MDI_3_P

23

24

MDI_3_M

25

26

27

28

29

30

31

32

33

34

35

36

37

38

39

40

41

42

43

44

45

46

47

48

49

50

51

52

53

54

55

56

57

58

59

60

61

62

63

64

65

66

67

68

69

70

71

72

73

74

75

76

77

78

79

80

81

82

83

84

MUX_AD_04

85

86

88

MUX_AD_03

87

88

89

90

MUX_AD_02

89

90

91

92

MUX_AD_01

91

92

93

94

MUX_AD_00

93

94

95

96

95

96

97

98

97

98

99

100

99

100

Off-Bd SD Ca rd

SD2_CMD 3.3V SD2_CLK 5V

MDI_1_M ETH_CT 3.3V

3.3V ra il ca n s upply up

SD2_D0 SD2_D1

SD ca rd s igna ls on conne ct or

t o 700 mA t o ba s e boa rd

a re wire d in pa ra lle l wit h

LCD_D00 LCD_D01

SD ca rd s ocke t . Only one

LCD_D02

ca n be popula t e d wit h SD ca rd

LCD_D03

HOST_USB_M

USB Port s

LCD_D04 LCD_D05 V_BAT

HOST_USB_P 1.2V USB_OTG_M USB_OTG_P

LCD_D06 3.3V

LCD_D07 LCD_D21 LCD_D22

CPU_JTAG_TRST#

C52 10 nF

LCD_D23 EN_LCD_3.3V

PCIE_TX_P PCIE_TX_M

BOOT_MODE_0 BOOT_MODE_1

PCIE_RX_M

SPI_1_MISO SPI_1_MOSI

PCIE_RX_P DDR_1.5V

SPI_1_CLK

PCIE_CLK_P C53 10 nF

MUX_AD_15

PCIE_CLK_M 1.8V

SPI or DIO

SPI_2_CS# SPI_2_MOSI SPI_2_MISO SPI_2_CLK SATA_RX_M

Da t a Bus

SATA_RX_P

CPU JTAG Vcc

or DIO

BUS_ALE# BUS_DIR

SATA_TX_P

Cons ole CAN

BUS_CS#

3.3V SATA_TX_M

UART1_TXD UART1_RXD CAN_1_TXD CAN_1_RXD

I2C_2_CLK I2C_2_DAT AUD_MCLK AUD_CLK AUD_FRM AUD_TXD

I2C I2S or DIO

AUD_RXD CPU_JTAG_TMS CPU_JTAG_TCK

CPU JTAG

CPU_JTAG_TDI CPU_JTAG_TDO

CN2-54 Code c CLK on t he TS-8390

DIO_0 CN2-54 DIO_1 DIO_2 DIO_3 DIO_4 DIO_5 DIO_6 DIO_7 DIO_8 DIO_9 USB_OTG_ID USB_OTG_VBUS CN2-78 CN2-80 UART3_TXD UART3_RXD CN2-86 CN2-88 UART5_TXD

Se ria l Port s

UART5_RXD

or DIO

CN2-94 CN2-96 CN2-98 CN2-100

MUX_AD_[00: 15] TYCO_100PIN_SBC

TYCO_100PIN_SBC

Bus Cont rol CN1-Pin 67 = UART0 TXEN

ETH_CT

If Bus is not ne e de d, a ll Bus C115 .22 uF

s igna ls ca n be cha nge d t o DIO

ne a r CN2-5,11

De vice s conne ct e d t o t his bus mus t ne ve r drive it whe n BUS_CS# is de a s s e rt e d (mus t be off wit hin 30 nS of de a s s e rt ion)

De vice s mus t pull t he BUS_WAIT# line low if t he y ne e d more t ha n 150 nS s t robe

The da t a bus ca n not ha ve more t ha n 30 pF of off-boa rd ca pa cit ive loa ding Ma y ne e d da t a buffe r chip for he a vy loa ds

Te chnologic Sys t e ms Tit le : Re v:

Da t e Ma y 21, 2014

TS-4900 Off-boa rd Conne ct ors A

De s igne r

She e t

7

of

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