MIT International Journal of Electrical and Instrumentation Engineering Vol. 4, No. 2, August 2014, pp. 69-80 ISSN 2230-7656 ©MIT Publications

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Performance Investigation of SVPWM Controlled Diode Clamped and Flying Capacitor Multilevel Converters Vikas Shukla Member, IEEE Dept of EE, KNIT, Sultanpur [email protected]

S. P. Singh Member, IEEE Dept of EE, KNIT, Sultanpur [email protected]

A. K. Gautam Student Member, IEEE Dept of EE, KNIT, Sultanpur [email protected]

Vipul Agarwal Dept of EE, MIT Moradabad [email protected]

ABSTRACT

load, increase in load and decrease in load. The analysis is also performed for source perturbation like Increase & decrease up in output voltage without use of transformer. Due to power electronic switches used in conversion process vulnerability of power system is increased and results in different power quality issues power factor, Harmonics injection in supply and

this paper perform transformer less boosting, conversion and less vulnerability to power quality. Index Terms:

INTRODUCTION The era of high power converters and Medium voltage (MV) drives evolved in mid 1980s when 4500 volt Gate Turn off Thyristor (GTO) became commercially available. They have the drawback of poor power quality in terms of injection of current harmonics, resultant voltage waveform distortion and poor power factor at input ac supply. Also slowly varying

: Multilevel converters present great advantages compared with conventional and very well-known two-level converters. These advantages are fundamentally focused on improvements in the output signal quality and a nominal power increase in the converter. The power converter output voltage improves its quality as the number of

levels increases reducing the total harmonic distortion (THD) of the output waveforms. These properties make multilevel converters very attractive and researchers are spending great efforts trying to improve multiand the performance of different optimization algorithms in order to enhance the THD of the output signals, and the ripple of the currents. For instance, nowadays researchers are focused on the harmonic elimination using pre-calculated switching the development of new multilevel converter topologies (hybrid or new ones), and new control strategies. Also conversion of 3 phase ac to dc, line side voltage and current waveforms are getting polluted with conventional pulses schemes like 12, 24, 48..... Pulse convertors as shown in Fig. 1. So multilevel converters are showing much effectiveness in this area with new control technique.

MIT International Journal of Electrical and Instrumentation Engineering Vol. 4, No. 2, August 2014, pp. 69-80 ISSN 2230-7656 ©MIT Publications

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Fig. 1: Block diagram representation of a multilevel converter

DIODE CLAMPED AND FLYING CAPACITOR MULTILEVEL CONVERTERS

Fig.3: A 4-Level Flying Capacitor Multilevel Converter

The drawbacks of the two-level converters are the high voltage stress across the devices, large passive components and hence due to the inherent advantages of the three-level Diode Clamped converters were proposed to draw the sinusoidal line currents in phase with mains voltage. And improving the waveform quality and reducing voltage stress on the power devices. The voltage stress on the open power devices is constrained by clamping capacitors.

SVPWM CONTROL TECHNIQUE FOR DIODE CLAMPED AND FLYING CAPACITOR A standard Space vector PWM has been used for three-phase Diode clamped and Flying capacitor multilevel converters. The basic principle of operation of a Converter employing SVPWM technique block diagram is shown below.

Fig. 4: Control Scheme of Multilevel converter in two-frame of references

Fig. 2: A 4-level Diode Clamped Multilevel Converter

this topology capacitor are not shared among different legs of the converter; each phase has its own set of capacitors. Regulation of capacitor voltages is possible without using an external circuit regardless of the number of levels of the converter. This is one of the advantages of this topology. Because the voltage of the outer capacitors is higher than the inner ones, several capacitors need to be connected in a series to reach to the required voltage (the tolerable voltage for each capacitor bank). Therefore, the number of capacitors drastically increases when the number of voltage levels increases. Furthermore, the number of capacitors is proportional to the number of phases of the converter. This is one of the primary drawbacks of this topology.

This scheme involves 3-basic actions performed by system as for switching operation and ride through from any abnormal operation.

Transformation Stage minals of three phase ac supply through source inductance. The input three phase supply voltage can be written as, Va =

Vb =

Vb =

…(1)

MIT International Journal of Electrical and Instrumentation Engineering Vol. 4, No. 2, August 2014, pp. 69-80 ISSN 2230-7656 ©MIT Publications

Where Vm is peak phase voltage of supply and frequency of source.

is angular

For the diode clamped three level converters, line to ground voltages can be derived from switching states Sa , Sb, Sc. If the converter is connected to a balanced three phase source, corresponding phase voltages can be derived from line to ground voltages using (2). Then these phase voltages are transformed into the reference frame by (3) and the resultant coordinates for the vectors in sector can be computed. This can implemented using Clarke’s function and easily applied using MATLAB em-

=

...(2)

=

…(3)

.

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. . …(5)

.

. .

Where is angular frequency of three - phase voltage and vd, v´d , id and vq, v´q , iq are components of v, v´ , id and is is in d and q axis respectively. Here both equations depict behavior of id and iq can be controlled using voltages vd and vq

0

Concept of Space vector calculation The space vector diagram with equivalent circuit representation

Fig.6: Space vector diagram for all switching states in three phase converters

…(4)

This equation can be expressed in a rotating reference frame (d-q), with the d-axis oriented in the direction of source voltage vector v as shown in Fig. 5. Fig.7: One sector of space vectors representation with time of switching

It is to be emphasized that this method only controls the total DC bus voltage. The current controllers deliver the reference values for voltages in d and q frame of reference. By using coordinates frame transformation, we obtain v* and v* in stationary frame of reference. The voltages v* and v* are used to derive the reference command input v* and its angle . These are now fed to space vector modulator and used for generation of control pulses for 12 semiconductor switches.

Fig. 5: Vector diagram of multilevel converter in two frame of references

The equation can be written as below

All 27 possible conduction states of NPC or Flying capacitor multilevel converter produce 19 different space vectors. The complex plane can be subdivision of 6 sectors and 24 triangles triangle can be formed using voltage components v0 , v7 and v9. Also it is assumed command voltage vector v* will reside in

MIT International Journal of Electrical and Instrumentation Engineering Vol. 4, No. 2, August 2014, pp. 69-80 ISSN 2230-7656 ©MIT Publications

region R1 when following equations of (4.6) and (4.7). V1 Ta Ta

8

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For comparison of two dif-

Tb + V2 Tc = V* Tsamp/2

…(6)

+ Tc = Tsamp/2 b

…(7)

Where V1, V2 and V8 are corner voltage triangles of selected region. Respective time intervals are represented as Ta , Tb and Tc whether Tsamp is sampling time of these vectors.

parameter which helps at time of different cases as preset indicators and responses in a manner of ease in comparison. So for this objective few parameters named as Source side and Load side in disturbed and without any disturbance. Table I System Parameters

region one as a reference then we can obtain analytical time expression for time intervals Ta, Tb and Tc.

System Parameters Input Side Parameters mH DC Bus capacitors C1 = C2 = 4700 F

…(8)

Region 1:

mH

Chopping Frequency of Switches=5000 Hz DC Bus voltage (Reference)=3000 volts

SIMULATION RESULTS OF DIODE CLAMPED MULTILEVEL CONVERTER

…(9)

Region 2:

load

5mH and 1000 volt ac (rms). Also no variation is applied in source voltage. Then the performance evaluation of Diode clamped converter is performed. Region 3:

…(10)

Fig. 8: Output voltage waveform

Region 4:

…(11)

As shown in Fig.8.The peak overshoot is 320 volts and start to settle after peak value. At time t=0.6 sec it completely settled down to reference.

Where is command vector angle, modulation index m = 2/ , (V*/V0), V* command voltage vector and V0 is dc bus voltage of converter. In similar fashion two other region time vectors can be calculated.

SIMULATION RESULTS AND DISCUSSIONS A MATLAB/SIMULINK model is developed to investigate the performance comparison of PI based SVPWM controlled Flying capacitor and Diode clamped converters. The performance is analyzed for different cases in which changes in load done.

Fig. 9: Waveform of source voltage and current

As shown in Fig. 9. Waveforms are depicted from source side current and phase angle no lagging operation is visualized. And waveform is having little distortion.

MIT International Journal of Electrical and Instrumentation Engineering Vol. 4, No. 2, August 2014, pp. 69-80 ISSN 2230-7656 ©MIT Publications

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As shown in Fig.15 load is suddenly increased at t=1 sec. The dip in output supply voltage of 240 volt and settled down at time t = 1.8 sec

Fig.10: Voltage across upper capacitor

As shown in the Fig.10. Vc1 Is crossing and swinging over 1500 volts. The same property is showing by Fig.11.

Fig. 16: Waveforms of source voltage and current for sudden Increase in Load

As shown in Fig.16 source voltage and current Waveforms are depicted from source side current and phase angle no lagging operation is visualized.

Fig.11: Voltage across lower capacitor

Fig. 17: Voltage across upper capacitor

which crossing and swinging over 1500 volts are. The same property is showing by Fig.18. Fig.12: Voltage difference across capacitors,

Vc = Vc1 – Vc2

Fig. 18: Voltage across lower capacitor

Fig. 13: Harmonic spectrum of source current

: denly increased at t=1 sec. In this condition the performance and behavior of Diode Clamped Converter is analyzed with such change in load.

Fig. 15: Output Voltage waveform for Sudden Increase in Load

Fig. 19: Voltage difference across capacitors,

Vc = Vc1 – Vc2 Fig.19 shows Voltage difference across capacitors, which is range of 8 volts. Fig. 20 shows the power factor of supply which is approximate to unity.

Fig. 20: Power Factor of source

MIT International Journal of Electrical and Instrumentation Engineering Vol. 4, No. 2, August 2014, pp. 69-80 ISSN 2230-7656 ©MIT Publications

denly decreased at t=1 sec. In this condition the performance and behaviour of Diode Clamped Converter is analyzed with such change in load.

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Vc = Vc1 – Vc2 Fig. 25 shows Voltage difference across capacitor which are of range 7 volts.

Fig. 26: Power Factor of system Fig.21: Output Voltage Waveform during Sudden Decrease in Load

Fig. 26 shows the power factor of supply which is approximate to unity.

As shown in Fig.21. Load is suddenly decreased at (t=1) sec. The rise in output supply voltage of 220 volt and settled down at time (t = 1.5) sec.

Fig. 27: Harmonic analysis of source current Fig. 22: Waveform of source voltage and current for sudden Load Decrease

voltage

The analysis is performed with three phase ac source on line side of rating 1100 volt (rms) value on frequency of 50 Hz. In this no transient condition is examined. The increase in voltage is of 10% and for this case the analysis is carried out. Fig. 23: Voltage across upper capacitor

Fig. 28: Output voltage waveform for increase in Source Voltage Fig. 24: Voltage across lower capacitor

As shown in Fig. 28 the output waveform of DC supply is with

which is crossing and swinging over 1500 volts. The same property is showing by Fig. 24.

voltage is done. The peak overshoot is 250 volts and start to settle after peak value. At time t = 2.4 sec it completely settled down to reference.

Fig. 25: Voltage difference across capacitors,

Fig. 29: Waveform of source voltage and current for increase in source voltage

MIT International Journal of Electrical and Instrumentation Engineering Vol. 4, No. 2, August 2014, pp. 69-80 ISSN 2230-7656 ©MIT Publications

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As shown in Fig. 29 Waveform are depicted from source side current and phase angle no lagging operation is visualized. Also waveform is having little distortion.

Fig. 35: Waveform of source voltage and current for Decrease in source voltage Fig. 30: Voltage across upper capacitor

As shown in Fig. 34 the output waveform of DC supply is with overshoot is 400 volts and start to settle after peak value. At time t = 0.9 sec it completely settled down to reference.

Fig. 31: Voltage across lower capacitor

As shown in the Fig. 30 voltage across upper capacitor is shown which is crossing and swinging over 1500 volts. The same property is showing by Fig. 31.

Fig. 32: Voltage difference across capacitors,

Fig. 32 shows Voltage difference across capacitors, which are of range 10 volts.

Fig. 36: Voltage across upper capacitor

Fig. 37: Voltage across lower capacitor

As shown in the Fig. 36 voltage across upper capacitor is shown which is crossing and swinging over 1500 volts. The same property is showing by Fig. 37.

Fig. 33: Power Factor of source

Fig. 33 shows the power factor of supply which is approximate to unity. Fig. 38: Voltage difference across capacitors,

Supply voltage is decreased to 900 volt and in this condition the performance and behaviour of controller is analyzed with such reduction in source voltage.

Fig. 38 shows Voltage difference across capacitors, which are of range 7 volts.

Fig. 39: Power Factor of source Fig. 34: Output voltage waveform for decrease in Source Voltage

Fig. 39 shows the power factor of supply which is approximate to unity.

MIT International Journal of Electrical and Instrumentation Engineering Vol. 4, No. 2, August 2014, pp. 69-80 ISSN 2230-7656 ©MIT Publications

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Fig. 40: Harmonic analysis of source current during load disturbance Fig. 44: Voltage across upper capacitor

Fig. 41: Switching stress across a switch

Fig. 41 shows the switching stress across a switch during its operation and showing peak value of voltage across it as 1600 volts. This voltage is of intermittent nature because of switch getting regularly turning On and Off.

SIMULATION RESULT OF FLYING CAPACITOR MULTILEVEL CONVERTER load

Fig. 45: Voltage across lower capacitor

As shown in the Fig. 44 voltage across capacitor one Vc1 is shown which is crossing and swinging over 1500 volts. The same property is showing by Fig.45 Fig. 46 shows Voltage difference across capacitors which are of range 7 volts

variation is applied in source voltage. Then the performance

Fig. 42: Output voltage waveform

As shown in Fig.42. The peak overshoot is not found and start to settle after peak value. At time t = 0.4 sec it completely settled down to reference.

Fig. 46: Voltage difference across capacitors

Fig. 43: Waveform of source voltage and current

As shown in Fig. 43, Waveform are depicted from source side current and phase angle no lagging operation is visualized. Also waveform is having little distortion.

Fig. 47: Power Factor of Source. Fig. 47: shows the power factor of supply which is approximate to unity.

MIT International Journal of Electrical and Instrumentation Engineering Vol. 4, No. 2, August 2014, pp. 69-80 ISSN 2230-7656 ©MIT Publications

Fig. 48 Harmonic analysis of source current

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Fig. 51: Voltage across lower capacitor

Fig. 50 and Fig. 51 shows the balancing of capacitor voltage which is of variable in nature. Whenever a capacitor voltage is increasing other voltage is getting decreased. suddenly increased at t=1 sec. In this condition the performance and behaviour of Flying Capacitor Converter is analyzed with such change in load.

Fig. 52: Voltage difference across capacitors,

Fig. 52 shows Voltage difference across capacitors which are of range 8 volts. Fig. 48: Output Voltage waveform for Sudden increase in Load

Fig. 53: Power Factor of source

Fig. 49: Waveform of source voltage and current for sudden increase in Load

As shown in Fig. 48. The dip in output supply voltage of 200 volt and settled down at time (t = 1.8) sec. As shown in Fig. 48, Waveforms are depicted from source side current and phase angle no lagging operation is visualized.

Fig. 50: Voltage across upper capacitor

Fig. 53 shows the power factor of supply which is approximate to unity.

: is suddenly decreased at t=1 sec. In this condition performance and behaviour of Flying Capacitor Converter is analyzed with such change in load.

Fig. 54: Output Voltage Waveform during Sudden decrease in Load

MIT International Journal of Electrical and Instrumentation Engineering Vol. 4, No. 2, August 2014, pp. 69-80 ISSN 2230-7656 ©MIT Publications

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As shown in Fig. 54. Load is suddenly decreased at t = 1 sec. The rise in output supply voltage of 210 volt and settled down at time t=1.3sec. Due to sudden drop of load the output voltage is getting increased at time t=1sec. This supply current is suddenly sensed performed at time t=1.3 seconds and output supply is maintained at 3000 volts reference. Fig. 59: Power Factor of system

Fig. 59 shows the power factor of supply which is approximate to unity.

Fig. 55: Waveform of source voltage and current for sudden Decrease in Load Fig. 60: Harmonic analysis of source current during load disturbance

voltage

Fig. 56: Voltage across upper capacitor

and no transient condition is examined.

Fig. 61: Output voltage waveform for Increase in Source Voltage Fig. 57: Voltage across lower capacitor

Fig. 62: Waveform of source voltage and current for increase in source voltage Fig. 58: Voltage difference across capacitors

Fig. 58 shows Voltage difference across capacitors which are of range 15 volts.

done. At time (t=0.3) sec it completely settled down to reference.

MIT International Journal of Electrical and Instrumentation Engineering Vol. 4, No. 2, August 2014, pp. 69-80 ISSN 2230-7656 ©MIT Publications

Fig. 63: Voltage across upper capacitor

Fig. 64: Voltage across lower capacitor

As shown in the Fig. 63 voltage across capacitor one Vc1 is shown which is crossing and swinging over 1500 volts. The same property is showing by Fig. 64.

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Fig. 67: Output voltage waveform for decrease in Source Voltage

Fig. 68: Waveform of source voltage and current for decrease in source voltage

As shown in Fig. 67 the output waveform of DC supply is with t =0.3 sec it completely settled down to reference.

Fig. 69: Voltage across upper capacitor Fig.65: Voltage difference across capacitors,

Fig. 65 shows Voltage difference across capacitors which are of range 10 volts.

Fig. 70: Voltage across lower capacitor

As shown in the Fig. 69 voltage across capacitor one Vc1 is shown which is crossing and swinging over 1500 volts. The same property is showing by Fig. 70. Fig. 66: Power Factor of source

Fig.66 shows the power factor of supply which is approximate to unity.

Supply voltage is decreased to 900 volt and in this condition the performance and behaviour of controller is analyzed with such reduction in source voltage.

Fig. 71: Voltage difference across capacitors,

MIT International Journal of Electrical and Instrumentation Engineering Vol. 4, No. 2, August 2014, pp. 69-80 ISSN 2230-7656 ©MIT Publications

Fig.71 shows Voltage difference across capacitors which are of range 10 volts.

3.

0.15

0.4

4.

Settling time (sec)

0.7

0.4

5.

DC bus voltage Overshoot (%)

11.33

0

6.

DC bus voltage Undershoot (%) Nature of Response

10

10.1

Under damped

Over damped

7.

Peak Time (sec)

80

CONCLUSIONS Fig. 72: Power Factor of source

Fig. 72 shows the power factor of supply which is approximate to unity.

The main conclusions drawn from work which is carried out in this paper are summarizes for saliency of work: different kind of problems as reduction of life of equipment; heat up of windings, distorted waveform of source current etc. THD of line side current should also be within prescribed limit IEC standard and is about 5%-10% for both of converters. But Diode clamped converter is working in limit of 6% THD. converters are able to operate without transformer at source side for step up of voltage and then conversion to DC.

Fig. 73: Harmonic analysis of source current during load disturbance

in case of supply voltage variation.

REFERENCES 1. F.Z. Peng, J.S. Lai, J. McKeever, and J. VanCoevering, “A multilevel voltage-source converter system with balanced DC voltage,” in , 1995, pp. 1144-1150 P 2. P.G. Kamp, B. Endres, and M. Wolf, “Modular high power DC-link , converter units for power system application,” in 1997, pp. 4305-4310. 3. L.H. Walker, “10 MW GTO converter for battery peaking services,” , vol. 26, pp. 63-72, Jan./Feb. 1990.

Fig. 74: Switching stress across a switch

Fig. 74 show the switching stress across a switch during its operation and showing peak value of voltage across it as 2600 volts. This voltage is of intermittent nature because of switch getting regularly turning ON and Off of switch.

PERFORMANCE COMPARISON OF DIODE CLAMPED AND FLYING CAPACITOR MULTILEVEL CONVERTERS Performance comparison of SVPWM controlled Diode clamped

4. E.M. Berkouk and G. Manesse, “Multilevel PWM rectifiermultilevel inverter cascade application to the speed control of the , pp. 1031-1035, 1998. PMSM,” in link with independent reactive power control,” Delivery, vol. 13, pp. 902-908, July 1998. a DC power supply with frequent output short circuit,” in , vol. 2, pp. 1165-1172, 1999.

from simulation results. TABLE II: Dynamic Performance Comparison Of Both Converters Using Svpwm

7. L.M. Tolbert, F.Z. Peng, and T.G. Habetler, “Multilevel converters for large electric drives,” , vol. 35, pp. 36-44, Jan./Feb. 1999.

S. No.

Performance Parameters

1. 2.

Diode Clamped Multilevel Converter

Flying Capacitor Multilevel Converter

8. K.T. Wong, “Harmonic analysis of PWM multilevel converters,” , vol. 148, pp. 35-43, Jan. 2001.

Delay time (sec)

0.01

0.1

Rise Time (sec)

0.1

0.26

9. N. Celanovic and D. Boroyevich, “A fast space-vector modulation algorithm for multilevel three-phase converters,” Applicat., vol. 37, pp. 637-641, Mar./Apr. 2001.