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CHAPTER 8
PERFORMANCE ANALYSIS OF THREE LEVEL DIODE CLAMPED INVERTER WITH TWO LEVEL VOLTAGE SOURCE INVERTER
8.1
INTRODUCTION
An inverter is commonly used in variable speed AC motor drives to produce a variable three-phase AC output voltage from a constant DC voltage source, which has two voltage level (+VDC, -VDC). The output waveform of inverters should be sinusoidal for efficient operation. But the output of conventional two level PWM inverters would be a square wave (or) quasi square wave. The square wave is rich in harmonic content. To minimize the output voltage distortion with improved fundamental voltage, the multilevel inverter concept has been implemented. The concept of utilizing multiple small voltage levels (multilevel) to perform power conversion was patented by an MIT researcher over twenty years ago. Advantages of this multilevel approach include good power quality, good electromagnetic compatibility (EMC), low switching losses, and high voltage capability. The main disadvantages of this technique are that a larger number of switching semiconductors are required for lower-voltage systems and the small voltage steps must be supplied on the DC side either by a capacitor bank or isolated voltage sources. The first topology introduced was the series H-bridge design (Baker 1975). This was followed by the diode clamped converter which utilized a bank of series capacitors. These designs can create higher power
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quality for a given number of semiconductor devices than the fundamental topologies alone due to a multiplying effect of the number of levels.
These multilevel inverters are suitable for high voltage and high power application due to their ability to synthesize waveforms with better harmonic spectrum. Numerous topologies have been introduced and widely studied for utility and drive applications. Multilevel pulse width modulated (PWM) inverters are gaining importance due to the fact that the lower order harmonics in the output waveform can be eliminated without any increase in the higher order harmonics, unlike the regular two level PWM inverters. Multilevel inverters provide more than two voltage levels. As the number of levels reaches infinity, the output Total Harmonic Distortion (THD) approaches to zero. This inverter generates almost sinusoidal staircase voltage with only one time switching per line cycle. In this chapter the comparative performance of the three level, three phase diode clamped inverter with the conventional two level, three phase voltage source inverter was carried out for both the simulated and hardware models.
8.2
TWO LEVEL PULSE WIDTH MODULATED INVERTER
The standard three-phase voltage source inverter is shown in Figure 8.1 and the eight valid switch states are given in Table 8.1. As in single-phase VSIs, the switches of any leg of the inverter (S1 and S4, S3 and S6, or S5 and S2) cannot be switched on simultaneously because this would result in a short circuit across the DC link voltage supply. Similarly in order to avoid undefined states in the VSI, and thus undefined AC output line voltages, the switches of any leg of the inverter cannot be switched off simultaneously as this will result in voltages that will depend upon the respective line current polarity. Of the eight valid states, two of them (7 and 8 in Table 8.1) produce zero AC line voltages. In this case, the AC line currents freewheel through
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either the upper or lower components. The remaining states (l to 6 in Table 8.1) produce non-zero AC output voltages. In order to generate a given voltage waveform, the inverter moves from one state to another. Thus the resulting AC output line voltages consist of discrete values of voltages that are Vi , 0, and Vi . The selection of the states in order to generate the given waveform is done by the modulating technique that should ensure the use of only the valid states (Muhammad H. Rashid 2004).
Figure 8.1 Three phase voltage source inverter
Table 8.1 Valid switching states for three-phase VSI
Sl.No.
ON State
OFF State
State
V ab
Vbc
Vca
1.
S1, S2 and S6
S4, S5 and S3
1
Vi
0
Vi
2.
S2, S3 and S1 S5, S6 and S4
2
0
Vi
Vi
3.
S3, S4 and S2 S6, S1 and S5
3
Vi
Vi
0
4.
S4, S5 and S3 S1, S2 and S6
4
Vi
0
Vi
5.
S5, S6 and S4 S2, S3 and S1
5
0
Vi
Vi
6.
S6, S1 and S5 S3, S4 and S2
6
Vi
Vi
0
7.
S1, S3 and S5 S4, S6 and S2
7
0
0
0
8.
S4, S6 and S2 S1, S3 and S5
8
0
0
0
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8.2.1
Simulation of Two Level PWM Three Phase Inverter
The IGBT based three-phase two level inverter is simulated using PSpice with sinusoidal modulation and it is shown in Figure 8.2. The inverter circuit has the following specifications: Input voltage =230V DC, Output voltage = 230V, 50Hz, three phase AC and load resistance = 360Ω per phase and its output line voltage waveform is shown in Figure 8.3. It may not be possible to reduce the overall voltage distortion due to harmonics but by proper switching control the magnitudes of lower order harmonic voltages can be reduced, often at the cost of increasing the magnitudes of higher order harmonic voltages. Such a situation is acceptable in most cases as the harmonic voltages of higher frequencies can be satisfactorily filtered using lower sizes of filter chokes and capacitors. Many of the loads, like motor loads have an inherent quality to suppress high frequency harmonic currents and hence an external filter may not be necessary. Unlike in square wave inverters the switches of PWM inverters are turned on and off at significantly higher frequencies than the fundamental frequency of the output voltage waveform. Figure 8.4 shows the harmonic spectrum for simulation of threephase two level inverter.
Figure 8.2 PSpice model of three-phase two level inverter
Figure 8.3 Output line voltage waveforms for three-phase two level inverter 243
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Figure 8.4 Harmonic spectrum for three-phase two level inverter 8.2.2
Hardware Model of Two Level Inverter The hardware model is implemented for the three-phase two level
inverter using TMS 320LF2407 DSP processor for the same specifications mentioned in the previous section. The DSP processor is used to generate the gating signals. The hardware model is tested for a three-phase resistive load (360 ohms in each phase) and the test setup is shown in Figure 8.5. The results are recorded by using a fluke 434-power quality analyzer. The output line– line voltage waveform is shown in Figure 8.6. The harmonic spectrum of the output line–line voltage and individual harmonic distortion levels are shown in Figures 8.7 and 8.8 respectively. The comparison between the simulation results and hardware results are shown in Table 8.2.
Figure 8.5 Hardware test setup of two level inverter
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Figure 8.6 Output line-line voltage waveforms
Figure 8.7 Harmonic spectrum of the line – line voltage waveforms
Figure 8.8 Percentage harmonic distortion of individual harmonic levels
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Table 8.2
Comparative analysis of % harmonic distortion of output voltage waveform in both simulated and hardware results
Sl.No. Harmonic order
Harmonic Content Simulation (%) Hardware (%) 100.00 100
1
Fundamental
2 3 4 5 6 7 8
3 5 7 9 11 13 15
0.06 17.74 4.23 0.02 2.11 1.97 0.04
1.1 17.0 3.6 0.2 0.6 0.5 0.6
9 10 11 12
17 19 21 23
3.4 1.77 0.02 1.56
1.2 0.4 0.3 0.3
18.87
18.3
% THD
8.3
THREE
LEVEL
DIODE
CLAMPED
MULTI
LEVEL
INVERTER Recently the “multilevel inverter” has drawn tremendous interest in the power industry (Peng and Lai 1996). The general structure of the multilevel inverter is to synthesize a sinusoidal voltage from several levels of DC voltage sources, typically obtained from DC-bus capacitor/voltage sources. A three-level inverter, also known as a neutral-clamped inverter, which consists of two capacitor voltages in series and uses the center tap as the neutral. Each phase leg of the three-level converter has two pairs of switching devices in series. The center of each device pair is clamped to the neutral through clamping diodes. The waveform obtained from a three-level inverter is a quasi-square wave output.
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The diode clamp method can be applied to higher-level inverters. As the number of levels increases, the synthesized output waveform adds more steps, producing a staircase wave which approaches the sinusoidal wave with minimum harmonic distortion. Ultimately, a zero harmonic distortion of the output wave can be obtained by an infinite number of levels (Jih-Sheng Lai and Fang Zheng Peng 1996).
In three level inverters, the switching of the upper and lower devices in a half-bridge inverter generates a Va 0 wave with positive and negative levels ( 0.5Vd and 0.5V d ), respectively. If the fundamental output voltage and corresponding power level of the PWM inverter are to be increased to a high value, the DC link voltage Vd must be increased and the devices must be connected in series. By using matched devices in series, static voltage sharing may be somewhat easy, but dynamic voltage sharing during switching is always difficult. The problem may be solved by using a multilevel, Neutral clamped inverter (Fang Zheng Peng 2001).
The diode-clamped inverter provides multiple voltage levels through connection of the phases to a series bank of capacitors. According to the original invention, the concept can be extended to any number of levels by increasing the number of capacitors. Early descriptions of this topology were limited to three-levels (Fracchia et al 2000), where two capacitors are connected across the DC bus resulting in one additional level. The additional level was the neutral point of the dc bus, so the terminology neutral point clamped (NPC) inverter was introduced. However, with an even number of voltage levels, the neutral point is not accessible, and the term multiple point clamped (MPC) is sometimes applied (Fracchia et al 2000). Due to capacitor voltage balancing issues, the diode-clamped inverter implementation has been mostly limited to the three-level. Because of industrial developments over the
248
past several years, the three-level inverter is now used extensively in industry applications (Yamanaka et al 2000). Although most applications are mediumvoltage, a three-level inverter for 480V is on the market.
The basic configuration of a three-level three-phase diode clamped inverter is shown in Figure 8.9. In this configuration the DC link capacitor C has been split to create the neutral point 0. Since the operation of all the phase groups is essentially identical, consider only the operation of the half-bridge for phase a. A pair of devices with bypass diodes is connected in series with an additional diode connected between the neutral point and the center of the pair as shown in Figure 8.9. The devices Q1 and Q4 function as main devices (like a two-level inverter), and Q2 and Q3 function as auxiliary devices which help to clamp the output potential to the neutral point with the help of clamping diodes D1 and D2 (Nikola Celanovic and Dushan Boroyevich 2000).
Figure 8.9
Power circuit of three phase three-level diode clamped inverter
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The phase voltage Va0 waveform with three angles and the corresponding gate voltage switching waves as shown in Figure 8.10. The main devices (Q1 and Q4) generate the Va0 wave, whereas the auxiliary devices (Q3 and Q2) are driven complementary to the respective main devices, with such control, each output potential is clamped to the neutral potential in the off periods of the PWM control, as indicated in the Figure 8.10. Evidently, positive phase current +ia will be carried by devices Q1 and Q2 when Va0 is positive, by devices D3 and D4 when Va0 is negative, and by devices D1 and Q2 at the neutral clamping condition. On the other hand, negative phase current- ia will be carried by D1 and D2 when Va0 is positive, by Q3 and Q4, when Va0 is negative, and by Q3 and D2 at the neutral clamping condition. This operation mode gives three voltage levels (+ 0.5Vd, 0, - 0.5Vd) at the Va0 wave, compared to two levels (+0.5Vd and -0.5Vd) in a conventional two level inverter. The levels of line voltage wave Vab are +Vd, - Vd, +0.5Vd, - 0.5Vd and 0 compared to levels +Vd, -Vd and 0 in a two-level inverter. Therefore, the three-phase inverter has 33 = 27 switching states but there are only eight states are available for a two level inverter. The Line-Line voltage waveform is shown in Figure 8.11 (Fang Zheng Peng 2001).
Figure 8.10 PWM signals for switching devices of R phase
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Figure 8.11 Line – line voltage waveform
8.3.1
Simulation of Three Phase Three Level Diode Clamp Inverter
Three-Phase Three Level Diode clamp inverter has been simulated using PSpice and their results are verified with the developed hardware model. Figure 8.12 shows the simulated power circuit model for three-phase three level diode clamped multilevel inverter. The control circuit for generating PWM pulses for R phase is shown in Figure 8.13 and the corresponding PWM pulse waveform is shown in Figure 8.14. Similarly Figures 8.15, 8.16, 8.17 and 8.18 represent the control circuits and corresponding PWM pulse waveform for Y phase and B phase respectively. The phase voltage and the line to line voltage of the simulated model are shown in Figures 8.19 and 8.20 respectively. The harmonic spectrum of the output line-line voltage is shown in Figure 8.21.
Figure 8.12 PSpice simulation of three-phase three level diode clamped inverter 251
Figure 8.13 Control circuits for R-phase 252
Figure 8.14 PSpice simulation results of PWM signals for R-phase 253
Figure 8.15 Control circuits for Y-phase 254
Figure 8.16 PSpice simulation results of PWM signals for Y-phase 255
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Figure 8.17 Control circuits for B- phase
Figure 8.18 PSpice simulation results of PWM signals for B-phase 257
Figure 8.19 Output phase-neutral voltage of three level diode clamped inverter
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Figure 8.20 Output line-line voltage of three level diode clamped inverter
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Figure 8.21 Harmonic spectrum for output voltage of three level diode clamped inverter
8.3.2
Hardware Implementation of Three Phase Three Level Diode Clamp Inverter The hardware model of the three-phase three-level diode clamped
multilevel inverter is implemented by using TMS320LF2407 DSP Processor. The hardware description of the system is shown in Figure 8.22. The hardware model contains a diode bridge rectifier, power circuit, opto-coupler, gate drive circuitry, current sensor and signal conditioner. The input of diode bridge rectifier is 230V, 50Hz AC supply. KBPC 3510 device is used as diode bridge rectifier. An isolation transformer is a transformer, often with symmetrical windings, which is used to decouple two circuits. An isolation transformer allows an AC signal or power to be taken from one device and fed into another without electrically connecting the two circuits. Isolation transformers block transmission of DC signals from one circuit to the other, but allow AC signals to pass. They also block interference caused by ground loops. Isolation transformers are commonly designed with careful attention to capacitive coupling between the two windings. This is necessary because excessive capacitance could also couple AC current from the primary to the secondary. A grounded shield is commonly interposed between the primary
260
and the secondary. Any remaining capacitive coupling between the secondary and ground simply causes the secondary to become balanced about the ground potential.
Figure 8.22 Hardware description of three level diode clamped inverter
The three-phase three level diode clamped inverter for one leg is shown in Figure 8.23. To obtain the output voltages in three steps per leg are 0 , Vdc 2 and Vdc . Thus for a three-phase inverter there are 27 states in total. Table.8.3 gives overall switching states of the inverter. In this structure we use ( M 1) 2 3 switching devices, ( M 1) ( M 2) 3 clamping diodes and ( M 1) capacitors. S1, S 4, S 5, S 8, and S 9, S12 are the main switches, they are switched directly by control pulses. S 2, S 3, S 6, S 7 and S10, S11 are the auxiliary switches and allow connection of the output of each phase to neutral point. The circuit is designed for the output voltage of three-phase, 230V, 50Hz. The IGBT1 MBH15D is used as power switching device.
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Figure 8.23 Three-phase three level diode clamped inverter for one leg
Table 8.3 States of the switches for one leg of inverter States of the Switches S1 S2 S3 S4
Sl.No.
Symbols of States
1
P
1
1
0
0
Vd
2
0
0
1
1
0
Vd 2
3
N
0
0
1
1
0
Output Voltages
The developed hardware model of three-phase three-level diode clamped inverter with DSP processor is shown in Figure 8.24. The hardware model is tested for a three-phase resistive load (360 ohms in each phase) and the test setup is shown in Figure 8.25. The gating pulses are generated using TMS 320LF2407 DSP processor and all R, Y and B phase PWM signals are observed as shown in Figures 8.26, 8.27 and 8.28 respectively. The output line–line voltage waveform is shown in Figure 8.29. The harmonic spectrum of the output line–line voltage and its harmonic level table for different odd harmonics orders are shown in Figures 8.30 and 8.31 respectively. The comparison between the simulation results and hardware results are shown in Table 8.4.
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Figure 8.24 Hardware model for three-phase three level diode clamped inverter
Figure 8.25 Test setup for hardware model of three level diode clamped inverter
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Figure 8.26 Hardware PWM pulse – R-phase
Figure 8.27 Hardware PWM pulse – Y-phase
Figure 8.28 Hardware PWM pulse – B-phase
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Figure 8.29 Output line-line voltage of three level diode clamped inverter
Figure 8.30 Harmonic spectrum of line-line voltage
Figure 8.31 Percentage harmonic distortion of individual harmonic levels
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Table 8.4
Comparative analysis of % harmonic distortion of output voltage waveform for both simulated and hardware results
Harmonic Content Sl.No.
Harmonic Order
1
Fundamental
2 3 4 5 6 7 8 9 10 11 12
Simulation Result (%) 100
Hardware Result (%) 100
3 5 7 9 11 13 15 17
0.28 0.75 0.03 0.04 0.05 0.01 0.85 1.10
0.4 1.0 1.5 0.2 0.2 0.5 1.7 2.1
19 21 23
0.65 1.21 0.30
0.4 2.7 0.8
5.69
7.8
% THD
The three-phase three level diode clamp inverter is designed and simulated using PSpice and their results are verified and compared with developed hardware for the rating of 230V, 10A, and 1KW and tested with the resistive load, which results are validated using power quality analyzer (Fluke-434). The proposed new Diode Clamped multilevel inverter has been provided high quality of both output voltages and currents. Thus, the proposed multilevel inverter provides higher performance, less EMI, and higher efficiency. Because the switching frequency is the line frequency, switching losses and related EMI are negligible.
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8.4
COMPARISON OF TWO LEVEL AND THREE LEVEL DIODE CLAMPED INVERTER
In multilevel inverters the power switches of lower voltage can be used to obtain desired voltages. These are faster and smaller than the power switches of high voltage, which is used in two level inverters. Multilevel inverters offer better sinusoidal voltage waveform than two voltage levels. This cause the Total Harmonic Distortion (THD) to be lower. Switching losses are reduced because switching frequency can be lower than that of two level inverter and also the switching speed is faster. Conduction losses are also lower because of low forward-voltage drop. When several voltage levels are used, the dv/dt of the output voltage is smaller thus the stress in cables and motors is smaller. The energy per cycle is more in the three level inverter when compared to two level inverter.
In the determination of inverter configuration, usually the cost comparison of different configuration has to be executed. The cost of the inverter is affected mainly by the DC-link capacitor, IGBT and the filtering components, while rests of the electronic component have quite insignificant affects. The good estimation of inverter costs can be done by comparing the cost of IGBT and Capacitor. In general, the two-level configuration is 30% cheaper than the three-level configuration. The difference is mostly due to the cost of clamping diodes, which are not needed in two-level configuration. The cost comparison is not taking account the effect of the volume to the unit prices. The effect of volume will decrease the unit price, which can affect to the relation between total costs.
The hardware and SIMULINK model of three-phase two-level sine PWM inverter is compared with hardware and PSpice based model of threephase three-level diode clamped inverter. The harmonic levels of the different
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odd harmonic for both hardware model of conventional two level PWM inverter and three-phase three level diode clamped inverter as shown in Table 8.5.
Table 8.5
Comparative analysis of % harmonic distortion in two level and three level inverter
% Harmonic Content Sl.No. Two-Level Inverter Three-Level Inverter Simulation Hardware Simulation Hardware 1 Fundamental 100.00 100 100 100 2 3 0.06 1.1 0.28 0.4 3 5 17.74 17.0 0.75 1.0 4 7 4.23 3.6 0.03 1.5 Harmonic Order
5 6 7 8 9
9 11 13 15 17
0.02 2.11 1.97 0.04 3.4
0.2 0.6 0.5 0.6 1.2
0.04 0.05 0.01 0.85 1.10
0.2 0.2 0.5 1.7 2.1
10 11
19 21
1.77 0.02
0.4 0.3
0.65 1.21
0.4 2.7
12
23
1.56
0.3
0.30
0.8
18.87
18.3
5.69
7.8
% THD
8.5
CONCLUSION
The multilevel inverter topology can overcome some of the limitations of the standard two-level inverter. Output voltage and power increase with number of levels. Harmonics decrease as the number of levels increase. In addition, increasing output voltage does not require an increase in voltage rating of individual force commutated devices. The three level diode
268
clamp inverter is discussed in detail with experimental results to verify the simulated results. The performance of the proposed three level diode clamp inverter is compared with the conventional two level inverter for both experimental and simulated results. The three level inverter, total harmonic distortion reduced by 57.38% as compared with two level inverter. Three level inverter can work at a very low switching frequency, which gives the possibility to work with low speed semiconductors, and to generate low switching frequency losses.
