International Journal of Emerging Technology and Advanced Engineering Website: www.ijetae.com (ISSN 2250-2459, ISO 9001:2008 Certified Journal, Volume 4, Issue 5, May 2014)

Parametric Variation Analysis of SEPIC Converter for Constant Voltage Applications Kanchan Pal1 , Rheesabh Dwivedi2 1

M.Tech Scholar, Department of Electrical Engineering, Baddi University of Emerging Sciences & Technology, Solan (H.P) India 2 Assistant Professor, Department of Electrical Engineering, Teerthanker Mahaveer University, Moradabad (U.P) India

Abstract— This paper aims at designing of an optimized controller for non-isolated DC-DC Single-Ended PrimaryInductance converter (SEPIC) for constant voltage applications. The SEPIC converter can both step up and step down the input voltage, while maintaining the same polarity and the same ground reference for the input and output. MOSFETs are used as a switching device in low power and high frequency switching applications. It may be noted that, as the turn-on and turn-off time of MOSFETs are lower as compared to other switching devices, which reduces the switching losses. High frequency operation of MOSFET reduced size of filters components. These converters are now being used for various applications, such as Switched Mode Power Supply (SMPS) etc. The paper attempts to present parametric variation analysis of SEPIC converters for constant voltage output Keywords— Non-Inverting Controller, Duty cycle, PWM.

SEPIC

Converter,

II. OPERATION CIRCUIT MODEL FOR SEPIC CONVERTER The converter circuit is divided into two parts. During mode 1, When switch S is closed then current increases and the current also increases in the negative direction. Since S is a short while closed then instantaneous voltage is approximately and the voltage is approximately . Therefore, the capacitor supplies the energy to increase the magnitude of the current in and thus increase the energy stored in . During Mode 2, When switch S is open then current which flows in the capacitor i.e becomes the same as the current . The current will continue in the negative direction. It can be seen from the diagram that a negative will add to the current to increase the current delivered to the load. Then S is off, power is delivered to the load from both and . however is being charged by during this off cycle, and will in turn recharge during the on cycle.

PI

I. INTRODUCTION With the use of power electronics devices, high efficiency conversion of energy may be accomplished. One area where these devices are used is in dc-dc converters. These converters act as ―DC transformers‖ due to their ability to change a dc voltage from one level to another with high efficiency. The SEPIC converter allows for dc voltage at one level to be either raised or lower, depending on the switch duty cycle. The output filter consisting of an inductor and a capacitor is an important part of the DC-DC converter, its size is important. The inductor characteristics affect output ripple as well as circuit stability. The inductor’s important parameters include its value, saturation current, and core material. It is widely used in electrical power system communication, instruments and meters etc. This paper discusses all these parametric variation analysis for the design of an optimized controller and a buck-boost DC-DC converter, while presenting the result of analysis.

D1

S

Figure 1. Mode:1 when switch is closed

478

R

International Journal of Emerging Technology and Advanced Engineering Website: www.ijetae.com (ISSN 2250-2459, ISO 9001:2008 Certified Journal, Volume 4, Issue 5, May 2014)

Pulse Generator

D1

i + -

Li

D

g

+

B

-

AC m

R

Co

S

S

A

D

+

i -

Ci

+ v -

R

Scope

Lo Universal Bridge

Figure 4. Simulink model of open loop non- isolated SEPIC converter Figure 2. Mode:2 When switch is open

A. Design parameter and equations for non-isolated SEPIC converter:

CONTROLLER

D1

⁄

=

+

⁄

= ⁄ = ⁄ S

R

Figure 3. DC-DC Closed loop SEPIC converter

In Figure 3. a DC-DC SEPIC converter is shown. The switching period is T and the duty cycle is D. The average output voltage can be calculated in term of the switch duty cycle. D = on time duration of switch/ total switching time period. Duty cycle =

⁄ ⁄

Where, = switching frequency = peak to peak ripple current (assuming 10% of ) = peak to peak ripple current (assuming 10% of ) = voltage ripple (assuming 5% of ) D = duty cycle Calculated value of design variables are Duty cycle (D) = 56.25%, Boost inductor ( ) = 54.47 mH, Ripple filter inductor ( = 70 mH, Boost capacitance ( ) = 1.125 µF, Ripple filter capacitance ( ) = 1.125 µF. 450 400

Output voltage ( ) =

[

]

350 300 250

Control schematic of SEPIC converter output voltage is assumed to be 400V. A simple SEPIC converter model realize in MATLAB Simulink is shown in figure 4.

200 150 100 50 0

0

0.05

0.1

0.15

0.2

0.25

0.3

0.35

0.4

0.45

0.5

Figure 5. Open loop response of non-isolated SEPIC converter

479

International Journal of Emerging Technology and Advanced Engineering Website: www.ijetae.com (ISSN 2250-2459, ISO 9001:2008 Certified Journal, Volume 4, Issue 5, May 2014) The results of open loop SEPIC converter is shown in figure 5, which depicts peak to peak ripple voltage (∆Vo) is 53 Volt and maximum o v e r s h o o t o f 1 2 %. Since the design equations assume constant input voltage and constant load under steady state conditions, the variation of input voltage shall result in fluctuation in output Therefore, a closed loop controller is required with optimized parameters to suit the constant voltage output as per requirement of load.

500 400 300 200 100 0

0

0.1

0.2

0.3

0.4

0.5

Time (Secs)

B. Controller for closed loop SEPIC converter give design equations: The Simulink Schematic of SEPIC converter with analog PI controller is shown in figure 6.

2 1.5 1

i + -

Li

0.5

D

g

A

+

B

-

D

+

i -

Ci

0 Co

S

m

AC R

+ v -

0

0.1

0.2

0.3

0.4

0.5

0.4

0.5

Time (Secs)

Lo Universal Bridge

1.5 Out1

400 Constant

PI

1

In1 Out2

PI Controller

Scope

PWM

0.5

Figure 6. Closed loop SEPIC converter realize in Simulink

0

The output voltage is sensed Vout and compared with the input voltage Vref .An error signal is produced which is processed through PI controller to generate a control voltage. The control voltage is used to feed to the PWM generator for control of switch. The PI controller has two parameters namely K P and KI.

0

0.1

0.2

0.3

Time (Secs) Figure 7. Closed loop response of non-isolated SEPIC

The results of closed loop SEPIC converter is shown in fig.7 which has maximum overshoot of 3.2%, settling time 0.0116 sec and rise time 0.0107 sec.

PI controller has transfer function: C(s) = + Where, =Proportional gain and = Integral gain.

480

International Journal of Emerging Technology and Advanced Engineering Website: www.ijetae.com (ISSN 2250-2459, ISO 9001:2008 Certified Journal, Volume 4, Issue 5, May 2014) III. EFFECT DUE TO VARIATION OF PARAMETERS ON OUTPUT VOLTAGE AND INDUCTOR CURRENT Table-I Results of boost inductor (Li) variation

Li (mH)

Voltage(Vo) Settling Rise Time Time 0.01128 0.0106

O.S (%) 6.14

O.S (%) 3

4.47 29.47

3.2

0.01129

0.0107

6.78

0.01

0.0104

3.5

0.01062

0.0106

54.47

3.25

0.0113

0.0109

7.14

0.01

0.01

4

0.01062

0.0107

79.47

3.25

0.0114

0.0109

7.14

0.01

0.01

4

0.0107

0.0107

104.47

3.25

0.01151

0.0109

7

0.01

0.01

4

0.0108

0.0107

129.47

3.25

0.01165

0.0109

7

0.0101

0.01

4

0.011

0.0107

Settling Time (Secs)

3 2 1 0 50

100

Rise Time (Secs)

0.0118

0

Current (Lo) Settling Rise Time Time 0.01062 0.0104

O.S (%) 2.7

4 % Over Shoot

Current (Li) Settling Rise Time Time 0.01 0.0105

0.0116 0.0114 0.0112 0

150

50

100

150

0.011 0.0109 0.0108 0.0107 0.0106 0.0105 0

(mH)

(mH)

Fig.8.2 Effect on settling time due to variation in boost inductor ( )

Fig.8.1 Effect on overshoot due to variation in boost inductor ( )

100

200

(mH) Fig.8.3 Effect on rise time due to variation in boost inductor ( )

Figure 8. Effect on output voltage (VO) due to variation in boost inductor ( )

When the value of boost inductor ( increases up to two times of the designed value then output voltage ( overshoot and rise time remains constant however settling time increases.

7 6.5 6 0

100

200

0.01015

Rise Time (Secs)

Settling Time (Secs)

% Over Shoot

7.5

If the value of boost inductor ( decreases from its designed value then output voltage ( overshoot, settling time and rise time continuously decreases.

0.0101 0.01005 0.01

0.0106 0.0104 0.0102 0.01 0.0098

0.00995 0

100

200

0

(mH)

(mH) Fig.9.1 Effect on overshoot due to variation in boost inductor ( )

Fig.9.2 Effect on settling time due to variation in boost inductor ( )

200

(mH) Fig.9.3 Effect on rise time due to variation in boost inductor ( )

Figure 9. Effect on inductor current (ILi) due to variation in boost inductor ( )

481

100

International Journal of Emerging Technology and Advanced Engineering Website: www.ijetae.com (ISSN 2250-2459, ISO 9001:2008 Certified Journal, Volume 4, Issue 5, May 2014) When the value of boost inductor ( increases up to two times of the designed value then boost inductor current ( overshoot continuously decreases, settling time and rise time remains constant.

4 2 0 0

5

10

0.0112

Rise Time (Secs)

Settling Time (Secs)

% Over Shoot

6

If the value of boost inductor ( decreases from its designed value then boost inductor current ( overshoot continuously decreases, settling time remains constant and rise time increases.

0.011 0.0108 0.0106 0.0104 0

100

(mH)

0.0108 0.0107 0.0106 0.0105 0.0104 0.0103

200

0

100

(mH) Fig.10.2 Effect on settling time due to variation in boost inductor ( )

Fig.10.1 Effect on overshoot due to variation in boost inductor ( )

200

(mH) Fig.10.3 Effect on rise time due to variation in boost inductor ( )

Figure 10. Effect on inductor current (ILo) due to variation in boost inductor ( )

When the value of boost inductor ( increases up to two times of the designed value then filter inductor current ( overshoot and rise time remains constant however settling time continuously increases.

If the value of boost inductor ( decreases from its designed value then filter inductor current ( overshoot and rise time continuously decreases however settling time remains constant.

Table-II Results of filter inductor (Lo) variation

Lo (mH)

Voltage ) Settling Rise Time Time 0.0111 0.0105

Rise Time 0.01

O.S (%) 3.5

Current ( Settling Time 0.0105

)

10

O.S (%) 3.25

40

3.25

0.0113

0.0106

7.14

0.01

0.01

3.5

0.0105

0.0107

70

3.25

0.0113

0.0109

7.14

0.01

0.01

4

0.01062

0.0107

110

3.25

0.0115

0.011

7.85

0.01

0.01

4

0.0107

0.0108

140

3.375

0.0117

0.011

7.85

0.01

0.01

4

0.0108

0.0108

170

3.375

0.01175

0.011

7.85

0.01

0.01

4

0.0109

0.0108

0

100

0.012

Rise Time (Secs)

Settling Time (Secs)

3.4 % Over Shoot

O.S (%) 7.14

Current ( ) Settling Time 0.01

0.0115

3.3 3.2

0.011 0

100

200

Fig.11.1 Effect on overshoot due to variation in filter inductor ( )

Rise Time 0.0105

0.0112 0.011 0.0108 0.0106 0.0104

0

100

200

Fig. 11.2 Effect on settling time due to variation in filter inductor ( )

Fig. 11.3 Effect on rise time due to variation in filter inductor ( )

Figure 11. Effect on output voltage (VO) due to variation in filter inductor (

482

200

)

International Journal of Emerging Technology and Advanced Engineering Website: www.ijetae.com (ISSN 2250-2459, ISO 9001:2008 Certified Journal, Volume 4, Issue 5, May 2014) When the values of ripple filter inductor ( increases up to two and half times of the designed value then output voltage ( overshoot, settling time and rise time continuously increases.

7.5 7 0

100

0.015

Rise Time (Secs)

Settling Time (Secs)

% Over Shoot

8

If the values of ripple filter inductor ( decreases up to seven times from its designed value then output voltage ( overshoot remains constant, settling time and rise time continuously decreases.

0.01 0.005

0

100

0.005 0

200

Fig. 12.2 Effect on settling time due to variation in filter inductor ( )

Fig.12.1 Effect on overshoot due to variation in filter inductor ( )

0.01

0

0

200

0.015

4 2 0 0

5

10

Fig.13.1 Effect on overshoot due to variation in filter inductor ( )

0.0112 0.011 0.0108 0.0106 0.0104 0

)

If the values of ripple filter inductor ( decreases up to seven times from its designed value then boost inductor current ( overshoot, settling time and rise time remains constant.

Rise Time (Secs)

Settling Time (Secs)

% Over Shoot

6

200

Fig. 12.3 Effect on rise time due to variation in filter inductor ( )

Figure 12. Effect on inductor current (ILi) due to variation in filter inductor (

When the value of ripple filter inductor ( increases up to two and half times of the designed value then boost inductor current ( overshoot increases, settling time and rise time remains constant.

100

50

100

Fig. 13.2 Effect on settling time due to variation in filter inductor ( )

0.0108 0.0106 0.0104 0.0102

150

0

200

Fig. 13.3 Effect on rise time due to variation in filter inductor ( )

Figure 13. Effect on inductor current (ILO) due to variation in filter inductor (

When the value of ripple filter inductor ( increases up to two times of the designed value then filter inductor current ( overshoot remains constant, settling time increases, rise time increases and finally its become constant.

100

)

If the values of ripple filter inductor ( decreases up to seven times from its designed value then filter inductor current ( increases, settling time and rise time continuously decreases.

483

International Journal of Emerging Technology and Advanced Engineering Website: www.ijetae.com (ISSN 2250-2459, ISO 9001:2008 Certified Journal, Volume 4, Issue 5, May 2014) Table-III Results of boost capacitor (Ci) variation

(µF)

O.S (%)

Voltage( ) Settling Time

O.S (%)

Current ( Settling Time

O.S (%)

) Rise Time

2.8

0.0113

0.0108

6

0.01

0.01

3

0.0103

0.0102

1.125

3.25

0.0113

0.0109

7.14

0.01

0.01

4

0.0106

0.0107

3.125

3.25

0.0113

0.0107

7.85

0.01

0.01

5

0.0134

0.0107

5.125

3.375

0.0113

0.0107

8.2

0.01

0.01

7

0.14

0.0108

7.125

3.5

0.0113

0.0107

18.9

0.199

0.01

20

0.335

0.0108

9.125

3.8

0.0113

0.0107

28.57

0.355

0.01

34.5

0.498

0.0128

3 2 1

0.015

Rise Time (Secs)

Settling Time (Secs)

0.125

4 % Over Shoot

Rise Time

Current ( ) Settling Rise Time Time

0.01 0.005 0

0 0

5

0

10

5

0.0109 0.0108 0.0107 0.0106

10

0

Fig. 14.2 Effect on settling time due to variation in boost capacitor ( )

Fig. 14.1 Effect on over shoot due to variation in boost capacitor ( )

0.011

5

10

Fig. 14.3 Effect on rise time due to variation in boost capacitor ( )

Figure 14. Effect on output voltage (VO) due to variation in boost capacitor ( )

When the value of boost capacitor ( increases up to nine times of the designed value then output voltage ( overshoot increases, settling time remain constant, rise time increases and finally become constant.

20 10 0 0

5

10

Fig. 15.1 Effect on over shoot due to variation in boost capacitor ( )

0.45 0.35 0.25 0.15 0.05 -0.05 0

Rise Time (Secs)

Settling Time (Secs)

% Over Shoot

30

If the values of boost capacitor ( decreases from the designed value then output voltage ( overshoot and rise time decreases however settling time remains constant.

5

Fig. 15.2 Effect on settling time due to variation in boost capacitor ( )

10

0.012 0.01 0.008 0.006 0.004 0.002 0 0

Fig. 15.3 Effect on rise time due to variation in boost capacitor ( )

Figure 15. Effect on inductor current (ILi) due to variation in boost capacitor ( )

484

5

10

International Journal of Emerging Technology and Advanced Engineering Website: www.ijetae.com (ISSN 2250-2459, ISO 9001:2008 Certified Journal, Volume 4, Issue 5, May 2014) When the value of boost capacitor ( increases up to nine times of the designed value then boost inductor current ( overshoot and settling time increases however rise time remains constant.

30 20 10 0 0

5

0.6 0.4 0.2 0 0

10

Fig. 16.1 Effect on over shoot due to variation in boost capacitor ( )

0.015 Rise Time (Secs)

Settling Time (Secs)

% Over Shoot

40

If the values of boost capacitor ( decreases from the designed value then boost inductor current ( overshoot decreases however settling time and rise time remains constant.

5

0.01 0.005 0

10

0

Fig. 16.2 Effect on settling time due to variation in boost capacitor ( )

5

10

Fig. 16.3 Effect on rise time due to variation in boost capacitor ( )

Figure 16. Effect on inductor current (ILO) due to variation in boost capacitor ( )

When the value of boost capacitor ( increases up to nine times of the designed value then filter inductor current ( overshoot, settling time and rise time are continuously increases.

If the values of boost capacitor ( decreases from the designed value then filter inductor current ( overshoot, settling time and rise time are continuously decreases.

Table-IV Results of filter capacitor (Co) variation

0.1

O.S (%) 0

Voltage( ) Settling Rise Time Time 0.0119 0.127

O.S (%) 0.4

0.125

0.82

0.0117

0.11

1.4

0.0103

1.125

3.25

0.0113

0.0109

7.14

2.125

3.5

0.0113

0.0107

3.125

4

0.0112

0.0107

4.125

4.9

0.0111

0.0106

5.125

6

0.0144

0.01066

(µF)

Current ( ) Settling Rise Time Time 0.0104 0.0105

O.S (%) 0.3

Current ( Settling Time 0.0113

0.0102

4.28

0.0112

0.011

0.01

0.01

4

0.01062

0.0107

8.5

0.01

0.01

4.17

0.0101

0.1

10.71

0.01

0.01

6

0.01

0.1

14.28

0.01

0.01

9.86

0.01

0.1

17.85

0.0135

0.01

14.2

0.0127

0.1

485

) Rise Time 0.0115

International Journal of Emerging Technology and Advanced Engineering Website: www.ijetae.com (ISSN 2250-2459, ISO 9001:2008 Certified Journal, Volume 4, Issue 5, May 2014)

6 4 2

0.015 0.01 0.005

0 0

5

0.15

0.02 Rise Time (Secs)

Settling Time (Secs)

% Over Shoot

8

0 0

10

Fig. 17.1 Effect on over shoot due to variation in boost capacitor ( )

5

0.1 0.05 0

10

0

Fig. 17.2 Effect on settling time due to variation in boost capacitor ( )

2

20 10 0 0

5

0.015 0.01 0.005 0 0

10

Fig. 18.1 Effect on over shoot due to variation in boost capacitor ( )

)

5

0.0106 0.0104 0.0102 0.01 0.0098

10

0

Fig. 18.2 Effect on settling time due to variation in boost capacitor ( )

20 10 0 0

5

10

Fig. 19.1 Effect on over shoot due to variation in boost capacitor ( )

10

)

If the values of filter capacitor ( decreases up to ten times from the designed value then boost inductor current ( overshoot decreases, settling time and rise time increases. Rise Time (Secs)

Settling Time (Secs)

% Over Shoot

When the value of filter capacitor ( increases up to six times of the designed value then boost inductor current ( overshoot and settling time continuously increases however rise time remains constant value.

5

Fig. 18.3 Effect on rise time due to variation in boost capacitor ( )

Figure 18. Effect on inductor current (ILi) due to variation in filter capacitor (

30

8

If the values of filter capacitor ( decreases up to ten times from the designed value then output voltage ( overshoot decreases, settling time and rise time are increased.

Rise Time (Secs)

Settling Time (Secs)

% Over shoot

30

6

Fig. 17.3 Effect on rise time due to variation in boost capacitor ( )

Figure 17. Effect on output voltage (VO) due to variation in filter capacitor (

When the value of filter capacitor ( increases up to six times of the designed value then output voltage ( overshoot increases, settling time initially decreases and again its start increases however rise time continuously decreases.

4

0.015 0.01 0.005 0

0.15 0.1 0.05 0

0

2

4

6

Fig. 19.2 Effect on settling time due to variation in boost capacitor ( )

8

0

2

6

Fig. 19.3 Effect on rise time due to variation in boost capacitor ( )

Figure 19. Effect on inductor current (ILO) due to variation in boost capacitor (

486

4

)

8

International Journal of Emerging Technology and Advanced Engineering Website: www.ijetae.com (ISSN 2250-2459, ISO 9001:2008 Certified Journal, Volume 4, Issue 5, May 2014) REFERENCES

When the value of filter capacitor ( increases up to six times of the designed value then output filter inductor current ( overshoot increases, settling time initially decreases and again its start increases however rise time continuously decreases. If the values of filter capacitor ( decreases up to ten times from the designed value then filter inductor current ( overshoot decreases, settling time and rise time increases.

Sanjeev Singh and Bhim Singh, ―Power quality improved PMBLDCM drive for adjustable speed application with reduced sensor buck-boost PFC converter‖ in proc. IEEE 11th ICETET, 2011, pp.180-184. [2] Sanjeev Singh and Bhim Singh, ―Comprehensive study of singlephase AC-DC power factor corrected converters with highfrequency isolation‖ IEEE Trans. on Industrial Informatics, vol. 7, no. 4, Nov. 2011, , pp. 540-556. [3] Boopathy.K and Dr.Bhoopathy Bagan .K, ―Buck Boost converter with improved transient response for low power applications‖ in Proc. IEEE SIEA, Sep 2011, pp. 155-160. [4] Altamir Ronsani and Ivo Barbi, ―Three-phase single stage AC-DC buck-boost converter operating in buck and boost modes‖ in Proc. IEEE, 2011, pp.176-182. [5] Sanjeev Singh and Bhim Singh, ―An adjustable speed PMBLDCM drive for air conditioner using PFC Zeta converter,‖ Int. J. Power Electron. (IJPElec), vol. 3, no. 2, pp. 171–188, Apr. 2011. [6] Sanjeev Singh and Bhim Singh, ―Power Electronics, Drives and Energy Systems (PEDES),‖ in Proc. IEEE PEDES’2010. [7] Sanjeev Singh and Bhim Singh, ―Single-phase power factor controller topologies for permanent magnet brushless DC motor drives,‖ in IET Power Electron., 2010, Vol. 3, Iss. 2, pp. 147–175. [8] Sanjeev Singh and Bhim Singh, ―A voltage controlled adjustable speed PMBLDCM drive using a single-stage PFC half-bridge converter,‖ in Proc. IEEE APEC’10, 2010, pp. 1976–1983. [9] Marcos Orellana, Stephane Petibon and Bruno Estibals, ―Four switch buck-boost converter for photovoltaic DC-DC ower applications‖ in proc. IEEE, ISGE, 2010, pp.469-474. [10] Bor-Ren Lin and Chun-Chi Chen, ―Soft switching isolated Sepicconverter with the Buck-Boost type of active clamp‖ in proc. IEEE ICIEA, 23-25 May 2007, pp. 1232- 1237. [1]

IV. CONCLUSION The parametric variation analysis of non-isolated SEPIC converters has been carried out for constant voltage applications considering inductor and capacitor as performance parameters. Non-isolated SEPIC converter has been designed to deliver 400 volts DC to a 400 watt load. Performance and applicability of this converter is presented on the basis of simulation in MATLAB SIMULINK. The design concepts are validated through simulation and results obtained show that a closed loop system using SEPIC converter will be highly stable with high efficiency. SEPIC converter can be used for universal input voltage and wide output power range. Better efficiency due to: moderate duty cycles, lower voltage MOSFETs and rectifiers, and reduced switching losses due to reduced peak-to-peak voltage swing. If the parameter of SEPIC converter is varied in wide range then the output response does not much vary much. The closed loop SEPIC converter has an efficiency of 96.43%.

487