43

ELECTRICAL CIRCUITS 4. OPERATIONAL AMPLIFIERS INPUT/OUTPUT CHARACTERISTICS

Introduction The purpose of this development is not to examine the detailed design of the internals of the chip for the operational amplifier but rather to present various refinements of electrical equivalent circuits that will mimic the behavior of the device as seen at its inputs and outputs. The Ideal Operational Amplifier The symbol for the opamp is shown in Figure 1.

Figure 1 Operational Amplifier symbol The inputs are at Vinvert and Vnon-invert and the output is at Vout . Looking into the inputs, electrically, it looks like an open circuit that is source-less and looking into the output, electrically, it looks like a perfect controlled voltage source with zero source impedance and voltage given by Equation 1.

VOUT  AVnoninvert  Vinvert 

(1)

Where: The Gain A   , from DC to light frequencies Essentially, the perfect opamp is an ideal voltage controlled voltage source referenced to ground with infinite input impedance, zero output impedance and infinite gain. Figure 2 illustrates this.

Figure 2 perfect opamp voltage controlled voltage source Analysis of Circuits with Perfect Opamps

44

The perfect opamp characteristics lead to very powerful simplifications for analysis of circuits containing opamps. 1. No current flows into the inputs 2. If the output voltage is finite then the differential voltage across the inputs must be zero. Consider the circuit of Figure 3 , the inverting opamp.

Figure 3 Opamp as inverting gain Using Simplification 2, if VOUT is finite, then the potential at the inverting input must be the same as the non-inverting input, ground. Using Simplification 1, all the current through resistor RIN into the inverting node must equal the current through resistor R F and go out of that node. Equation 2 implements these constraints:

VIN  0 0  VOUT  RIN RF

(2)

Solving for VOUT :

VOUT  

RF VIN RIN

(3)

Equation 3 gives the gain expression for the inverting opamp. Observe from Equation 2, the impedance seen by the input source V IN is RIN . This means that if V IN has thevinen source impedance RS , the gain relationship of Equation 3 becomes that of Equation 4:

VOUT  

RF VIN RS  RIN

(4)

45 Now, consider the circuit of Figure 4, the non-inverting opamp:

Figure 4 Opamp as non-inverting gain Again we assume that the output is finite. This means that the differential voltage between the inverting and non-inverting inputs must be zero. Additionally, the input terminals draw no current. Thus the voltage at the inverting input is V IN . We can now write a voltage divider relationship from the output VOUT , to the inverting input V IN as given in Equation 5.

VIN 

RIN VOUT RF  RIN

(5)

Solving for VOUT :

 R  VOUT  1  F VIN  RIN 

(6)

Equation 6 gives the gain for the non-inverting opamp. Observe that the impedance seen by the input signal source looking directly into the non-inverting input of the opamp amp is an open circuit (this is in contrast to the inverting gain opamp). Now consider the circuit of Figure 5, the differential amplifier. To analyze this circuit we will use superposition, the results of the inverting gain Equation 3 and the results of the non-inverting gain Equation 6.

46

Figure 5 the differential amplifier In applying the concept of superposition, we first set VIN 2 to zero and then obtain an expression for the output due to VIN 1 . Then we set VIN 1 to zero and then obtain the response to VIN 2 . We add both answers together to get the total result. Examining the circuit with VIN 2 set to zero, we have resistor RIN in parallel with RF tying the noninverting input to ground with a finite resistor. Since the non-inverting input impedance is an open circuit, the circuit is the same as Figure 3 an inverting amplifier and the output using Equation 3 is:

VOUT 1  

RF VIN 1 RIN

(7)

Now observe that at the non-inverting input resistors RIN and RF form a voltage divider. Thus we can write an expression for the voltage at the non-inverting input VIN* 2 as:

VIN* 2 

RF VIN 2 RIN  RF

If we set source VIN 1 to zero we can using Equation 6 write an expression for the noninverting gain for VIN* 2 as:

(8)

47

 R  VOUT 2  1  F VIN* 2  RIN  Plug Equation 8 into Equation 9 and simplify: VOUT 2 

RF VIN 2 RIN

(9)

(10)

Now for the total output sum Equations 7 and 10:

VOUT  

RF VIN 1  VIN 2  RIN

(11)

It is obvious from Equation 11 why this circuit is called differential amplifier. Also observe that source impedance in VIN 1 or VIN 2 invalidates the expected results of Equation 11. Now consider the circuit of Figure 6, the voltage follower:

Figure 6 the voltage follower We analyze this circuit by inspection. If the output is finite then by the infinite gain assumption there can be no difference between the inverting and non-inverting inputs. Thus the output must equal the input. Also observe that if V IN had a source impedance the op-amp would ignore it as it has infinite input impedance. Additionally, observe that the signal at the output has zero source impedance. These 2 characteristics of this circuit are the reason it is used in design. The voltage follower neutralizes source impedance a very useful characteristic.

48

Now consider the circuit of Figure 7, the transimpedance amplifier:

Figure 7 Transimpedance amplifier Again we use the infinite gain assumption to argue that the potential at the inverting input is the same as the non-inverting input, zero. We use the infinite input impedance assumption to argue that all the current from the signal input I IN must flow through R F . Thus we can obtain the following:

I IN  VOUT

0  VOUT RF   I IN RF

(12)

In Equation 12 we observe that the signal, a current source, has been converted to a voltage source. This is a useful characteristic as, for example, many kinds of sensors look like a current source and during the conditioning process whereby signals must be converted to voltages with a range compatible with a computer data acquisition system. The first step for such an application is to convert from a current to a voltage source. Also observe that if the signal current has a source impedance, the amplifier circuit will completely ignore it as the input impedance to this circuit is a perfect short circuit. Now consider the circuit of Figure 8 the summer:

49

Figure 8 the summing amplifier Observe that this circuit is like the inverting amplifier of Figure 3 except that there are multiple inputs tied into the inverting input. We apply the principle of superposition and set all the inputs except ith one to zero. Now each input simply becomes an input resistor to ground and they are all in parallel. Now applying the perfect op-amp assumptions, the voltage at the inverting input is the same as the non-inverting input, ground. Thus all these parallel resistors draw no current and the one source only sees an inverting amplifier with output given by:

 R Vout i  Vin i   F  Rin i

  

(13)

Adding up the responses from all the inputs it becomes the summing amplifier: n  R Vout TOTAL  Vin i   F i 1  Rin i

  

(14)

Non-Ideal Op-Amps from a Qualitative Perspective For many many applications the ideal op-amp assumptions serve well and designs that are realized using them are quite adequate. However, the design engineer must completely understand the limitations of these assumptions to know when they are valid and not valid. The typical garden variety IC op-amp has the following limitations 1. 2. 3.

Output voltage swing limited by the power supplies usually +/-15V Output current swing limited by short circuit protection usually 10ma Input impedance while large ~1meg, is not infinite

50 4. Gain also large but not infinite ~50K to 100K 5. Bandwidth is nowhere close to DC to light. It’s ~DC to 100KHz Figure 9 illustrates the output voltage swing limitation as imposed on a voltage follower.

Figure 9 Op-amp power supply voltage swing limitation The limitation of current limit is constraining relative to the load resistance seen by the op-amp output. Figure 10 illustrates how the output voltage swing will be reduced by short circuit protection reacting to a smaller and smaller load resistance.

Figure 10 Op-amp output limiting from short circuit current protection The relationship that is described in Figure 10 is given by Equation 15.   VMAX  I SC RLoad

 MAX  SC

Where: V is the output voltage limit of the +/- voltage swing I is the +/- short circuit current limit

(15)

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RLoad is the total resistance at the op-amp output VPS is power supply voltage (in Figure 10) Figure 11 illustrates a typical response of gain with frequency.

Figure 11 Op-amp typical gain vs frequency All of these limitations will be evaluated quantitatively along with other limitations in depth later in this hand-out. We are now ready to do some simple designs of op-amp circuits using the ideal op-amp assumptions. Gain Offset Amplifier Designs A very important application for the operational amplifier is interfacing a sensor for a physical measurement with a data acquisition system. Modern industrial processes involve sensing the progress of an operation by measured observations, digesting those measured observations and generating control signals that are input into the operation to keep it within desired bounds. Today the heart of this modern controller is a computer and the observations must be translated to be input into the computer. The system that performs this translation is a data acquisition system. To get an accurate translation, the measured observations must range between very specific voltage limits. The device that monitors the physical process is a transducer and the output of most transducers is very rarely compatible with the data acquisition systems input voltage range. Figure 12 illustrates a block diagram of this concept. The transducer senses the status of the process. The op-amp circuit conditions the electrical response of the transducer into a range of voltage compatible to the data acquisition system. The data acquisition system translates the voltage signal so the computer can read it. The computer generates a control command that is translated by the computer interface into a signal that can drive the valve and thus control the process. Observe that the computer is also receiving other input signals and issuing other outputs. Our focus in this section is the design of the opamp circuit that interfaces the transducer to the data acquisition system.

52

Figure 12 Block diagram typical process control The transducer is a device that changes some electrically discernable parameter that is a function of the desired process variable. In this section we will limit electrically discernable process parameters to voltage, current and resistance. Additionally, we will consider only cases where the process and the electrical parameter are related as the equation of a straight line. Figure 13 illustrates that typical relationship, where x is the transducer electrical parameter and p is the process parameter. Additionally, calibration data for that transducer might be given by x1 , p1  and x2 , p2  . The straight line equation for this data is given by:

x  mp  xos The slope m and the Y intercept xos are given by:

 x  x1   x  x1   , xos  x1   2  p1 m   2 p  p p  p 1  1   2  2

(16)

(17)

53

Figure 13 typical transducer electrical process parameter relationship A typical design problem for a gain offset application might be that you are given the transducer to be used and calibration data. You are also given the output voltage swing for the process parameter swing: Vout LOW , pa  to Vout High , pb  The first step is to plug p a and p b into Equation 16 to get x a and xb . Now the output voltage swing is in terms of all electrical parameters: Vout LOW , xa  to Vout High , xb  We consider 3 cases for x a and xb by examples Case 1 x is a resistance, R x : The resistance swing of R x , must be converted into a voltage swing: Vx . Additionally, that voltage swing in Vx is typically made deliberately less than the voltage swing of Vout . The output voltage swing constraint now becomes: VoutLow ,Vxa  to

Vout

High

,Vx b  . This final output voltage constraint is also a straight line equation given

by:

Vout  GVx  Vos

 Vout High  Vout Low G Vxb  Vxa 

(18)

  , Vos  VoutHigh  GVxb 

(19)

Equations 18 and 19 are used to design the final op-amp stages. Lets do an example: Example 1 Given a transducer in which a resistance R X changes in a straight line relationship with a process parameter. The electrical constraint between the resistance swing and the voltage swing to the data system is given by:

54

(0V, 1.1Kohm) to (10V, 1Kohm)

(20)

We need an op-amp circuit that converts that resistance swing into a proportional voltage swing. Additionally, we choose that voltage swing to be less than the specified output voltage swing. The inverting op-amp circuit of Figure 3 will do this. If we let R F be R X and let V IN be a precision reference voltage VREF then the transducer resistance R X has been converted into a voltage V X . Figure 14 illustrates the circuit and Equation 20 gives the relationship.

Figure 14 Transducer resistance to voltage converter

V X  VREF We pick:

RX RREF VREF  1.0V RF  1.0K

(21)

Thus the design requirement of Equation 20 translates to: (0V, -1.1V) to (10V, -1V)

(22)

These values are plugged into Equation 19 to obtain the gain offset relation for this design:

G

10  0  100 , VOS  10  100(1)  110V  1  1.1

(23)

Thus we need an op-amp circuit that generates a gain of G  100 with an offset voltage of VOS  110V . The fact that the gain is positive says that the op-amp must be of the noninverting type. This circuit is given by Figure 4 with gain described by Equation 6. We

55 design the circuit for the gain then we will modify it to incorporate the required offset. If we pick Rf  99K and RIN  1K , Equation 6 becomes:  99 K  VOUT  1  V X  100V X 1K  

(24)

Now we use the concept of superposition and modify the circuit of Figure 4 to become Figure 15.

Figure 15 non-inverting op-amp as a gain offset for Example 1 If by superposition we set V X  0 the output from VREF is given by Equation 3 and becomes:

VOUT  99VREF But Equation 23 requires that the output must be: VOUT  110 when V X  0 . Thus 110 Equation 25 yields: VREF   1.1111V  99 The complete design schematic is given by Figure 16:

(25)

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Figure 16 Example 1 complete signal conditioner schematic One should always check the design to insure it performs as specified. If we set R X  1.1K , the output becomes VOUT  0.0011V and if R X  1K , the output is VOUT  9.9989V . Case 2 The transducer is a current source Ix : The current swing of Ix , must be converted into a voltage swing: Vx . As with the previous example, that voltage swing is made deliberately less than the voltage swing of the output, Vout . For the current to voltage conversion we use the op-amp circuit of Figure 7, the transimpedance amplifier. At this point the problem is exactly like Case 1 as the output voltage constraint has become: Vout LOW ,Vx a  to Vout High ,Vx b  . Consider a design example: Example 2 Given a transducer in which a current Ix changes in a straight line relationship with a process parameter. The electrical constraint between the current swing and the voltage swing to the data system is given by: (0V, 0.1ma) to (10V, 0.5ma)

(26)

We need an op-amp circuit that converts that current swing into a proportional voltage swing. Additionally, we choose that voltage swing to be less than the specified output voltage swing. The transimpedance op-amp circuit of Figure 7 will do this. If we let R F be 1k and plug the swing of the current Ix into Equation 12, then the design constraint of Equation 24 becomes: (0V, -.1V) to (10V, -0.5V)

(27)

57 Figure 17 illustrates the schematic of this transimpedance amplifier:

Figure 17 transimpedance amplifier for Example 2 The values of Equation 27 are plugged into Equation 19 to obtain the gain offset relation for this design:

G

10  0  25 , VOS  10  25(0.5)  2.5V  0.5  0.1

(28)

Thus we need an op-amp circuit that generates a gain of G  25 with an offset voltage of VOS  2.5V . The fact that the gain is negative says that the op-amp must be of the inverting type. This circuit is given by Figure 3 with gain described by Equation 3. We design the circuit for the gain then we will modify it to incorporate the required offset. If we pick Rf  25K and RIN  1K , Equation 3 becomes:

VOUT  

25K V X  25V X 1K

(29)

Now we use the concept of superposition and modify the circuit of Figure 4 to become Figure 18. Using the principle of superposition, when the signal input is zero the output must be the offset This is expressed in Equation 30 where we have picked RREF  10K .

VOUT

Vx 0

 2.5  

25K VREF , VREF  1V 10 K

The complete schematic is given by Figure 19.

(30)

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Figure 18 summing amplifier as gain offset for Example 2

Figure 19 complete signal conditioner amplifier for Example 2 Case 3 The transducer is a voltage source Vx with an imprecise source impedance Rx : Other than negating any effect of Rx , this case was covered as part of the first 2 cases. Consider the following example. Example 3 Given a transducer where a voltage Vx (that has an imprecise source impedance) changes in a straight line relationship with a process parameter. The electrical constraint between the transducer voltage swing and the voltage swing to the data system is given by:

59 (-5V, 0.01V) to (+5V, 0.15V)

(31)

Because of the imprecise source impedance the signal source can’t be input directly into an inverting amplifier as it is not possible to realize the desired gain. The data from Equation 31 can be directly plugged into Equation 19.

G

55  71.486 , VOS  5  71.486(0.15)  5.7229 0.15  0.01

(32)

The amplifier that implements positive gain is the non-inverting of Figure 4. This circuit will reject any effect of imprecise source impedance seen at the non-inverting input. The circuit with offset will be exactly like that of Figure 15, but with different resisters. To realize the gain of G  71.486 , pick RF  70.486K and RIN  1K . To obtain the required VOS  5.7229 :

 5.7229  70.486VREF , VREF 

5.7229  0.0812V 70.486

(33)

The complete circuit is shown in Figure 20:

Figure 20 signal conditioner circuit for Example 3 As a check, set V X  0.15 and the output is: 4.9994V and set V X  0.01 and the output is: -5.0086V.