Optical Packet Switching Tutorial for WAON ’98 Dr. David K. Hunter, Department of Electronic and Electrical Engineering, University of Strathclyde, 204 George Street, Glasgow G1 1XW, U.K. Email: [email protected] This tutorial will provide an introduction to optical packet switches and their theory of operation, and will discuss how they might be networked and used in real systems. The advantage of carrying out packet switching optically lies in the immunity of optics to electromagnetic interference (EMI) and pinout problems, which may make it more cost-effective in the future to implement large packet switches optically. A packet switch must perform two principal functions. Firstly, each packet must be switched to the correct output. Since multiple packets, arriving in an unscheduled manner, may arrive simultaneously for one output, it may be necessary to buffer one or more packets. Also, in ATM systems, it may be necessary to carry out header translation. In the tutorial, the mode of operation of header translation, and the motivation for including it will be reviewed. The implementation of buffering is a major problem in optical packet switches; in electronics, random access memory (RAM) – with all the flexibility that this implies – is available, but in optics, fixed delay lines must implement the memory function. A large part of the tutorial will consist of a review of various optical packet switch architectures, and to provide a firm theoretical foundation for these. The theory of modelling these architectures with Markov chains, and the classification of various electronic ATM switch architectures, is discussed. There are three principal approaches to providing optical buffering: •

imitate electronic ATM by having large buffers and possibly header translation,

•

provide no buffering and use deflection routing – in deflection routing, contending packets are sent to the wrong output and find their way to the correct destination node by an alternative route, and

•

use a small amount of buffering but still use deflection routing – this is a compromise between the above two options.

It is shown that the size of optical packet switch that can be built is limited by optical splitting loss and noise, and it will be shown how larger switch fabrics can be constructed out of existing switch elements to overcome this problem.

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Networking concepts are discussed – both for building small 2x2 nodes into ring and shuffle networks – and for incorporating larger nodes into the layered structure of the telecommunications network. While some work has been done, the precise manner in which these might be integrated into the network remains to be investigated. Finally, synchronisation, a crucial aspect of optical packet switching, is outlined. Generally, packets entering a node must have their boundaries aligned otherwise switch devices within the node will corrupt them. In conclusion, the tutorial will cover all the major aspects relevant to optical packet switching, providing a perspective on how they fit in with the current developments in optical WDM networking, and also providing a firm understanding of the theory of their operation.

Further Reading 1. M. J. Karol, M. G. Hluchyj, S. P. Morgan: “Input Versus Output Queueing on a Space-Division Packet Switch”, IEEE Transactions on Communications, December 1987, vol. 35, no. 12, pp1347-1356 2. M. G. Hluchyj, M. J. Karol: “Queueing in High-Performance Packet Switching", IEEE Journal on Selected Areas in Communications, vol. 6, no. 9, December 1988, pp1587-1597 3. C. Bendelli, M. Burzio, M. Calzavara, P. Cinato, P. Gambini, M. Puleo, E. Vezzoni, F. Delorme, H. Nakajima: “Photonic ATM Switch Based on a Multiwavelength Fiber Loop Buffer”, CSELT Technical Reports, 1995, vol. 23, pp331-335 4. Y. Choi, H. Tode, H. Okada, H. Ikeda: “A Large Capacity Photonic ATM Switch Based on Wavelength Division Multiplexing Technology”, IEICE Trans. Communications, 4 April 1996, vol. E79-B, no.4, pp560-568 5. H. Obara: “Scalable Two-stage WDM Crossconnect Architecture”, Electronics Letters, Jan 1996, vol. 32, no. 1, pp57-58 6. D. Chiaroni, C. Chauzat, D. De Bouard, S. Gurib, M. Sotom, J. M. Gabriagues: “A Novel Photonic Architecture for High Capacity ATM Switch Applications”, Photonics in Switching’95, Salt Lake City, Utah, April 1995, paper PThC3 7. D. Chiaroni, C. Chauzat, M. Sotom, D. De Bouard, F. Masetti, J. C. Jacquinot, J. L. Moncelet, M. Bachmann, P. Doussiere, M. Goix and E. Grard: “Feasibility Issues of a High Speed Photonic Packet Switching Fabric Based On WDM Subnanosecond Optical Gates”, ECOC’96, Oslo, pp127-130 8. Y. Nakahira, H. Inoue, Y. Shiraishi: “Evaluation of Photonic ATM Switch Architecture – Proposal of a New Switch Architecture”, XV International Switching Symposium (ISS’95), April 1995, vol. 2 9. D. K. Hunter: “Switch with Large Optical Buffers (SLOB) for ATM traffic”, AllOptical Communication Systems: Architecture, Control and Network Issues II, Photonics East ‘96 Symposium, SPIE, 18-22 Nov. 1996, Boston, MA, USA, paper 2919-02 10. Y. Shimazu and M. Tsukada: “Ultrafast Photonic ATM Switch with Optical Output Buffers”, IEEE Journal of Lightwave Technology, February 1992, vol.10, no. 2, pp265-272

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11. Z. Haas: “The Staggering Switch: an Electronically Controlled Optical Packet Switch”, IEEE Journal of Lightwave Technology, May/June 1993, vol.11, no. 5/6, pp925-936 12. D. K. Hunter, D. Cotter, R. B. Ahmad, W. D. Cornwell, T. H. Gilfedder, P. J. Legg, I. Andonovic: “ 2 × 2 Buffered Switch Fabrics for Traffic Routing, Merging and Shaping in Photonic Cell Networks”, IEEE/OSA Journal of Lightwave Technology, January 1997, vol. 15, no. 1, pp86-101 13. W. H. Nelson, P. Poggliolini, M. Cerisola, A.N. M. M. Choudhury, T. K. Fong, R. Theodore Hofmeister, C.-L. Lu, A. Mekkittikul, D. J. M. Subido IX, C.-J. Suh, E. W. M. Wong: “CORD: Contention Resolution by Delay Lines”, IEEE Journal on Selected Areas in Communications, June 1996, vol. 14, no. 5, pp1014-1029 14. R. L. Cruz, J.-T. Tsai: “COD: Alternative Architectures for High-Speed Packet Switching”, IEEE/ACM Transactions on Networking, February 1996, vol. 4, no. 1, pp11-21 15. A. Bononi, F. Forghieri, P. R. Prucnal: “Throughput Limitations in Ultra-Fast AllOptical Soliton Mesh Networks using Deflection Routing”, OFC ’93, San Jose, CA, February 1993 16. M. J. Karol: “Shared Memory Optical Packet (ATM) Switch”, Multigigabit Fiber Communication Systems, 13-14 July, 1993, SPIE Proceedings, vol. 2024, pp212222

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Optical Packet Switching Recently, optical packet switch architectures, composed of devices such as optical switches, fibre delay lines and passive couplers, have been proposed to overcome the electromagnetic interference (EMI), pinout and interconnection problems that would be encountered in future very high speed electronic switch cores. Various approaches have been proposed – both those that mimic electronic switching and those that minimise the amount of buffering. Some representative switching architectures will be described; since optical random access memory does not exist, buffering must be carried out with delay lines. Various proposals for building these nodes into networks, using both regular and irregular topologies, will be outlined, and the problem of synchronisation and its proposed solutions will be discussed. David K. Hunter was born in Glasgow, Scotland. He obtained a B.Sc. in Electronics and Microprocessor Engineering with first class honours from the University of Strathclyde, Scotland, in 1987, and the Ph.D. degree from the same university in 1991 for research into switch architectures for optical TDM. Since 1991 he has been a Research Fellow, then Senior Research Fellow at the University of Strathclyde. Since 1995, Dr. Hunter has held a five-year EPSRC Advanced Fellowship. His research interests include optical switch architectures, telecommunications switch modelling, network routing and network survivability.

Optical Packet Switching Tutorial for WAON ‘98 Dr. David K. Hunter, University of Strathclyde, Scotland May 1998

Optical Packet Switching

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Acknowledgements • M. C. Chia, University of Strathclyde • S. Quist, University of Strathclyde

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1

Aims and Objectives • After this tutorial, you should be able to understand: – what optical packet switches are and why they are being proposed, – the distinction between the various types, – how they work and are modelled, – how they are networked, and – you should be able to understand the literature on this subject. May 1998

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Outline of Tutorial • Introduction • Buffering in packet switches generally • Optical packet switches • Switch fabrics • Networking concepts • Synchronisation • Conclusions May 1998

Optical Packet Switching

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2

Introduction

May 1998

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Functions of a Packet Switch 1 3

3

4 1 2

1

1

2

4

2

3

2

1

Packet switch

3 3

4

2 3 4

• switching • buffering • header translation? May 1998

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3

ATM (Asynchronous Transfer Mode) • • • • • •

ATM is a type of packet switching Connection oriented Standardised by ITU-T Packets (called “cells”) all the same size Can carry any service Useful as a point of reference for optical packet switching in general

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ATM Cell Format

48 bytes payload

5 bytes header

16 bits VCI 12 bits VPI 12 bits other

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4

VPI and VCI • VPI - virtual path indicator – defines paths which are semi-permanent – paths set up by network management

• VCI - virtual circuit indicator – defines circuits which are short-term – circuits set up by users

• Each VP (virtual path) contains multiple VCs (virtual circuits) May 1998

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Switches and Crossconnects • Crossconnects – process semi-permanent (virtual) paths – under network management control – ATM crossconnect - VPI only

• Switches – process temporary (virtual) circuits – under user control – ATM switch - VPI and VCI May 1998

Optical Packet Switching

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5

Header Translation in ATM VCI in

VCI out

port out

3

7

29

5

22

13

VCI = 5 • Incoming VCI indexes table containing: – outgoing VCI – outgoing port May 1998

Optical Packet Switching

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VCIs in an ATM Network VCI = 9 VCI = 4

VCI = 23 VCI = 6

• VCI translated (changed) at every node • VCI in ATM vs position in TDM frame May 1998

Optical Packet Switching

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6

Why Optical Packet Switching? • Close conductors tend to exhibit crosstalk EMI – electrons interact and photons don’t – problem overcome by optics

• This makes interconnection of chips a problem – large pinouts required – not a problem in optics May 1998

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Control of Optical Packet Switches Electronically controlled optical packet switch

in

out

Electronic control • Electronic control • Optical packet switching May 1998

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7

Buffering with Fixed Delay Lines • Buffer easily implemented in electronics with random access memory • Must be implemented optically with switches and fixed delay lines May 1998

k

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Approaches to Optical Packet Switching • Large buffers (>50 cells deep) – imitate electronic ATM – may have header translation

• no buffers – based on deflection routing

• compromise ( Buffer depth 55 – Load 0.9 => Buffer depth 110

• For bursty traffic, buffer depths of 1000s have been quoted May 1998

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Optical Output Buffering • Output buffering is the basis of many optical packet switches • Once a packet is in a delay line, it is difficult to change its delay – this suits output buffering – delay in each output buffer can be determined before packet enters it May 1998

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15

Shared Buffering (Electronic) 1

in N

Mux & S/P Conv

Central RAM

Demux & P/S Conv

1

out N

Next addr mem

WAR 1 Route decode

WAR N

RAR 1 RAR N

O/P count

Idle addr queue May 1998

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Optical Shared Buffering • Impossible to implement this scheme optically – too complex – optical RAM doesn’t exist

• Most optical packet switch implementations are in a sense shared buffering – Delay lines shared among multiple buffers May 1998

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16

Recirculation Buffering (STARLITE) unit delay

in

Space switch

out

• E.g. 64 x 64 switch, cell loss 10-9 requires 256 recirculation loops with load of 0.8 May 1998

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Optical Recirculation Buffering • This scheme is seldom proposed for optics with unity delays – too many circulations required – too much loss and/or noise would accumulate

• Several schemes have been proposed where some delays are greater than unity (e.g. SMOP - see later) May 1998

Optical Packet Switching

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17

Input Buffering - Head-of-Line Blocking 1

4 1 2 2 2 1 4 3 1

2

Space switch

3 4

2 1 4

• 58% maximum throughput for uniform Bernoulli traffic May 1998

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Optical Input Buffering • Input buffering never proposed for optical implementation because: – poor performance – using multiple rounds too complex – in general, once a packet is put in an optical buffer, its exit time is predetermined – input buffering is a problem because delay in buffer is not known in advance May 1998

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18

Buffered Optical Packet Switches

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Emulation of Output-Buffered Switch inputs

Delay stamp

Delay module

outputs

Counters

• Delay module: – can delay packet by any amount from 0 to d – can send it to any output – at most one packet per output per timeslot May 1998

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19

Control of Counters • There are N counters - one for each output • Increment counter i when packet arrives wishing to go to output i • Decrement counter i when packet leaves output i • The value of counter i is the delay in timeslots to be experienced by an incoming packet going to output i May 1998

Optical Packet Switching

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OASIS combiner

filters 1

1 2 1 2

b

N TWCs

May 1998

N

active demultiplexers Optical Packet Switching

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20

Optical Performance of OASIS - Simulated Optical Path Tuneable Wavelength Converter

SLA #2

SLA #1 #1

AWG Splitting Loss

#m

Combining Loss

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Scalability of OASIS

Power Penalty (dB)

5 4 622 Mb/s

3

2.5 Gb/s

2

10 Gb/s

1 0 4

8

16

Number of inputs and outputs May 1998

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21

power penalty (dB)

Cascadability of OASIS at 2.5Gb/s 10 8

4 I/Os

6

8 I/Os

4

16 I/Os

2 0 0

1

2

3

4

5

6

7

8

Number of stages

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KEOPS Broadcast and Select Switch Wavelength Converters Fibre Delay Line Buffer INPUTS 1 1 D

Wavelength Selectors λ1

OUTPUTS

λN

Output 1 Control Logic

D

Output N Control Logic N

K Mux

D

λ1 λN

Detector Optical Gate

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Demux

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22

Scalability of Broadcast and Select Switch Power Penalty (dB)

4 3.5 3 2.5

622Mb/s

2 1.5

2.5Gb/s 10Gb/s

1 0.5 0 4

8

16

Number of inputs and outputs May 1998

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Power Penalty (dB)

Cascadability of Broadcast and Select Switch at 2.5Gb/s 10 8 6 4 2 0

4 I/Os 8 I/Os 16 I/Os

0

1

2

3

4

5

6

7

Number of stages May 1998

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23

ULPHA Input #1

Input Interface Module IIM CC

Input #2

Star Coupler

IIM CC

1: n Coupler

. . .

LD Input #n

Cell Selectors CS

Cell coder

Data

(t)

output #1

CS

CB

CD

output #2

. . .

. . .

. . .

CS

CB

CD

1/V

output #n

#n

Data

…..

Addres (t) s

…..

∆T

….. T

Cell Decode CrD

T/n #1

IIM CC

Addres

Cell Buffer CB

(t1) T

Addres

Data

(t2) T optical electrical

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Single-Buffer Node (Bononi) 1

OR

ADD

1

DROP

•One incoming packet may be sent to delay line •Version with add/drop required in practice May 1998

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24

Modelling of Single Buffer Node • L - for lower output • U - for upper output • N - no cell

• • • • • •

• A = (U, L) • B = (L, U) • C = (U, U) May 1998

D = (L, L) E = (U, N) F = (N, U) G = (L, N) H = (N, L) I = (N, N)

Optical Packet Switching

49

State Diagram for Single Buffer Node CF IGE IEG L ABHD

BCF N

U IEG

ADH

ABFC

DH May 1998

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25

2x2 Switching Module 1

2

4

n/2

• Logarithmic growth with buffer depth n-1 • Functions much as output-buffered switch – but with non-optimal delay

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Operation of 2x2 Module • If traffic load is 100% then it can be mathematically proven that 2x2 structure exhibits no internal blocking – But 100% loading implies instability

• Solution: – Put each blank cell in the emptiest queue – This forces the system toward equilibrium, avoiding instability May 1998

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26

2x2 Module with 100% Load

2L

2L

2L

0

2L

1 2U

n-2 2U

L + U ,2U

n-1

2U

2U L+U

L+U

May 1998

L + U ,2L

Optical Packet Switching

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2x2 Module, 2 max lim   b ≤ω ≤ B ε → 0 max (b ,1 − ω + ε )     •Condition for strict-sense nb to new calls β = maximum traffic on any input/output link •b = minimum traffic per circuit •B = maximum traffic per circuit •reduces to m ≥ 2n - 1 if b = B = β = 1 May 1998

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34

Switch with Large Optical Buffers (SLOB) 1 2 3

m

0

m

m2

2m

2m 2

m−1

1

2

m2 − m

1 2

m k −1

1 2

2 m k −1

k

m3 − m2 m k − m k −1

3

m

to output wavelength demultiplexer

• Cascades k Alcatel switches • Buffer depth is mk - 1 • Buffer depths of thousands possible May 1998

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Bufferless Optical Packet Switches

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35

Deflection Routing

D

• Packet sent to “wrong” output in case of: – contention – buffer overflow May 1998

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Deflection Routing Node To/from local node

inputs

Pipelined control processor

To/from local node

outputs control data

• Blumenthal et al, IEEE PTL, Feb 1992 May 1998

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36

Networking Concepts

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2x2 Packet Switch as an Add/Drop Multiplexer WADM λ1 λ2 λ3 λ4

2x2 optical packet switch To/from local node

To/from local node

• Specific circuits can be selectively dropped and added May 1998

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37

Ring Networks Packet ADMs

• Ring networks are resilient May 1998

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Perfect Shuffle Networks

• Perfect shuffle network proposed covering USA (!) May 1998

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38

Layering in Telecommunications Networks ATM SDH/SONET WDM PHY May 1998

• Client/server relationship between layers • Each layer provides paths for the layer above Optical Packet Switching

77

Physical Layer

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39

WDM Layer

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SDH/SONET Layer

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40

ACTS KEOPS Networking Concept Electronic ATM Transparent packet optical layer Transparent WDM optical transport layer

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WASPNET Networking Concept ATM ATM

E.g. 64kb/s

SDH/SONET

PDH

WASPNET • WASPNET can support both “conventional” optical paths and packets May 1998

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41

Synchronisation

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The Need for Synchronisation Misaligned packets

2x2

Timeslot boundary

• Switching within fabric will “chop up” packets if they are not properly aligned May 1998

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Synchronised System Guard band

Aligned packets

2x2

Timeslot boundary

• Guard band between packets allow switch time to change state May 1998

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Coarse Synchroniser T/2

T/4

T/8

T/n

• Synchonisation to within an nth of packet

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43

Fine Synchroniser Dispersive fibre

TWC

• Synchronisation to a fraction of a bit period • TWC = Tunable Wavelength Converter May 1998

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Synchronisation Strategy • Guard band between packets – allows switches time to change state

• Coarse sync before switch inputs – fine sync not required in switch

• Fine sync prior to electronic detection • Electronic controller uses optical “signature” in header May 1998

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Conclusions

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Conclusions • Although WDM facility-switched networks are currently being deployed, optical packet switching may represent the next step beyond that • The objective is not necessarily to imitate electronic ATM or conform to the ATM standard, although optical packet switched networks will probably have to interface to electronic ATM May 1998

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Conclusions Contd. • The major problem in designing optical packet switches is the lack of optical RAM • Switch architectures focus on: – imitating electronic ATM – using deflection routing – using a small amount of buffering

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Conclusions Contd. 2 • While some work has been done, the manner in which these nodes will be networked largely remains to be investigated • Synchronisation is an important and crucial issue

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