Introduction

MOR for multi-terminal circuits

Results

Summary

Bibliography

Model reduction for multi-terminal RC circuits Roxana Ionut¸iu1

3

Industry supervisor: Joost Rommes2 Supervisor: Wil Schilders 2 3 Supervisor: Athanasios C. Antoulas 1 2 NXP

1 Jacobs University, Bremen, Germany Semiconductors, Eindhoven, The Netherlands 3 TU Eindhoven, the Netherlands

4th April 2010

/centre for analysis, scientific computing and applications

Introduction

MOR for multi-terminal circuits

Results

Summary

Bibliography

Outline 1

Introduction Motivation from electronics industry

2

MOR for multi-terminal circuits Circuit modelling General MOR framework Multi-terminal MOR

3

Results Netlist TL1 Circuit simulations

Netlist TL3 4

Summary

5

Bibliography /centre for analysis, scientific computing and applications

Introduction

MOR for multi-terminal circuits

Results

Summary

Bibliography

Outline 1

Introduction Motivation from electronics industry

2

MOR for multi-terminal circuits Circuit modelling General MOR framework Multi-terminal MOR

3

Results Netlist TL1 Circuit simulations

Netlist TL3 4

Summary

5

Bibliography /centre for analysis, scientific computing and applications

Introduction

MOR for multi-terminal circuits

Results

Summary

Bibliography

Smaller feature sizes but increasing complexity Parasitic interconnect dominates complexity of VLSI designs electromagnetic coupling effects circuit performance power

inadequate for simulations memory capacity, CPU time

Solution Interconnect modelling and reduction synthesis, optimization, verification

Intel 4004. First microprocessor (1971)

/centre for analysis, scientific computing and applications

Introduction

MOR for multi-terminal circuits

Results

Summary

Bibliography

MOR for electrical circuits Original system

Σ C ,G , B , BT , D

Reduced system

Model Reduction

Large matrices n = 1M

Small matrices n = 1k

Sparse

Ideally Sparse

Chip

Network synthesis

Modified nodal analysis

Original circuit

Extraction

Layout

  ,G  ,B  ,B  T , D Σ C

# R = 1k # C = 1k # L = 1k # nodes = 1k # terminals = 10k

# R = 1M # C = 1M # L = 1M # nodes = 1M # terminals = 10k ●

Reduced circuit

long CPU time

Full ● numerical hurdles Simulation

Simulation

/centre for analysis, scientific computing and applications

Introduction

MOR for multi-terminal circuits

Results

Summary

Bibliography

Outline 1

Introduction Motivation from electronics industry

2

MOR for multi-terminal circuits Circuit modelling General MOR framework Multi-terminal MOR

3

Results Netlist TL1 Circuit simulations

Netlist TL3 4

Summary

5

Bibliography /centre for analysis, scientific computing and applications

Introduction

MOR for multi-terminal circuits

Results

Summary

Bibliography

Modified nodal analysis (MNA) of RLC circuits From Kirchoff’s current and voltage laws, and the branch constitutive equations Dynamical system (differential algebraic)          d v(t) C 0 G El v(t) Ev = iin (t) + 0 L dt iL (t) −El∗ 0 iL (t) 0 | {z } | {z } | {z } | {z } | {z } ˙ E −A B x(t) x(t)  
v(t) ∗ E∗v 0 = y(t) | {z } iL (t) | {z } C x(t)

x internal variables: node voltages and currents through Ls iin system inputs: currents injected into terminals y system outputs: voltage drops at terminals /centre for analysis, scientific computing and applications

Introduction

MOR for multi-terminal circuits

Results

Summary

Bibliography

Outline 1

Introduction Motivation from electronics industry

2

MOR for multi-terminal circuits Circuit modelling General MOR framework Multi-terminal MOR

3

Results Netlist TL1 Circuit simulations

Netlist TL3 4

Summary

5

Bibliography /centre for analysis, scientific computing and applications

Introduction

MOR for multi-terminal circuits

Results

Summary

Bibliography

Model order reduction Given original system Σ: dimension n, p terminals    ˙ (A, E) B E x(t) = A x(t) + B u(t) Σ= y(t) = C x(t) + D u(t) C D x ∈ Rn×1 , E ∈ Rn×n , A ∈ Rn×n , B ∈ Rn×m , C ∈ Rp×n , D ∈ Rp×m b dimension k , p terminals, p ≤ k Find reduced Σ: ) " ˆ ˆ ˆx ˆx ˆ u(t) ˆ˙ (t) = A ˆ(t) + B E ˆ = (A, E) Σ ˆ ˆx ˆ(t) = C ˆ(t) + D u(t) C y

n # ˆ B D

ˆ ∈ Rp×k ˆ ∈ Rk ×k , B ˆ ∈ Rk ×m , C ˆ ∈ Rk×1 , Eˆ ∈ Rk×k , A x Construct W, V to project Σ on a k -dimensional subspace ˆ = W∗ EV, E

ˆ = W∗ AV, A

ˆ = W∗ B, B

ˆ = CV, C

D=D

/centre for analysis, scientific computing and applications

Introduction

MOR for multi-terminal circuits

Results

Summary

Bibliography

Challenges in MOR

The usual targets achieving accuracy and small dimensionality preserving system properties: stability, passivity New requirements for multi-terminal circuits Critical for (re)simulation: preserving structure → convenient synthesized models preserving sparsity [few circuit elements] → memory and CPU requirements

/centre for analysis, scientific computing and applications

Introduction

MOR for multi-terminal circuits

Results

Summary

Bibliography

How to meet MOR challenges ˆ = W∗ EV, E

ˆ = W∗ AV, A

ˆ = W∗ B, B

ˆ = CV, C

D=D

V, W ∈ Cn×k , k ≥ p, p = #terminals Existing methods: Krylov/SVD-/EVD-based V, W satisfy the usual targets: accuracy, stability, passivity ˆ A ˆ are dense → expensive to re-simulate! when p > 100, E, New methods for multi-terminal circuits ˆ A ˆ with preserved introduce graph-theoretical tools → E, structure & sparsity maintain the accuracy, stability, passivity requirements /centre for analysis, scientific computing and applications

Introduction

MOR for multi-terminal circuits

Results

Summary

Bibliography

Outline 1

Introduction Motivation from electronics industry

2

MOR for multi-terminal circuits Circuit modelling General MOR framework Multi-terminal MOR

3

Results Netlist TL1 Circuit simulations

Netlist TL3 4

Summary

5

Bibliography /centre for analysis, scientific computing and applications

Sparse reduction of R networks [Rommes, Schilders: IEEE TCAD ’10] [Rommes ’09 - COMSON MOR School]

Introduction

MOR for multi-terminal circuits

Results

Summary

Bibliography

Reducing large circuits with many terminals Candidates: circuits with O(103 ) nodes and O(102 ) terminals (and beyond!) Divide Partition network graph into smaller sub-networks identifies structure fewer #nodes and #terminals per sub-network reduction is simplified algorithmically and computationally Conquer Reduce sub-networks individually can use an MOR method of choice allows better control on sparsity /centre for analysis, scientific computing and applications

Introduction

MOR for multi-terminal circuits

Results

Summary

Bibliography

Multi-terminal RC transmission line 1441 1406 1440

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3216

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3220

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1973

3219

969 930

1052 1119 1106

68

70

3218

968 929

1050 1120 1105

69

74

73

1971

p = 22 terminals

980 965

75

79

80

1970

987 988

964

944

946

1104 82

81

1969 1968

989

963

945

1047 1048

78

76

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1964 1966

990

962

947

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1967

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1123 1102 77

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88

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1962

961

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1124 1101

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1961 32

949

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1042

89

93

1959

1963

992 984

1100 1960

960

1041

1125

1958

952

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1040

92

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955 1039

1126 1099

98

1957

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1037 1038

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101

1955

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115

117

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1138 1137

1091

1145

1944

1011 1019

41 1148 1147

1941

1945

n = 3254 nodes

1009 1021

1161

1164 1146 1940

1942

1024 1022

1176 1162

1163

1171 1165

1939 33

1279

1174

1172

1170 1166

1938

1284 1023

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1175

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1297

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← RC network as a graph [shown are only R connections]

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136

138

3195

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1068 46

3208

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887 133

883

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1067 47

1987 1988

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1982 1981

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59

1979 1980

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924

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1989

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1075 866 838

840

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3247 3245

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690 153 805

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3230

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2021

2019

3231

173

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745

747 763

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2016

2020

3232

3237

170

171 157 809

744

749

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2017

3235

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165 164 160 812 741

733

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2013

2015

3223 162 163

161 813 740

732 752

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847

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2012

3224

815 814

754 755

753

758

846

858

2011

3225

896

1079 833

739

757

845

859

2008

2010

3228 897

894 816 831 895

1080

860

2007

2009

3227 893

817 830

829 1078 832

835

834

756

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898

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2004

2006

3226

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865

864

863

862

2003

2005

3234

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1996

1999

2000

2002

900

823

1084

1992 1993

1994

1997

1998

2001

3233

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870

1991 1990

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2316 2315

3013

3024 3073

3005

2317

2311

3025 2370

3070 3076

2314 3018

3026 3074

2318

2320

2313

3027 3014

2249

3069

3075

3078

2871

2371 3172 3180

3178

2875 2375

2909

2860

2922

3177 2923

2872

2687 2873

2686

2848

2688

2846

2857

2685

2844 2851

2853

2856

2845

2854

2912

2919

2876

2847

2850 2859

2911 2918

2843

2852

2803

2917 2855

2913

2689

2800

2684

2801

2802 2804

2842

2916 2836

2835

2678

2837

2805

2683 2841

2834

2675

2840

2839

2680 2691

2838

2682

2496

2497 2798 2809

2673

2796

2650

2696

2780

2635 2634

2630

2585 2560

2558 2561

2557

2552 2551

2553

2581

2562

2556

2563

2564

2394 2749

2748 2744

2742

2554

2565

2566

2392

2393

2747

2743

2391 2395

2398

2550

2389 2549

2396 2388

2399

2548

2543

2542

2397 2547

2545 2408

2384

2544 2546

2412

2385

2413

2411

2439

2555

2750

2540

2442

2567

2746

2745

2570

2751

2741

2541

2539 2426

2383 2415

2425 2441

2568

2569 2580

2579

2390 2573

2752 2740 2739

2400

2538 2438 2437

2444

2582

2583

2578

2754

2753 2738 2737

2537

2407 2436

2445

2571

2574

2755

2736 2735

2536

2534 2435 2434

2443

2559

2586

2577

2572

2597

2756

2734 2733

2535

2533 2433

2446 2448

2584 2587

2576

2575

2758

2757

2732 2731

2401

2532 2432 2431

2447 2449

2598

2760

2730 2729

2427 2430

2450 2452

2588

2594

2595

2625 2759

2761

2728

2531 2528

2429 2428

2762

2764 2763

2727

2530

2451 2453

2596 2624

2765

2726 2725 2766

2529

2454 2474

2593

2382

2381 2623

2724 2768 2767

2402

2473 2475

2592

2627

2626

2622 2723

2722 2769

2770

2527

2478

2589

2629

2628

2599

2621 2721

2720 2772

2525

2526 2455

2590

2632

2605

2604

2719

2771 2524

2406 2472

2591

2633

2606

2603 2620

2718 2773 2774

2522 2470

2471

2631 2636

2619 2717

2716

2523

2521 2469

2468

2477 2476

2607

2602

2715

2776 2775

2520 2467

2480

2601 2618

2714 2777

2403 2456 2466

2465 2481

2479

2638

2637

2600 2617

2713

2712

2778 2519

2464

2482

2608

2616 2711

2710

2779 2518

2457

2485 2484

2639

2609

2611

2709 2781

2483

2640

2610

2612 2655

2708

2782 2517

2463

2487

2615 2656

2707 2784

2783 2516

2458

2486

2642

2613 2654

2657 2705 2785 2706 2786 2515

2514 2461

2462

2641

2379 2658

2703 2788 2704

2787

2513 2460

2490 2488

2614

2659

2701 2789 2702

2404 2512

2459 2489

2644 2653

2670

2700

2511 2405

2493

2492

2645 2380

2669

2660

2699 2792

2790

2508

2494 2822

2491

2652 2671

2668

2663

2698 2791

2510

2507

2820

2821 2823

2643

2672 2665

2662

2697 2793

2506 2509

2818

2819

2825

2646 2651

2695

2794

2505

2504

2667

2664

2694

2797 2501

2503

2378

2377 2824

2647

2666

2795 2500 2502

2816 2817

2648

2692

2693

2498

2661

2814

2815

2812

2811 2828

2826

2649 2676 2681

2495 28072808

2499

2813 2831

2830 2810

2674 2677

2806

2833

2832

2829

2827

2376

2679

2690

2799

2914

2915

2874

2849

2858

2910 2921

2920

2863 2877

2862

2861

3171 3179

6 sub-networks are identified

2997

2312 3016 30293015

3068 2247

2242 2243

2319

2321 3030

3067

2250

3017 2246 2245

3080

3079

3002

2322

3031

3056

3028 3059 2253

2244

3081

3001

3032

3065 2277

3057

2241

3084

3083

3039 2999

2300

8

2280

2252

2171 2172

3085

3086

3000

2301 2302

7

2281

2275

2224 2276

2254 2173

2170 3088

3040 3038

3054 2225

2274

2255

3090

3036

2304

2226

2227

22562273

3042

3053 2303 2296

2223

2259

3159 3162

3

3173

268

3181

2258

2257 2272

2240

3152

3154

371

3163

2

3174

273

272

2309

2308

2294

2283 2234

2235 2260

2236 2271

2239 2169 2174

3092

2295

2284 2233

2232 2261

2237 2270

2238 2168 2167

2950

3147

378

206

3155

3164 3169

3170

266

271 3184

6

2292

2293

2282

2228 2179

2175 2166

604

3096

2290

2291

2286

2285

2229 2180 2262

2178 2269

2176 605 603

3093

3153

265

3183

2289

2288

2287

2222

2230 2158

2159 2263

2177 2268

2162 602

3094

374

1

264

274 269

3182

3142

3143

3146

376

373

370

263 275

3190

2206

2219

2220

2221

2231 2160

2161 2264

2163 2267

2165 601 600

3097

3149 377

208

372

3165

262

247

2207

2218

2185

2184

2181 9

10 2265

2164 2266

606 599

3098

3100

3148

207 369 229

3167

250

3191

2208

2217

2183

2157 11

2149 2148

607 12

609

598 597 3101

3104

2186

2182

2154 2104

2105 2147

608 13

610

596

3109

375

251

261

3192

367 368

3166

289

255

230

290

252

256

2209

2216

2156

2106

574 14

611

3102

2187

2155

2153 2107

2146 612 15

575

3077

3144

3145 381

379 209

240

291 241

307

287 286

285

246

2210

2215

2188 2152

2150 2108

2109 2145 613 16

615

3082

5

384

382

380

3134

3137

3138

3141 383

361

362

363

2211

2214

2189 2151

2103 2110

2111 2144 614 17

616

595 594

3087

3140

210

222 364 347

239

292

234

227 245

221 332

348

365

2212

2213

2190 2102

2070

2112

2113 2143 573 18

617

3106

2205

2192

2191 2069

2071

2114

2115 2142 618 19

593

3091 3136

3139 205

385

346 366

293

232

233

238

294

231

305

345

237

235

226

310

344

236

295 317

316

314

342

343

330 303

315

242

243

3130

3133

539

537 356 386

2204

2193

2101 2068

2072

2116

2117 2141 619

576

591

3099

3135 538

387

2203

2100 2067

2073

2118

2119 2140

20

590

3095

536 218

357

3129

2194

2099 2066

2074

2120

620

621

589

3107

3103

540

217 355

220

2121

2139

21 622

588

3110

3125

3126

2202

2195

2098 2065

2075

2122

2123

572 22

587

592

3131 542 3132

388

353

219 359

3124

2196

2097 2076

2064

2124

2138

624

623

586

3111 3113

3105 3128

543

541

2125

2137

585

3114 3116

3108

3127 545

531

186

358

351

360

349

550

529

530 544

510

509

2201

2197

2096 2077

2063

2126

23

584 3115

3117

3112

546 511

533

534

535

352

336

350

340

341

331 298

338

339

418

299

302

512

532

507

508

214

2127

625

577

583

3118 3119

3123

2095 2062

2136

582

581 481

3120

3122

551

2198 2078

2061

2060

2128

24 627 578

580

482

553

2200 2094

2079 2058

2059 2129

626

2135

2134 628

579

483

555

3121 552

549

548

2199 2093

2080 2057

2056 2130

571

629 2133

565

564

554

524

525

187 547

25 2092

2081 2054

2055

2131

630

484

556

522 517 516 523

514

513

26 2091

2082 2053

2052

185

570 2132

567

566

562

563

520 501

515

527

528

398

389

216

354

334

335

416

421 419

324

323 322

321

333

215

213

211

414 192 415

390

212

413

424

423

392

391

412

425

434

435

436

394

393

411

426

439

438

437

326

27 2090

2083 2050

569

568

498 502 526 503

504

505

506

557

521 518

500

497 496

403 404

402 401

400 399

397 396

395

519

499

495

405

406

407

408

409

190

188

494 204

202

201

200

199

410

184

631

561

189

493 203

452

451

450

449

198

183

632

182 486 487

480

558

453

458

459

485 488 560

559

472

457 464

460

448

197

2051

490

491

492

454

463

461

447

428

427

181

489 478

473

462

446

429

430

431

633

634

476

475

471 474

445

444

443

442

2088

649 2084

479 643 470

455

441

2049

477

469 468

456

28

2085

2089

648

2048

636

639 637

467

30 29

650 2047

635 638

640 641

466

2087

709

654 707

647 646 645 644

2414

2422

2410

2409

2387

2386

2421

2440

2416

2424

2417

2423 2420 2419

2418

/centre for analysis, scientific computing and applications

Introduction

MOR for multi-terminal circuits

Results

Summary

Bibliography

MOR for multi-terminal RC: “how to” Divide 1. graph-based network partitioning (strongly connected components, bi-connected components etc.) Conquer Per sub-network: 2. partition nodes & matrices selected nodes: xS ∈ Rp+m (terminals + some internal) remaining nodes: xR ∈ Rn−m internal nodes

3. reduce xR , keep xS Advanced option: fill-in minimizing node reorderings → improved sparsity Based on method for R-networks [Rommes, Schilders: IEEE TCAD ’10] /centre for analysis, scientific computing and applications

Introduction

MOR for multi-terminal circuits

Results

Summary

Bibliography

RC netlist reduction: the maths [I., Rommes: COMSON ’09]

On full circuit or per sub-network: Original circuit model:

G, C ∈ Rn×n , B ∈ Rn×p

From MNA circuit equations: (G + sC)x = Bu, partition x in:         GR GK CR CK xR 0 +s = u. xS BS CTK CS GTK GS Moment revealing transformation [Kerns, Yang: IEEE TCAD ’97]: X = 0

0

G = XT GX, C = XT CX,

0



I 0

−G−1 R GK I



0

B = XT B, x = XT x /centre for analysis, scientific computing and applications

RC netlist reduction: the maths ... 0

0

G =



GR 0 0

GS 0

CS



0 0 GS

0

0

G , C ∈ Rn×n , B ∈ Rn×p

Transformed model:



0

, C =

CR 0 CK

0

CK 0 CS



GS − GTK G−1 R GK ,

=

CS + VT CR V + VT CK + CTK V,

0 BS



0



, x =

xR 0 xS

V = −G−1 R GK

0T

0



, B =

=

0

0

0

CK = CK + CR V 0

0

[(GS + sCS ) − s2 C K (GR + sCR )−1 C K ]x S = BS u {z } | {z } | Y0 R (s)

Y0 S (s)

0

Multiport admittance: Y S (s) already captures first 2 moments! Reduced circuit model:

b C b ∈ Rk×k G,

0 b = G0 , C b = C0 , B b = BS , x b = xS G S S

p≤k n b + sC) b x b b = Bu (G



Introduction

MOR for multi-terminal circuits

Results

Summary

Bibliography

RC netlist reduction: strategy & maths Benefits moment preservation → necessary for accuracy guaranteed stabillity and passivity → necessary in simulation Limitations 4 1. recall transform involving V = G−1 R GK → costly for O(10 ) nodes and beyond

2. fill-in in GS 0 and CS 0 → too many circuit elements! Solution structured reduction (i.e. per sub-networks) to resolve [1.] fill-in minimizing node reorderings to resolve [2.] /centre for analysis, scientific computing and applications

Industrial testcases Parasitic extraction RC models of a Low Noise Amplifier circuit (C45 technology)1 Inventory #ext. nodes #int. nodes #resistors #capacitors Analysis AC Noise SP PSS Speed up 1

TL 1 Original Red

TL 2 Original Red

79 29806 70338 12038

TL 3 Original Red

75 0 117 1047

65.83 s 0.12 s 59.68 s 0.13 s 82.81 s 0.21 s 793.13 s 2.93 s > 270x

33818 81843 12145

79 0 99 920

CPU time 60.11 0.17 s 54.82 0.18 s 110.7 0.19 s 424.28 3.33 s > 127x

27962 66068 9786

0 117 1032

NA2 NA NA NA

0.12 s 0.14 s 0.22 s 3.05 s ∞

Thanks: Gerben de Jong, Dennis Jeurissen (SDR Project, NXP Semiconductors) 2 No DC solution found (no convergence)

Introduction

MOR for multi-terminal circuits

Results

Summary

Bibliography

Outline 1

Introduction Motivation from electronics industry

2

MOR for multi-terminal circuits Circuit modelling General MOR framework Multi-terminal MOR

3

Results Netlist TL1 Circuit simulations

Netlist TL3 4

Summary

5

Bibliography /centre for analysis, scientific computing and applications

Introduction

MOR for multi-terminal circuits

Results

Summary

Bibliography

TL1 original matrices: n = 29885, p = 79 G

C

/centre for analysis, scientific computing and applications

Introduction

MOR for multi-terminal circuits

Results

Summary

Bibliography

TL1 reduced matrices: k = 79, p = 79 Maximum reduction ↔ eliminate all nodes except terminals b b G C

/centre for analysis, scientific computing and applications

Introduction

MOR for multi-terminal circuits

Results

Summary

Bibliography

TL1 reduced matrices: k = 2867, p = 79 Partial reduction ↔ preserve some internal nodes b b G C

/centre for analysis, scientific computing and applications

Introduction

MOR for multi-terminal circuits

Results

Summary

Bibliography

TL1: Reduction Summary 2 reduced netlists: maximum reduced and partially reduced TL 1 Inventory

Original

#ext. nodes #int. nodes #resistors #capacitors

29806 70338 12038

Analysis AC Noise SP PSS

Reduced (max.) 79 0 117 1047

CPU time 65.83 s 0.12 s 59.68 s 0.13 s 82.81 s 0.21 s 793.13 s 2.93 s

Perc.

Reduced (partial)

100% 99.8% 91.3%

2903 4248 4382

90.2% 93.9% 63.6%

Speed Up ∼548x ∼450x ∼394x ∼270x

CPU time 1.46 s 1.71 s 2.74 s 17.46 s

Speed Up ∼45x ∼35x ∼30x ∼45x

Perc. 79

/centre for analysis, scientific computing and applications

Introduction

MOR for multi-terminal circuits

Results

Summary

Bibliography

AC analysis - node “in”: magnitude Comparison: original, maximum and partially reduced

/centre for analysis, scientific computing and applications

Introduction

MOR for multi-terminal circuits

Results

Summary

Bibliography

PSS analysis, time domain - node “out” Comparison: original, maximum and partially reduced

/centre for analysis, scientific computing and applications

Introduction

MOR for multi-terminal circuits

Results

Summary

Bibliography

PSS analysis, freq. domain - node “out” Comparison: original, maximum and partially reduced [matched fundamental harmonics at 2 GHz]

/centre for analysis, scientific computing and applications

Introduction

MOR for multi-terminal circuits

Results

Summary

Bibliography

Noise analysis - NF Comparison: original, maximum and partially reduced → perfect match for range of interest [up to 10GHz]

/centre for analysis, scientific computing and applications

Introduction

MOR for multi-terminal circuits

Results

Summary

Bibliography

Outline 1

Introduction Motivation from electronics industry

2

MOR for multi-terminal circuits Circuit modelling General MOR framework Multi-terminal MOR

3

Results Netlist TL1 Circuit simulations

Netlist TL3 4

Summary

5

Bibliography /centre for analysis, scientific computing and applications

Reduction Summary: TL3 Immediate benefit from reduction! Original simulation not possible → error “NO DC solution found, no convergence” Simulation possible after reduction [quality “predicted” from experiments with TL1 and TL2] Inventory

Original

#ext. nodes #int. nodes #resistors #capacitors

27962 66068 9786

Analysis AC Noise SP PSS 3

TL 3 Reduced

Percentage

79 0 117 1032

CPU time NA3 0.12 s NA 0.14 s NA 0.22 s NA 3.05 s

No DC solution found (no convergence)

100% 99.8% 89.5% Speed Up ∞ ∞ ∞ ∞

Introduction

MOR for multi-terminal circuits

Results

Summary

Bibliography

TL3 reduced circuit simulations PSS: node “Vse2lse 0:2”

Noise: NF

/centre for analysis, scientific computing and applications

Introduction

MOR for multi-terminal circuits

Results

Summary

Bibliography

Summary MOR for multi-terminal circuits electronics industry needs new MOR methods → structure identification and sparsity preservation divide and conquer strategy → efficiency from reducing smaller subnetworks individually reduced netlists for multi-terminal RC networks (up to 100 terminals) significant reduction in #nodes, #Rs, #Cs → much faster simulations partial reduction possible → better approximation

netlists beyond 100 terminals → in progress

/centre for analysis, scientific computing and applications

For further reading Rommes, J., Schilders,W. H. A.: “Efficient methods for large resistor networks” IEEE Trans. CAD Circ. Syst. 29(1), 28–39 (2010) Rommes, J:, “Eigenvalue problems and model order reduction in the electronics industry,” COMSON Autumn School on MOR, presented in Terschelling, the Netherlands, Sept. 21-25, 2009. Kerns, K.J., Yang, A.T.: Stable and efficient reduction of large, multiport networks by pole analysis via congruence transformations. IEEE Trans. on Comp.-Aided Design of Integrated Circuits and Systems 16(7), 734–744 (1997) Ionutiu, R., Rommes, J.: “On synthesis of reduced order models” To appear in Lecture Notes in Electrical Engineering, Springer. Proceedings of Workshop on Model Order Reduction for Circuit Simulation, Hamburg, Germany, Oct. 30-31, 2008. Ionutiu, R., Rommes, J.: “Model order reduction for multi-terminal circuits,” COMSON Handbook (2009).