Mixed signal systems and integrated circuits

Akira Matsuzawa Tokyo Institute of Technology

5/10/2009

A. Matsuzawa

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Contents • • • • • •

Mixed signal systems High speed A/D converters High speed D/A converters Sigma delta A/D and D/A converters Wireless systems and RF CMOS circuits PLL and related systems

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Aim of this lecture • Understanding basic current mixed signal systems – Wireless transceiver

• Understanding basic mixed signal circuit building blocks: basic operation method and basic design method – – – – – –

5/10/2009

A/D and D/A converter Sigma-delta modulation Phase Lock Loop and Delay Lock Loop Low Noise Amplifier Frequency Mixer Voltage Controlled Oscillator and Frequency Synthesizer

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1. Mixed signal systems

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Current electronics and mixed signal technology

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Exciting digital consumer electronics world New consumer electronics era has been emerged. Key technologies are digital multimedia and System on a Chip.

Broadcasting Communication Network

Anywhere

Exciting Multimedia with System LSI Solutions Audio and Video Better Look Better Sound Higher Quality

Semiconductor Technology 5/10/2009

Storage Media

Anytime

Media Processor

System and Software Technologies A. Matsuzawa

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LCD Driver LCD driver is a simple example of mixed signal LSI

LCD Drivers

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LCD Driver LCD driver is an array of DA converters 6bit *R,G,B*2=36bit

Cotroler

#1

Start

Carry

#2

#8

Shift Resigter 64 64

D00-07 D20-27 D40-47

FlipFlop

D10-17 D30-37 D50-57

FlipFlop

6bits*3=18 6bits*3=18

selector

1 6 6

6bits*3=18 384 * 6 bits Latch

6 6 384 * 6 bits Latch 6 6 384 * 6 bits level shifter 6 6 384 * Voltage Scalling DA Converter

384 output

XGA: 1024*RGB (=3072) → 3072/384=8LSIs

5/10/2009

subpixel

pixel A. Matsuzawa

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Image of current electronics Digital consumer electronics and networking drive current electronics. IEEE 1394, USB, Blue tooth, Wireless LAN

DAB CS/BS

Ethenet

Digital TV ITS HII Station

Home network

ADSL, FTTH Network Digital TV W-CDMA

5/10/2009

Home Server

DVC

A. Matsuzawa

DVD 9

Mixed signal technology :Digital networkingｓ Mixed signal technology enables high speed digital networking. Data conversion

Equalization

Encryption

Data and clock recovery

Noise cancellation

Error correction

Analog

Digital DAC DAC DAC DAC

Line I/F

TX3 TX4

6b, 125MHz ADC, DAC ADC ADC ADC ADC

250Mbaud (PAM-5)

Pulse Shaping

TX1 TX2

Slicer

FFE

DFE

Clock Recovery

Side-stream Scramber & Trellis,Viterbi Symbol Encoder

Side-stream Descramber & Trellis, Viterbi decoder

Echo Canceller

Analog circuit 3-NEXTCanceller

Digital circuit 5/10/2009

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x-DSL ADSL and VDSL use the mixed signal technology ○ADSL-service, 0.5-8Mbps(Dwn)/1Mbps (Up) for 5～6Km ○VDSL-service, 13-52Mbps(Dwn) for 0.3-1.5Km ,

RXin ADSL: 0.1MHz-1.1MHZ VDSL: 2.0MHz-3.5MHz TXout

Antialiazing Filter

Reconstr action Filter

ADC

DAC

Decimation Filter

DDFS

DDFS

Adaptive DFE

Interpolation Filter

Error Correction FEC

Error Correction FEC

○ 4～256-QAM modulation → 60MHz 10-bit ADC and DAC for VDSL → 5MS/s 14-bit ADC and DAC for ADSL ○ 96-tap Decision Feedback Equalizer(DFE) ○ T=8 Read-Solomon Forward Error Correction (FEC) 5/10/2009

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Mixed signal tech. ; Digital read channel Digital storage also needs high speed mixed signal technologies.

Variable Variable Gain GainAmp. Amp.

Analog Analog Filter Filter

AAto toDD Converter Converter

Voltage Voltage Controlled Controlled Oscillator Oscillator

Data In (Erroneous)

Digital Digital FIR FIRFilter Filter

Viterbi Viterbi Error Error Correction Correction Data Out

Clock Clock Recovery Recovery

Pickup signal Analog circuit Digital circuit

Data Out (No error) 5/10/2009

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Mixed signal SoC for DVD RAM system This enables high readability for weak signal from DVD RAM pickup. World fastest and highly integrated mixed signal CMOS SoC

0.18um- eDRAM 24M Tr 16Mb DRAM 500MHz Mixed Signal Goto, et al., ISSCC 2001 5/10/2009

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Mixed signal SoC Mixed signal SoC can realize full system integration for DVD application. Embedded analog is the key.

0.13um, Cu 6Layer, 24MTr

CPU2 CPU１ System Controller

Pixel Operation Processor

Front-End

Analog FE +Digital R/C

VCO ADC

PRML Read Channel Servo DSP

AV Decode Processor IO Processor

Gm-C Filter

Back Back -End -End

Analog Analog Front Front End End

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Okamoto, et al., ISSCC 2003 14

Recent developed mixed signal CMOS LSIs 5G RF LAN

12b 50MHz ADC 2ch 12b 50MHz DAC 2ch

AFE for ADLS

AFE (Analog Front End)

Digital network 1394b (1GHz)

AFE for Digital Camera 12b 20MHz ADC+AGC

12b 20MHz ADC+DAC

2GHz RF CMOS

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Application area in mixed signal CMOS tech. Almost all the products need mixed signal CMOS LSI tech. ・Cellular phone: PDC, W-CDMA Wireless ・RR-Net: Bluetooth, IEEE802.11 ・Broad cast: STB, DTV, DAB Network Network Communication Communication ・Optical:FTTH, OC-xx ・Metal: ADSL, VDSL, Power line modem Wired ・Serial: IEEE1394, USB, Ethernet ・Parallel: DVI, LVDS Recording Recording ・DVD, VDC, HDD Output Output Input Input Power Powersupply supply 5/10/2009

・LCD, PDP, EL, Audio drive ・Camera, Others ・ Switching supply, Every LSIs (On-chip) A. Matsuzawa

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Digital technology in real world Digital signal suffers heavy damage in real world. But, digital can address this issue by own advantages, but needs the help of analog tech. Pure digital Advantages of Digital Tech. • • • • •

High robustness Programmability Time shift (memory) Error correction High Scalability

Media (Cable, Disc, Air, etc)

Noise Distortion Interference Limited bandwidth

Real world Damaged digital

Mixed Mixedsignal signaltechnology technology Reconstruction (Analog+Digital) (Analog+Digital) Not only digital, but also analog; ADC, DAC, Filter, and PLL are needed 5/10/2009

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Recovered digital 17

Role of current analog technology The role of current analog technology is an interface between digital technology and outer physical world. Analog supports digital.

Outer world Clock Generation

Analog： Physical aspects Digital： Meta-physics

Wireless com. Wired com.

(Brain）

Recording

Digital signal Processing and control

Interface Image (Sense and actuate organ; Mouse, Eye, Ear, Nose, etc.)

Power supply

Energy conversion

(Digestive organ, Circulatory organ) 5/10/2009

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Audio Motor Sensor 18

Basic technology for digital network and storage Analog and data converter technologies are needed for digital network and digital storage

Network Storage media Analog Analog Processing Processing

Data Data Converter Converter

・RF ・A/D Converter ・Optical I/F ・D/A Converter ・Cable drive ・Signal Generation

Communication Communication processing processing

・Mod/ Demod ・Channel select ・Error correction ・Protocol ・Encryption

Analog technology 5/10/2009

Data Data compression compression

・MPEG2, 4 ・DSP ・Codec

Digital technology A. Matsuzawa

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Development of ADCs for digital consumer products Development of ADCs has contributed to the progress of digital consumer electronics.

Performance Index Number

100

6b, 1GHz

Bip / BiCMOS

6b,800MHz

10b, 20MHz, 30mW

DVD Digital Camera 8b, 100MHz

CMOS

Digital OSC

50

DVC

Applied System

10b, 300MHz HDTV

8b,20MHz

20

Video Camera 6b, 80MHz

10 5

Wide-TV

10b, 30MHz

Perfec TV MUSE Receiver

8b,120MHz HDTV

Camera

2

Digital OSC 10b,20MHz

1

Video Switcher

'85 5/10/2009

'90 A. Matsuzawa

'95 20

Progress in A/D converter; video-rate 10b ADC ADC is a key for mixed signal technology. We have reduced the cost and power of ADC drastically; 1/ 2,000 in Power and 1/200,000 in cost! dulling past 20 years CMOS technology attained it.

1980

1982

1993

Now

Conventional product World 1st Monolithic World lowest power SoC Core Board Level (Disc.+Bip) 20W $ 8,000 Analog Devices Inc.

Bipolar (3um) 2W $ 800

CMOS (1.2um) CMOS (0.15um) 10mW 30mW $0.04 $ 2.00

Our development Our development Our development

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Power and area reduction of video-rate 10b ADCs Power and area of ADC have been reducing continuously. Currently, ADC can be embedded on a chip Power reduction 2000 1000 500 200 100 50

Flash Two-step Subranging Folding/Interpolating Pipeline Look-ahead Pipeline Others

20 10 5 2 1 1980 1985 1990 1995 2000 2005 2010 Year

5/10/2009

100.0

Flash Two-step Subranging Folding/Interpolating Pipeline Look-ahead Pipeline Others

50.0 20.0 Area size (mm2)

Power (mW)

10000 5000

Area reduction

10.0 5.0 2.0 1.0 0.5 0.2 0.1 1980

A. Matsuzawa

1985 1990

1995 Year

2000 2005

2010

22

Power and area reduction of video-rate 10b ADCs

100.0 50.0

100.0

20.0 10.0

Flash Two-step Subranging Folding/Interpolating Pipeline Look-ahead Pipeline Others

5.0 2.0 1.0 0.5 0.2 0.1 0.1

0.2 0.3 0.5 0.7 1

2

3

5

Area size (mm2)

Power/MHz (mW/MHz)

50.0

7 10

20.0 10.0 5.0

Flash Two-step Subranging Folding/Interpolating Pipeline Look-ahead Pipeline Others

2.0 1.0 0.5 0.2 0.1 0.1

0.2 0.3 0.5 0.7 1

2

5

10

Process node (m)

Process node (m)

M. Hotta et al. IEICE 2006. June

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Early stage mixed signal CMOS LSI for CE Success of CMOS ADC and DAC enabled low cost mixed signal CMOS LSI. This also enabled low cost and low power digital portable AV products. 1993 Model: Portable VCR with digital image stabilizing

6b Video ADC

Digital Video filter

System block diagram

8b low speed ADC;DAC 5/10/2009

8b CPU A. Matsuzawa

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Mixed signal system: Digital Camera Current camera system uses digital technology.

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Ultra-high speed ADCs Ultra-high speed ADCs have been developed.

8b, 120MHz, (1984） World fastest 8b ADC

8b, 600MHz ADC (1991） World fastest 8b ADC

6b, 1GHz ADC (1991） World fastest in production (Dual Parallel method）

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Digital Oscilloscope Ultra-high speed ADCs have realized Digital Oscilloscopes.

横河電機： 8b 1GHz (1994年） 松下通信工業：10b 100MHz OSC (1986年）

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Progress in high-speed ADC High speed ADC has reduced its power and area down to be embedded. World fastest 6b ADC 6b, 1GHz ADC 2W, 1.5um Bipolar

ISSCC 1991

6b, 800MHz ADC 400mW, 2mm2 0.25umCMOS

Pd/2N[mW]

ISSCC 2000 World fastest CMOS ADC

10

1

Reported Pd of CMOS ADCs

ps s G W/ m 10

s sp G W/ m 1

ISSCC 2002 World lowest Pd HS ADC 7b, 400MHz ADC 50mW, 0.3mm2 0.18umCMOS 5/10/2009

A. Matsuzawa

1 order down

This Work

0.1 1

10

Conversion rate [x100Msps] 28

System: DVD player Current electrical system is complicated and needs analog and memory. Optical Disc Optical Head

Memory

32bit MCU DRAM Embedded

Red Laser

Driver

Head Amp

16M SDRAM

PhotoPhoto-receptive Compound

4M Red Laser Unit DRAM ODC

High-speed Analog-Digital

Read Channel Pre Amp

Analog

Analog Front End

Servo DSP

：First-Gen. ：Second-Gen. 5/10/2009

Copy Protection

MPEG 2 Video

Demodulation ECC

MPEG Algorithm

Video Output

AC-3 Output AC-3 Audio

CD DEM

System Controller MCU

Servo DSP

AV Decoder

Media Core Processor

Stereo Output

Console Panel

System Controller MCU

：Third-Gen. ：Fourth-Gen.

OS API A. Matsuzawa

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Full DVD system integration in 0.13um tech. Advanced mixed signal SoC has been successfully developed. Okamoto, et al., ISSCC 2003

0.13um, Cu 6Layer, 24MTr

CPU2 CPU１ System Controller

Pixel Operation Processor

Front-End

Analog FE +Digital R/C

VCO ADC

PRML Read Channel

AV Decode Processor IO Processor

Servo DSP

Gm-C Filter

Back Back -End -End

Analog Analog Front Front End End

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Cost reduction in DVD Recorder One-chip integration for hole DVD system has been realized. This makes circuit board simpler and contribute to the cost down, as well as performance up. ’2000 Model ’2003 Model

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Scaled CMOS technology Current Scaled CMOS technology is very artistic. Matsushita’s 0.13um CMOS technology Gate SiO2

Seven lattices

Si

100nm Transistor 5/10/2009

Cu Interconnection A. Matsuzawa

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CMOS as analog device CMOS has many issues as analog device, but also has a variety of circuit techniques CMOS

Bipolar

Comment

Switch action

++

--

Low Input current

++

--

Only CMOS can realize switched capacitor circuits

High gm

-

+

CMOS is ¼ of Bip.

Low Capacitance

+

-

This results in Cp issue

fT

+

+

Almost same

Voltage mismatch

--

++

CMOS is 10x of Bip.

1/f noise

--

++

CMOS is 10x to 100x of Bip.

Low Sub. effect

-

+

Offset cancel

++

--

Analog calibration

++

--

Digital calibration

++

--

Embed in CMOS

++

--

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CMOS has a variety of techniques to address the self issues

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GHz operation by CMOS Cutoff frequency of MOS becomes higher than that of Bipolar. Over several GHz operations have attained in CMOS technology 0.13um 100G

0.18um 0.25um

Frequency (Hz)

50G 20G

fT : CMOS fT : Bipolar (w/o SiGe) fT /10 (CMOS )

0.35um

RF circuits

10G 5G

Cellular Phone

CDMA

5GHz W-LAN

fT /60 (CMOS )

gm fT  2Cin vsat fTpeak  2Leff

Digital circuits

2G 1G

IEEE 1394 D R/C for HDD

500M 200M 100M

1995

5/10/2009

2005

2000

A. Matsuzawa

Year 34

CMOS technology for over GHz networking Digital consumer needs over GHz wire line networking. CMOS has attained 5Gbps data transfer.

World first 1394b transceiver For 1Gbps networking

Test chip for 5Gbps wire line

0.25um 3AL_CMOS

0.18um 4AL_CMOS

5Gbps Eye pattern

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Basic issue of analog in LSL technology Scaling can realize higher integration and higher speed yet low power for digital circuits. In contrast, analog performance is used to be degraded with scaling.

Performance (Log)

Architectural and circuit technology development has been needed.

Integration

Speed

1  2 L

1  1.5 L

L W

tox Leff

Xj

0.7x

Scaling Rule

Signal swing Dynamic range =

L

1.5

Scaling 1 Design　 Rule 5/10/2009

Noise + Mismatch+Distortion

(Log) A. Matsuzawa

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Wireless systems The number of wireless standards are increasing

W-CDMA (384k) GSM GPRS EDGE

2005年～ HSDPA (14M)

cdma2000 cdma2000-1X EV-DV 1x(144K) EV-DO(2.4M) (5.2M)

2010 4G

Cellular

PDC

PAN

LAN

IEEE802.20(4M) PHS

A-PHS IEEE802.11b (11M)

ZigBee

802.11a/g 802.11n (54M) (100M)

Bluetooth

IEEE802.15 UWB

Data rate 5/10/2009

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Technology edge RF CMOS LSI Many RF CMOS LSIs have been developed for many standards Wireless LAN, 802.11 a/b/g 0.25um, 2.5V, 23mm2, 5GHz

Discrete-time Bluetooth 0.13um, 1.5V, 2.4GHz

M. Zargari (Atheros), et al., ISSCC 2004, pp.96 5/10/2009

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K. Muhammad (TI), et al., ISSCC2004, pp.268

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Current status of RF CMOS chip RF CMOS was a university research theme, however currently becomes major technology in wireless world.

• Current products – – – – –

Bluetooth: 2.4GHz, CSR etc., major Wireless LAN: 5GHz, Atheros etc., major CDMA : 0.9GHz-1.9GHz, Qualcomm, becomes major Zigbee: 2.4GHz, not yet, however must use CMOS TAG: 2.4GHz, Hitachi etc., major

Major Cellular phone standard, GSM uses SiGe-BiCMOS technology

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Why CMOS? • Low cost – Must be biggest motivation – CMOS is 30-40% lower than Bi-CMOS

• High level system integration – CMOS is one or two generation advanced – CMOS can realize full system integration

• Stable supplyment and multi-foundries – Fabs for SiGe-BiCMOS are very limited.  Slow price decrease and limited product capability

• Easy to use – Universities and start-up companies can use CMOS with low usage fee, but SiGe is difficult to use such programs.

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Multi-standard issue Reconfigurable RF circuit is strongly needed for solving multi-standard issue. Multi-standards and multi chips

Future cellular phone needs 11 wireless standard!!

IMT-2000 RF

IMT-2000 BB

Current GSM RF

GSM BB

Bluetooth RF

Bluetoth BB

MCU

GPS RF

GPS BB

Power

Unification Future Reconfigurable RF

DSP

Yrjo Neuvo, ISSCC 2004, pp.32

Unified wireless system 5/10/2009

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Scalable circuit design for wireless systems Scalable and reconfigurable design is needed for addressing the multi-standard wireless systems Changeable: ADC/DAC resolution and bandwidth

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Basics of analog to digital and digital to analog conversion

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Basic mixed signal system Mixed signal systems has DSP, ADC, DAC, and pre/post filter basically. The signals are converted between time continuous and time discrete.

Time continuous

AGC

Pre Filter

Time discrete

ADC

DSP

Time continuous

DAC

(low pass)

Post Filter (low pass)

Clock

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Sampling theory The signal has bandwidth of fm. Periodical sampling pulse has a period of T. Voltage

Signal

F(x(t))

x(t)

Time

-fm

Time domain

v(t ) 

+fm

Frequency domain



  t  nT 

v(t ) 

n  



V e n

j

2nt T

n  

1 , Vn  T

Fourier expansion

Sampling Pulse

fc=1/T

T: period

Time domain 5/10/2009

Vn 

0

fc 2fc 3fc 4fc



T /2

T / 2

v(t )e

j

2nt T

dt

1 ,  e  j 2n  1 T

1  j v(t )   e T n  

2nt T

Frequency domain A. Matsuzawa

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Sampling Sampling process can be treated as the product of the signal and the sampling pulse Sampled signals have multi-sidebands at Nfc

Signal

x(t )  v(t ) 

x(t)



 xnT  t  nT 

x

n  

X(t)v(t) x

x(t) Time

v(t )  Sampling Pulse



  t  nT 

n  

T: period

v(t)

Time

Sampling



F  x(t )  v(t )   X  f   X nfc  f   X nfc  f  n 1

0

fc 2fc 3fc 4fc

Frequency 5/10/2009

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Frequency spectrum in sampled data. x(t )  v(t ) 



 xnT  t  nT 

n  

 1  j 2Tnt 1  e jx  e  jx  2nt    1  2 cos v(t )   e    cos x  2 T n   T T   n 1

1 1  2 cos2fct   2 cos2  2fct   2 cos3  2fct   ....... T 1 x(t )  v(t )   x(t )  2 x(t ) cos2fct   2 x(t ) cos2  2fct   2 x(t ) cos3  2fct   ....... T

v(t ) 

Thus x(t)v(t) can be regarded as a AM modulated signal that the career signal of which frequency is nfc and the modulated signal is x(t) If simply assuming x(t) is single tone: xocos (2πfat) Sampled signal has a sideband of +/- fa at around nfc  xo   x(t )  v(t )   cos2fat   2 cos2fat  cos2fct  T  n 1 

 cos A cos B 

1 cos( A  B)  cos( A  B)  2

 xo    cos2fat    cos2 nfc  fa t   cos2 nfc  fa t  T  n 1 

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Signal reconstruction from sampled data If signal bandwidth is less than fc/2, signal can be reconstructed perfectly. 

F  x(t )  v(t )   X ( f )   X nfc  f   X nfc  f 

F(x(t)v(t)): Fourier transform of x(t)v(t) X(f): Fourier transform of the analog signal

n 1

Low pass filter

Nyquist condition

fm 

fc/2

0

fc fm fc-fm

5/10/2009

fm fc-fm

fc

Signal non-overlap

2fc fc+fm

2fc+fm

Signal can be separated to reconstruct

2fc-fm

fm 

0

fc 2

fc+fm 2fc-fm

fc 2

Signal overlap

Signal can not be separated

2fc 2fc+fm

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Reconstruction from sampled signals Sampled signal can be reconstructed to be continuous signal through low pass filter. Sampled signal

Ideal Low pass filter

Reconstructed signal

x(t)

x

x

0dB Pass

Stop

ωc/2

Time

Time

Angular frequency Sampled signal:

Ideal Low pass filter:

 1 G ( )   0 

x(t )  v(t ) 



 xnT  t  nT 

n  



c



2

c

y (t ) 

 x(nT )  v(t  nT )

n  

2

sin fct  v(t )  fct



y (t ) 



 x(nT )

n  

sin fct  nT  fct  nT 

For the unit impulse signal

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Reconstruction by sampling function Signal can be reconstructed by the convolution between sampling signal and sampling function.

S (t ) 

Original signal

Sampling

T

1 fc

y (t ) 

sin fct  fct

Sampling function 

 x(nT )  S (t  nT )

n  

y (t ) 



 x(nT )

n  

sin fct  nT  fct  nT 

再生過程 Reconstruction

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Aliasing effect Signals of which frequencies are higher than fc/2 are folded to the lower frequencies L.T. fc/2. Nose which spreads wide frequency is also folded to lower frequency and accumulated.

Low pass filter is needed

Noise

Caution!! Frequencies are folded

Sampled signal is conventionally Noisy

falias  fsig  nfc

: nfc  fsig 

falias  n  1 f  fsig

:

2n  1 fc 2

2n  1 fc  2

fsig  n  1 fc

Accumulated Noise

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Special technique: Under sampling By using under sampling technique, we can obtain modulated signal from very high carrier frequency. However, very low SNR due to noise accumulation.

Under sampling technique

2GHz carrier

Bandwidth is 8MHz

8MHz signal

20MHz sampling

fc=20MHz

2GHz Carrier

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Reconstruction process Reconstructed signals has also folding frequency components. Thus DAC need post low pass filter. The interpolation technique can relax the required LPF spec. Interpolated signals Sampled signals Conversion period Conversion frequency Reconstructed signals and interpolation Required LPF spec. Folding noise

Original signal

Spectrum of reconstructed signals Folding noise

Spectrum of over sampled signals

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Aperture effect in DAC Due to the aperture effect, the higher frequency component of the output signal from DAC Is decreased. Sometime some technique is needed.

x

DSP

DAC

x

Actual Step pulse train in DAC output

Ideal impulse train

Time

Time

Frequency characteristics of DAC

Signal intensity

Aperture effect

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 f  sin    fc  A( f )   f  fc

High frequency signal of DAC is decreased Use aperture correction filter that has inverse frequency characteristics. Reduce the pulse width by using small duty pulse Increase the conversion frequency using over sampling technique

A. Matsuzawa

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Frequency spectrums in ADC and DAC

Input signal to ADC

Folding Signal in ADC and DSP

Re-folding

Signal from DAC without the aperture effect

Aperture effect

Signal from DAC with the aperture effect

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Quantization ADC has a finite resolution number and the signal is quantized. This causes error called “quantization error”. Analog to Digital Converter Ideal line Digital output

+ Input signal

Minimum step (1LSB)

Quantization step

Quantized signal

Quantization noise

Quantized signal = Input signal + Quantization noise Ideal quantization error Analog input 0 to 2N-1 Effective full-scale 0 to 2N Nominal full-scale

Quantization error

LSB (Least Significant Bit)

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Quantization noise and SNR Quantization causes noise and this noise power reduces with increase of resolution number. Principal signal to noise ratio (dB) of N bit ADC is about 6N+2. The higher resolution of ADC realizes the higher SNR for signal processing. Ideal quantization error

Probability density of quantization error 1  , x  0.5q p( x)   q  0, x  0.5q

Noise power

1q Nq   x p ( x)dx     0.5 q 3 2 0.5 q

Signal intensity

Signal power

1  2N q   S   2  2 

Full scale:

S  2N q

Step: q

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2

2

2

Signal to Noise Ratio

 S  SNRrms / rms  10 log   20 log 2 N  10 log(1.5)  Nq   6.02 N  1.76(dB) A. Matsuzawa

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SNR increase by increasing fsc We can increase SNR by increasing of conversion frequency with low pass filter. Conversion clock

Signal =2MHz

Quantization noise

fc/2 =5MHz

2x conversion rate

fc= 10MHz

Total Noise power is same, but power density is lower

Frequency Signal =2MHz Noise After LPF

Conversion clock Half noise power Is removed Quantization noise

fb=5MHz

fc/2 =10MHz

3dB higher SNR by 2x higher fc

 fc   SNRrms / rms  6.02 N  1.76  10 log  2 fb 

fc= 20MHz

fc: Conversion frequency fb: Bandwidth of LPF

Frequency

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