Ambipolar circuits for analog, mixed-signal, and radio-frequency applications Kartik Mohanram† , Xuebei Yang‡ , Guanxiong Liu∗ , Masoud Rostami‡ , and Alexander Balandin∗ † Department of Electrical and Computer Engineering, University of Pittsburgh ‡ Department of Electrical and Computer Engineering, Rice University ∗ Department of Electrical and Computer Engineering, University of California, Riverside [email protected] [email protected] [email protected] [email protected] [email protected]

Abstract This paper describes the circuit design of a polarity controllable triple-mode amplifier based on ambipolar graphene field-effect transistors for analog, mixed-signal, and radio frequency (AMS/RF) applications. We describe how such polarity controllable circuits can greatly simplify circuits for applications such as phase shift keying and phase detection in the AMS/RF space, with the potential to realize higher bandwidth and frequency as well as lower power consumption over conventional circuits based on state-ofthe-art technology. This paper emphasizes the theoretical analysis and performance optimization of these circuits, which have been independently fabricated and validated in our experiments.

1.

Introduction

Since its discovery in 2004, graphene has attracted strong interest as an alternative device technology for future nanoelectronics [1, 2]. Graphene field-effect transistors are widely considered exciting candidates for analog, mixed-signal, and radio frequency (AMS/RF) systems serving the rapidly growing wireless communications market in the high-frequency (≥ 60 GHz), millimeterwave domain [3]. Recent work has demonstrated graphene FETs with a cutoff frequency fT of 26GHz and it is further predicted that THz graphene FETs can be achieved at a channel length of 50nm [4]. Graphene FETs for AMS/RF applications use intrinsic micron-wide graphene ribbons as channel material, which results in graphene FETs displaying ambipolar conduction. In ambipolar conduction, which has also been reported in intrinsic carbon nanotube and silicon nanowire transistors [5, 6], the applied bias can be used to switch the transistor from n-type to p-type, with electron and hole conduction dominating the current, respectively [7]. Since traditional CMOS circuits are based on unipolar transistors, several techniques have been proposed to eliminate the ambipolar conduction behavior. However, proposals such as channel doping pose fabrication challenges and exhibit significant parametric variations. On the other hand, recent work has shown that controlling ambipolarity also provides exciting design opportunities. Ambipolarity has been exploited to implement universal reconfigurable 8-function gates [8], dynamic generalized NOR gates [9], and XOR-based static gates [10]. In [11], the first single-transistor frequency multiplier and full-wave rectifier that does not require any filters was implemented by accurately biasing an ambipolar graphene transistor. In this paper, we describe how ambipolar conduction can be used to realize a single-transistor graphene polarity controllable (GPC) amplifier whose small signal gain can be switched between positive and negative modes by controlling the gate bias, without alThis research was supported by NSF grant CCF-1208934 and SRC-DARPA through FCRP Center on Functional Engineered Nano Architectonics.

tering its physical configuration. We describe how GPC amplifiers can benefit communication circuits in applications such as phase shift keying (PSK) and phase detection that traditionally use complex analog multipliers and/or filters (circuits for both applications were fabricated and reported by our group in [12,13]). GPC amplifiers have several advantages over conventional multipliers. First, the GPC amplifier is a single-transistor design with lower parasitics and potentially higher spectral efficiency. Second, whereas inherent device properties limit the bandwidth of Si CMOS and Si BJT multipliers to about 10 GHz [14, 15], the high fT of graphene devices promises the ability to achieve a larger bandwidth using the GPC amplifier. Finally, whereas high electron-mobility transistor (HEMT) and heterojunction bipolar transistor (HBT) multipliers have achieved a bandwidth of 20–40 GHz [15–17], their DC power consumption ranges from 150mW to 2.5W, which is significantly higher than the 2–4mW range of the proposed GPC amplifier. The basic GPC amplifier uses one transistor and one resistor. When the transistor is biased to be p-type, the circuit is a commonsource amplifier whose gain is negative, and when the same transistor is biased to be n-type, the circuit is a common-drain amplifier whose gain is positive. Although this basic structure offers competitive performance, a potential shortcoming is that switching between common-source and common-drain configurations may introduce mismatched performance in gain, output DC level, and output resistance. We evaluate and mitigate these practical concerns through an enhanced GPC amplifier that integrates an additional resistor such that regardless of the applied bias, it is always configured in the common-source mode with source feedback and differential output. If the two resistances are equal, the enhanced GPC amplifier is symmetric for n-type and p-type modes, and achieves matched gain, output DC level, and output resistance. The proposed designs are validated using a zero band-gap, topgated graphene transistor reported in [7]. Although its Ion /Ioff is low, its high transconductance (≈ 320 µS) makes it suitable for AMS/RF applications. An analytical model for the current-voltage behavior of the device, described in [7], is used to evaluate the performance of the GPC amplifier proposed in this paper. Further, we also evaluate how asymmetry inherent to ambipolar conduction and fabrication non-idealities such as contact resistance decrease/increase mismatches in gain and output DC levels. Our analysis and simulations show that the enhanced GPC amplifier can mitigate such effects in practice. We provide extensive discussions and motivate solutions based on robust design to enforce equality in the small-signal gains with GPC amplifiers. This paper is organized as follows. Section 2 presents model background and GPC preliminaries. Section 3 describes the use of GPC amplifiers for PSK and phase detection. Section 4 discusses robust design issues to address asymmetric ambipolar conduction and contact resistance. Section 5 presents conclusions.

2.

Background and motivation

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In this section, we first provide the necessary background for the graphene transistors considered in this paper. We then introduce and discuss the basic and enhanced design of the GPC amplifier proposed in this paper.

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Graphene transistors

In this paper, we consider an ambipolar top-gated transistor reported in [7], the schematic for which is shown in Fig. 1(a). The width of the device is 2.1 µm and the length is 1µm. The back-gate capacitance (Cback ) is 12 nFcm-2 , the insulator thickness is 285 nm, and the dielectric constant is 3.9. The top-gate capacitance (Ctop ) is the series combination of the electrostatic capacitance of the gate dielectric and the quantum capacitance, with a value of 552 nFcm-2 . Due to the zero band-gap, Ion /Ioff is limited to 7; however, the FETs achieve a high transconductance of 320µS making them suitable for AMS/RF applications. A compact model for this graphene transistor [7] is shown in Fig. 1(b). Here Rs is the contact resistance and is reported to be 700–1300Ω for the range of voltages considered in this paper [7]. The I-V characteristic relating the drain current to the terminal biases is obtained by solving the following self-consistent system of expressions: R V −R I p W eµ RssdI s d n20 + (Ctop /e(Vgs-top + V − V0 ))2 dV L d Id = −2Rs Id ) 1 + µ(VsdLv sat 0 0 0 where V0 = Vgs-top + (Cback /Ctop )(Vgs-back − Vgs-back ), Vgs-top = 0 12 -2 1.45V, Vgs-back = 2.7V, and n0 = 0.5 × 10 cm . For the ideal case, carrier concentration remains high enough that the carriers’ saturation velocity vsat can be considered constant. For fixed vsat , the transistor exhibits symmetric ambipolar conduction, which is considered in the first part of the paper. For non-ideal cases, however, vsat varies according to the change of carrier concentration, and thus the transistor will exhibit asymmetric ambipolar conduction. The effects of asymmetry in ambipolar conduction on GPC amplifier design are addressed in section 4 in this paper. The device’s transfer characteristic is shown in Fig. 1(c). For a fixed drain-source voltage, a minimum conduction point Vmin is observed. At this point, the electron current is equal to the hole current, and the total current is at its minimum. When the gatesource voltage is less than Vmin , the current is mainly based on hole conduction, configuring the device as a p-type transistor; at higher voltages, on the other hand, electron conduction dominates and the device behaves as an n-type transistor. This behavior can be explained as follows using the top-of-the-barrier approach [18]: the rise of the gate-source voltage lowers both the conduction band and the valence band of graphene inside the channel. While a lower conduction band allows more electrons to enter the channel, resulting in an increase in the electron current, the decreasing valence band will obstruct more holes from entering the channel, hence reducing the hole current.

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Graphene polarity controllable amplifiers

In this paper, we propose a novel amplifier that exploits the ambipolar conduction property of the graphene transistor, named graphene polarity controllable amplifier or GPC amplifier. The schematic of the basic GPC amplifier is shown in Fig. 2(a). Vgs-back is fixed, and Vgs-top is used to apply both the bias and the small signal input. A resistance Rload is placed between the drain and ground. If the device is biased at the point where Vbias < Vmin (Vmin is the minimum conduction point), the small-signal transconductance gm = ∂Id /∂Vgs-top is negative, whereas if Vbias > Vmin , the transconduc-

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Figure 1: Graphene transistor, with top-gate and back-gate [7]: (a) structure, (b) compact model, and (c) ambipolar I-V characteristics for Vgs-back = 40V. 0.015 0.01 0.005

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Figure 2: (a) Basic GPC amplifier. (b) The AC coupled output signals for the GPC amplifier when Vdd is 5V, Rload is 4kΩ, and Vbias is set to 4V and 7V, respectively. The output DC values (not shown) are 2.37V and 2.29V, respectively. Note the 180◦ change of phase in the output Vout . tance is positive. For negative transconductance, the gain given by ∂Vout /∂Vgs-top = Rload ∂Id /∂Vgs-top is negative, and for positive transconductance, the gain is positive. The low frequency response of the basic GPC amplifier is shown in Fig. 2(b) when the effects of all capacitances are negligible. Vgs-top = Vbias + Vac − Vdd , and the output is obtained by solving the following equation selfconsistently: Vout = I(Vgs-top , Vout ) Rload Compared with traditional single transistor amplifiers based on unipolar MOSFETs, where the small-signal gain is always positive or negative, the gain of the proposed GPC amplifier can be tuned between positive and negative modes by proper biasing, which forms the basis for the operating principles of the GPC amplifier. As presented in Fig. 2, the gain is positive for high Vgs-top (> Vmin ), while it is negative for low Vgs-top (< Vmin ). When the swing of the input small signal is also considered, for a load resistance of 4kΩ and Vbias of 3.7V, the swing exceeds 0.4V , the harmonic distortion is less than 10%, and the gain is 0.80. The DC power of the GPC amplifier is 2–4mW depending on the bias points. Note that with the availability of a more detailed model and data, the swing and gain can be further optimized by choosing a better bias and load resistance. Note also that the AC performance is not evaluated here because gate-source and gate-drain capacitance is not fully incorporated into the model.

We report the small signal gains and output resistances of the basic GPC amplifier under different transconductance and load resistances in Table 1. For the fair comparison between the performance of the left and the right branch, symmetric bias pairs are chosen, i.e., Vbias,l + Vbias,r = 2Vmin . Hence, when biased at different branches the output DC levels and small signal transconductance are matched. Note that a negative and positive transconductance means the graphene transistor is biased at the left and right ambipolar branch, respectively. We make two observations. First, whereas increasing the absolute values of transconductance or load resistance significantly increases the absolute value of gain of the left branch, it has a comparitively smaller impact on the right branch. Second, even when the absolute values of the transconductance and load resistances are the same, the absolute value of the gain of the left branch is always greater than the right branch. This appears contradictory because one might expect that under symmetric conditions, nothing should change except the sign of gain. Table 1: Gain and output resistance for the basic GPC amplifier. Note that different gm are obtained through different bias and Vdd , which are not shown here. Output DC levels are always matched.

Rload (kΩ)

2.7

Gain 5.1

7.5

-230.1 230.2 -204.1 gm (µS) 204.2 -179.4 179.4

-0.612 0.379 -0.473 0.322 -0.372 0.271

-1.14 0.532 -0.794 0.440 -0.579 0.369

-1.64 0.618 -1.05 0.510 -0.731 0.423

Rout (kΩ) 2.7 5.1 7.5 2.66 1.65 2.33 1.58 2.06 1.51

4.95 2.31 3.91 2.16 3.23 2.05

7.17 2.71 5.17 2.52 4.05 2.35

To illustrate this problem we need to analyze the operating mode of the GPC amplifier for different biases. When the device is biased at the left branch, Vbias < Vmin and the current is mainly due to hole conduction, so the transistor can be regarded as p-type. In this situation, the circuit is configured as a common-source amplifier, and its gain can be roughly expressed as A = −|gm |Rload . When the transistor is biased at the right branch, however, it is mainly electron conduction that contributes to the current, so the transistor should be regarded as n-type. For an n-type transistor, the output terminal should be regarded as the source and the terminal connected to Vdd is drain, so the circuit is configured as a commondrain amplifier whose gain is A = |gm |Rload /(|gm |Rload +1). (Note that due to the terminal change, the transconductance we are measuring is actually ∂Id /∂Vgd when the transistor is biased at the right branch. However, this value is equal to gm under the fixed Vsd , so we can still use the data from Table 1.) Therefore, the GPC amplifier is configured as either common-source or common-drain amplifier depending on the bias voltage, which explains why different gains are obtained for the same transconductance and load resistance. The output resistance of both branches are shown in Table 1. As expected, they exhibit the features of common-source and common-drain configuration respectively, i.e., the output resistances are always larger when biased at the left branch for the same load resistance. A potential problem exists, however, for the proposed GPC amplifier. Since common-source and common-drain amplifiers exhibit very different figures of merit, the switching of GPC amplifiers between different configurations is bound to introduce different and mismatched performance in gain, output DC level, output resistance, etc. as shown in Table 1. While some of these values can

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Figure 3: (a) Enhanced GPC amplifier. (b) The AC coupled output signals for the GPC amplifier when Vdd is 5V, Rload is 10kΩ, and Vbias is set to 4.15V and 5.6V, respectively, The output gain for both values of Vbias is 2 and the output DC values are also equal to 1.34V. be matched by properly choosing the bias points, it is not possible to match all of them simultaneously. For example, in order to match the DC output for two bias points, it is required that Vbias,l + Vbias,r = 2Vmin . However, under these bias conditions, the absolute value of the gain cannot be matched, since | − gm,right Rload | >

|gm,left |Rload |gm,left |Rload + 1

where |gm,right | = |gm,left | for symmetric biases. The difference can be lowered only at the cost of reducing transconductance and gain. For applications that need matched performance, the mismatched behavior may prevent the use of the GPC amplifier. In order to solve this problem, we propose an enhanced GPC amplifier with the structure shown in Fig. 3(a) and output shown in Fig. 3(b). Equal resistances are added to both source and drain terminals, making the circuit symmetric. Now, regardless of whether the transistor is n-type or p-type, the amplifier is always configured in the common-source mode with resistive feedback at the source. The output is obtained differentially as shown in Fig. 3(a), and the absolute value of gain is approximately 2|gm |Rload /(1 + |gm |Rload ) regardless of whether the transistor is biased to be n-type or p-type. Similar to the basic GPC amplifier, Vbias,l + Vbias,r = 2Vmin is required in order to match the two DC outputs. Under these bias conditions |gm,right | = |gm,left |, resulting in the same absolute value of gain. The performance of the enhanced GPC amplifier is shown in Table 2. Note that as long as the bias satisfies |gm,right | = |gm,left |, the gains and output resistances are always equal in both modes for the enhanced GPC amplifier. Table 2: Gain and output resistance for the enhanced GPC amplifier. Note that different gm are obtained through different bias and Vdd , which are not shown here. Output DC levels are always matched.

Rload (kΩ) -189.5 189.6 -231.7 gm (µS) 231.6 -269.1 269.1

2

Gain 4.8

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Rout (kΩ) 4.8 7.6

-0.451 -0.685 -0.787 1.49 2.64 3.30 0.455 0.685 0.793 1.49 2.64 3.30 -0.653 -1.10 -1.34 1.65 3.18 4.20 0.647 1.10 1.35 1.65 3.18 4.20 -0.864 -1.65 -2.14 1.79 3.75 5.26 0.864 1.66 2.16 1.79 3.75 5.26

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