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Millimeter-Wave CMOS Power Amplifiers With High Output Power and Wideband Performances Yuan-Hung Hsiao, Student Member, IEEE, Zuo-Min Tsai, Member, IEEE, Hsin-Chiang Liao, Student Member, IEEE, Jui-Chih Kao, Student Member, IEEE, and Huei Wang, Fellow, IEEE

Abstract—In this paper, we propose a design method of multi-way combining networks with impedance transformation for millimeter-wave (MMW) power amplifiers (PAs) to achieve high output power and wideband performance simultaneously in millimeter-wave frequency. Based on the proposed methodology, three power amplifiers are designed and fabricated in V-band, W-band, and D-band using 65-nm CMOS technology. With 1.2-V supply, the saturation powers of these power amplifiers are 23.2 dBm, 18 dBm and 13.2 dBm at 64 GHz, 90 GHz, and 140 GHz, with 25.1-GHz, 26-GHz, and 30-GHz 3-dB bandwidth, respectively. Compared with the published MMW amplifiers, these PAs achieve high output power and wide band performances simultaneously, and the ouput power levels is the state-of-the-art performance at these frequencies. Index Terms—CMOS, high output power, impedance transformation, millimeter-wave, power amplifier, power combining, wideband.

I. INTRODUCTION

M

ILLIMETER-WAVE (MMW) wireless applications attract wide attention in recent years [1]–[4]. With the progress of the CMOS processes, the gate length of a transistor is minimized, which makes the CMOS devices operating in MMW possible. With advantages of low cost and high level baseband integrations, MMW systems integrated with digital control circuit are published [5] in the past three years. A power amplifier (PA) is the most critical component in MMW wireless transceiver systems, which provides enough output power to overcome the path loss of transmitters. Although many publications of MMW circuit design and implementation using CMOS processes have been reported, it is a challenge for PA design because of the drawbacks such as high lossy substrate and low breakdown voltage in CMOS process.

Manuscript received July 04, 2013; revised October 03, 2013; accepted October 16, 2013. Date of publication November 05, 2013; date of current version December 02, 2013. This work was supported in part by the National Science Council of Taiwan (NSC 102-2219-E-002-004), in part by National Taiwan University under Excellent Research Projects (10R8908), and in part by the TSMC University Shuttle Program. This paper is an expanded paper from the IEEE Internationa; Microwave Symposium held on June 2–7, 2013, Seattle, WA Y.-H. Hsiao, H.-C. Liao, J.-C. Kao, and H. Wang are with the Department of Electrical Engineering and Graduate Institute of Communication Engineering at National Taiwan University, Taipei 106, Taiwan (e-mail: [email protected]. tw). Z.-M. Tsai was with the Graduate Institute of Communication Engineering at National Taiwan University, Taipei 106, Taiwan. He is now with the Department of Electrical Engineering at National Chung Cheng University, Chiayi 621, Taiwan (e-mail: [email protected]). Color versions of one or more of the figures in this paper are available online at http://ieeexplore.ieee.org. Digital Object Identifier 10.1109/TMTT.2013.2288223

Power combining is a necessary technique for PAs to achieve high output power requirement in MMW frequency [6]. Several structures for power combining are proposed. The first one is direct combining, which connects transistors directly to realize combining. It is the simplest power combining technique and used widely in III–V semiconductor PA designs [7]–[10]. However, the combining transistors cannot exhibit the output power as expected because the output power of each transistor delivered to the combining node has unequal phase when the number of combining transistors increases. 3-dB coupler is another combining technique used in PA designs, including Wilkinson power combiner [11], [12] and quadrature coupler [13], [14]. The combining network design is straight forward since 3-dB coupler adds 3-dB output power directly with given PA units. Moreover, the quadrature coupler provides excellent return loss for a balanced PA, which is useful for system integrations. However, a 3-dB coupler is designed based on quarter-wavelength broadside coupled lines, so the limited bandwidth and large area are expected when the number of combining transistors increases. Transformer power combining [15]–[20] has been investigated recently, because of the properties which combine transistors and transfer impedance at the same time. In addition, with the virtual ground generated at the common node, it is not necessary to use on-chip bypass for dc bias network. Thus, using this structure can realize high output power PAs in a very compact size. Nevertheless, some drawbacks should be taken into consideration. Without additional compensated matching elements, gain performance is restricted for transformer PAs, and it is difficult to support the wideband applications. Besides, as the number of combining transistors increases, the transformer design becomes more complex, and interactive electrical magnetic (EM) simulations for optimal transformer structure are required. In this paper, we present a new design methodology of wideband power combining networks with impedance transformation. Since the optimum load for maximum output power is decreased when the combining number of transistors increases, the bandwidth performance of the PA is limited. To overcome this situation, we use the low impedance transmission line (TL) for combining network designs. Based on this method, a large number of transistor combining can be realized to achieve high output power and wideband performance simultaneously. Three PAs are designed and fabricated to demonstrate this method in V-band, W-band, and D-band, respectively. According to the experiment results, the highest saturation power of 23.2 dBm, 18 dBm, and 13.2 dBm, with 3-dB bandwidth of 25.1-GHz, 26-GHz, and 30-GHz are achieved in the V-band, W-band [21] and D-band [22] power amplifier, respectively.

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Fig. 1. Saturation output power and optimum load impedance for maximum output power versus the numbers of combining transistor.

II. DESIGN CONCEPT FOR WIDEBAND MULTI-WAY POWER COMBINING NETWORK WITH IMPEDANCE TRANSFORMATION A. Bandwidth Consideration Under Low Load Impedance Device size selection is the starting point for PA designs in MMW frequency. Large device size provides high output power, while the gain performance is lower because the parasitic capacitance degrades the gain, especially at high frequency. In general, the high output power can be achieved using combining technique, so the device size is selected to provide enough gain in the interested frequency range. With the device size and the number of the combining transistor are determined, the maximum output power can be obtained based on the load-pull simulation. By transferring the impedance from 50 to optimum load for maximum output power by matching network, the load can receive the maximum power from the device. For wideband PA designs, bandwidth performance can be constructed due to the matching network topology, which dominates the frequency response. Constant matching method [23] is one of the methodologies helping the designer with matching network design to achieve wideband performances. However, when the number of transistor combining increases, it is difficult to implement a PA with wideband performance. Fig. 1 presents the relationship of the number of transistor combining with the output power and impedance for maximum power delivery. It can be observed that when the number of combining device increases, the optimum load impedance for maximum output power also decreases quickly. In this case, the number of combining device is selected as 16 at 90 GHz, with optimum load for maximum output power , and it is near to the short circuit point on Smith chart. Fig. 2 shows curves of different values and several trajectories of impedance transformation by a series TL with different characteristic impedance of the same length connected at the device output. It is noted that in the low impedance region, curves are very close for different values, which will limit the design freedom for bandwidth because the curve of impedance transformation intersects high

Fig. 2. Curves of different Q values and the impedance transformation of series with fixed electrical TLs connected at small impedance length under different characteristic impedances.

curves easily. The trajectories of impedance transformation on the Smith chart can be expressed as (1) (2) (3) is the system impedance, and is the optimum where load impedance for maximum output power. For a TL with half wavelength, the curve of reflection coefficient makes a circle on the Smith chart, and the curvature of the circle can be described based on (2), which depends on the characteristic impedance of TL, as shown in Fig. 2. To observe the relationship directly, an approximate equation from (1)–(3) describes the radius of the circle with the small load impedance condition is (4) is inBased on this equation, the radius is increased when creased. The comparison between exact and approximate equation are plotted in Fig. 3, which agrees well in low impedance region. Although the curve is slightly different under the high load impedance condition, it can be observed that the radius increases when the characteristic impedance of series TL increases. Since curvature and inversed radius is in direct proportion, the curvature increases with lower characteristic impedance of series TL. It represents that the impedance transformation trajectory of a low impedance line will not intersect high curves, which means that compared with high impedance

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Fig. 4. A given characteristic impedance of transmission line can be split transmission lines connected in parallel with times characteristic into impedance. Fig. 3. Results from approximated and accurate equations for the radius of the circle are estimated by the impedance transformation trajectory of half-wave length transmission line.

TLs, using low impedance TLs at device output to design matching network will achieve wideband performance. When the impedance is transferred from low to high, the high characteristic impedance TL can be used because the curves are dispersed at the center of Smith chart. However, to realize the low impedance TLs in CMOS process is a challenge. Under the design rule check (DRC) limitation, the impedance of the TL is from 40 to 70 based on a thick-film microstrip line structure with UTM as signal line and metal 1 as reference plane, which is still too high to achieve wideband performance in a large number of transistors combining matching network design. Therefore, a design concept is developed to solve this problem.

Fig. 5. Equivalent characteristic impedance of the transmission line which uses 50 transmission lines connected in parallel with different number.

B. The Characteristic of Low Impedance Transmission Line and Realization As shown in Fig. 4(a), for a TL with given characteristic impedance, the Y matrix can be expressed as below (5) If a factor is multiplied in numerator and denominator, the factor can be expressed as summation terms of . Overall Y matrix of the two ports in Fig. 4(a) becomes

Fig. 6. Under even-mode operation, the connected node of parallel connected lines can be separated directly according to the equal potential assumption.

(6) where Y matrix stands for the individual TL in the parallel structure. Eq. (6) means that given TLs with characteristic impedance (i.e. 50 ) connected in parallel, which is shown in Fig. 4(b), can realize a TL with characteristic impedance (i.e. 50/N ). Fig. 5 shows the equivalent characteristic impedance versus different numbers of TLs connected in parallel. According to this property, we can use high characteristic impedance TLs connected in parallel to realize a TL with low characteristic impedance. Another important property is that the signal is even-mode operation in parallel connected TLs structure. Fig. 6 presents the

concept of equal potential assumption of even mode operation. As shown in Fig. 6(a), the voltage source with current pass through into the connected parallel TLs structure. The voltage remains the same at input node, and the current will be divided into . Based on the equal potential assumption of even mode operation, the node can be separated to construct the multi-paths structure with each path connected the voltage source with since the voltage is the same at the TLs input node, as shown in Fig. 6. With these two techniques, a TL can be modified to an -way power combiner with impedance transformation. In fact, these techniques can be used before modifying any matching network structure into a multi-way power combiner.

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Fig. 7. Concept of the proposed wideband power combining network with impedance transformation. (a) An originally given output matching network uses low impedance line for wideband performance. (b) Split the transmission lines and passive component for power combining network design. (c) Separate the connected nodes based on the even-mode assumption.

C. Design Procedure and Example The design procedure for wideband power combiner with impedance transformation is illustrated as follows. 1) Design a matching network with low impedance TLs to transfer the impedance from 50 to the optimum load for maximum output power. 2) Split the TLs connected in parallel to construct the combining structure. 3) Separate the connected node to construct the power combiner structure based on the equal potential assumption of even mode operation. To demonstrate the design procedure, a wideband matching network transferring the impedance from 50 ohm to is designed. This topology is also used in the W-band PA design [21] with 16-way power combining, as shown in Fig. 7(a). Next, each series TL is split into several TLs in parallel. For example, the first TL with characteristic impedance is split into 16 TLs connected in parallel with characteristic impedance of . The shunt capacitor and open stub

also can be split as shown in Fig. 7(b). Finally, based on the equal potential assumption, the connected nodes can be separated. For example, the point A can be split into , and the point B can be split into , respectively. Therefore, the power combiner with impedance transformation can be realized, as shown in Fig. 7(c). Fig. 8 presents the curve of impedance transformation and frequency response of the output combining network with impedance transformation, which illustrates wideband performance as expected. Ideally, the RF signal operated on this combining structure is always operated in even-mode. However, the odd-mode signal [24], [25] may be excited due to the discontinuities, such as bend or T-junction, which may cause the circuit to become unstable. To check the odd-mode stability, we can place a PEC at the symmetric plane and observe the input impedance, as shown in Fig. 9(a). If the input impedance is negative, it means that the circuit will be unstable under odd-mode excitation. In order to eliminate the odd-mode signal and guarantee the stability, the odd-mode suppression resistors should be inserted in each symmetric plane of the combining structure as shown in

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Fig. 10. (a) Original schematic of the output stage matching network (unit: ), and (b) the schematic of the 3-stage common source V-band power amplifier with 32-way transistor combining.

Fig. 8. (a) Impedance curve on Smith chart and (b) frequency response of the output matching network from 75 GHz to 110 GHz.

Fig. 11. DC biasing connection in the V-band PA design. M2 is used as reference ground and M1 is used as power plane.

a large number of transistors to achieve high output power without additional combiners/splitters. III. CIRCUIT DESIGN Fig. 9. (a) Block diagram to check the stability under odd-mode signal operation, and (b) insert the odd-mode suppression resistor to eliminate the odd-mode signal.

Fig. 9(b), and ensure the positive input impedance to suppress the odd-mode signal. By arranging the characteristic impedance of TLs and splitting nodes carefully, a multi-way, wideband power combiner with impedance transformation can be realized to combine

Three MMW CMOS PAs using the proposed method designed and fabricated in TSMC standard bulk 65-nm 1P9M CMOS GP process in different frequencies are described in this section. A. V-Band PA With 32-Way Power Combining In V-band PA design, unit transistor size is selected with fingers biased at 1.2-V and 0.8-V and the 3-stage common-source (CS) structure with combining

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Fig. 12. Chip photo of the V-band power amplifier with total size 2.04 includes all pad and dummy metal. The 32-way output combining structure is marked with solid line and quarter circuit block is addressed with dash line.

Fig. 15. (a) Original schematic of the output stage (unit: ), and (b) the schematic of the 3-stage CS W-band PA with 16-way output combining.

Fig. 13. Passive components for the W-band power amplifier include multimetal connected dummy and M8-UTM connected transmission line.

Fig. 14. Concept of bus-bar technique for dc bias construction. (a) A combining structure with open-stub for impedance transformation under even-mode operation. (b) Using TL spitting separated the open-stub connected in parallel. (c) Connect the end of the open stubs to construct the dc biasing path and do not affect the RF signal.

Fig. 16. Chip photo of the W-band PA with chip size

ratio 8:16:32 from the input to output stage is adopted. The output matching network is realized with low impedance lines to achieve wideband performance at first, which transfers

optimum load for maximum output power to 50 , and the impedance of TL is increased gradually. For the inter-stage matching network design, T-network structure is used to

.

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Fig. 20. The simulated and measured large signal performances at 64 GHz. Fig. 17. The complete schematic of the 4-stage CS D-band PA.

Fig. 21. The frequency responses versus output power of the V-band PA from 56 GHz to 66 GHz with about 1 dB variation.

Fig. 18. The chip photo of the 4-stage D-band PA with size of 0.38

.

Fig. 19. The simulated and measured S-parameters of the V-band PA.

transfer the impedance and establish dc bias path using the embedded short stub. When the original matching network designs are finished, the matching networks can be modified as a multi-way combiner

by the proposed method. To connect 32 transistors, the output matching network is modified to a 32-way power combiner. The original schematic and complete schematic of the output stage are shown in Fig. 10. It can be observed that this structure generates many closed loop contours from the schematic, and odd-mode signal may be excited due to discontinuities, causing oscillation in the closed loop. To avoid this situation and ensure the PA is operated in even-mode, the odd-mode suppression resistors are added to avoid the oscillation from odd-mode signals. These closed loop contours also create difficulties in designing the dc bias network. Fig. 11 shows the methodology for dc biasing in this work. We use the metal 2 layer (M2) as dc/ac ground plane, and take advantage of the metal 1 layer (M1) as the power plane. The dc current is fed through the transistors by the short stubs connected to the power plane. Many of the ground pads and the connected dummy metals from M2 to ultra-thick-metal (UTM) are placed in the chip to decrease the voltage drop due to the parasitic resistance and to help heat dissipation. Fig. 12 shows the chip photo with all pads and dummy metals included and the chip area is 2.04 . The 32-way output combining structure is marked with blue solid line and quarter circuit block is addressed with green dash line.

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TABLE I SUMMARY OF THE PUBLISHED V-BAND SI-BASED POWER AMPLIFIERS

: Excluding driving amplifier.

B. W-Band PA With 16-Way Power Combining [21] The 3-stage CS structure is also utilized to provide enough gain for the W-band PA design. Single transistor size is selected fingers biased at 1.2-V and 0.9-V , and with the combining ratio is 4:8:16 from the input to output stage. The design procedure is as same as the V-band PA design. After the matching network design is done, the output matching network is modified to a 16-way power combiner to connect 16 transistors in this PA. Fig. 13 is the description of passive components used in this design. In order to achieve low impedance line for narrow width TL, the M8-UTM connected TL is in use, which also promotes the dc current handling. The dc consideration in this amplifier is different from the V-band PA. To deal with the high return current, the M1 and M2 metals are connected as the reference ground plane of TLs to reduce the parasitic resistance. Several ground pads and connected dummy metals from M1 to UTM are placed, which not only reduce parasitic resistance of the ground plane, but also help the heat dissipation. On the other hand, to overcome the geometric limitation of the combining structure for dc biasing network designs, the “bus-bar” [26], [27] technique is utilized to solve this problem. In [26], [27], the dc path is embedded in the combining network, and optimized the RF performances by full EM simulation. In this work, we realize this technique by connecting the open stubs in the matching network directly. Fig. 14 shows the design procedure of dc biasing using bus-bar technique. In Fig. 14(a),

a simple combining structure with short open stubs structure connected two transistors is given. The open stub can be split into two open stubs with half characteristic impedance, which is presented in Fig. 14(b). Since the RF signal is operated in even mode, the connected point of the open stubs generates the virtual open at the symmetric plane. Thus, for the RF signal, the connected open stub is still an open stub for impedance transformation; on the other hand, it provides a path for dc current going through to bias the transistor directly, as shown in Fig. 14(c). The original and the complete schematics are presented in Fig. 15. The photograph is shown in Fig. 16 with 0.82chip size including all pads and dummy metals. C. D-Band PA With 8-Way Power Combining [22] unit finger width biased The 12-finger RF device with 1.0at 1.2-V and 0.9-V is utilized in D-band PA design. The 4-stage CS structure is used to provide sufficient gain, and the ratio of device size from the input to output stage is 1:2:4:8, with total gate width of 96at the output stage. Based on the same design procedure as the V-band and W-band PAs, the impedance transform network is realized by modifying the original output matching network to an 8-way power combiner, and the complete schematic is shown in Fig. 17. The dc bias network is constructed using the short stubs at the output stage. For other stages, the dc current is fed through the short stub directly. The chip photo of D-band PA is presented in Fig. 18. Chip size is 0.38 including all pads and dummy metals.

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TABLE II SUMMARY OF THE PUBLISHED W-BAND SI-BASED POWER AMPLIFIERS

: With a peak gain at 64 GHz.

Fig. 22. Simulated and measured results of the W-band PA S-parameters with .

IV. EXPERIMENTAL RESULTS A. V-Band PA With 32-Way Power Combining The on-wafer probing testing is adopted to measure this PA. and are biased at 1.2 V and 0.8 V respectively. AgThe

Fig. 23. Large signal measurement setup for the W-band PA. Gunn oscillator provides enough power to make sure this PA can be operated in saturation.

ilent vector network analyzer (VNA) is applied to measure the small signal from 10 MHz to 67 GHz, and Anritsu 37397D VNA with external mixed module 3742A-EW is utilized for high frequency small signal measurement from 70 GHz to 100 GHz. The simulated and measured S-parameters are shown in Fig. 19.

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TABLE III SUMMARY OF THE PUBLISHED D-BAND SI-BASED POWER AMPLIFIERS

: gain larger than 10 dB bandwidth,

: exclusive pads,

: estimated from power gain of cascaded experimental results.

Fig. 24. Measured large signal results at 90 GHz with 18-dBm saturation output power and 9% peak PAE. Fig. 26. Simulated and measured results of the D-band PA S-parameters from . 120 to 150 GHz with

Fig. 25. Measured large signal performances of the W-band PA from 86 GHz to 98 GHz.

The small signal gain achieves 16.3 dB at 60 GHz, and the 3-dB bandwidth covers 25.1 GHz from 48.8 GHz to 73.9 GHz.

In the large signal measurement, the input signal is generated using Agilent E8267D source generator (SG) connecting V-band amplifier module, Spacek Labs SPV-30-17, to provide enough power driving this PA to saturation power. The output signal is analyzed using an Agilent 4418C power meter with V-band power sensor. The simulated and measured power performances at 64 GHz are presented in Fig. 20. The is 19.6 dBm and saturation power achieves 23.2 dBm with peak 10% PAE. The saturation output power and across 54–66 GHz are presented in Fig. 21. It can be observed that the saturation output power and are over 21.5 dBm and 19 dBm respectively in this band. Table I summarizes the performances of this PA compared with other published works. Based on the methodology we proposed, a V-band PA with 32-way power combining is realized and achieves high saturation output power and wideband performance at the same time.

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Fig. 29. The power performances of three test boards of cascaded PAs.

Fig. 27. D-band large signal measurement setup with the custom probe holder for probe to module connected directly. Two chips are cascaded by 150 bond-wire. The left chip provides enough power to drive the right chip to saturation output power.

to make sure this PA can achieve saturation power. Agilent 4418C power meter with W-band power sensor is connected at the output to measure the power as represented in Fig. 23. The simulated and measured power performances at 90 GHz are shown in Fig. 24. The saturation power achieves 18 dBm with peak 9% PAE. The power performances versus frequency are are plotted in Fig. 25. The saturation power and better than 17 dBm and 15 dBm from 86 to 98 GHz respectively. This power level is the highest in CMOS PAs at this frequency. Performance summaries of this W-band PA compared with published works is presented in Table II. Again, with the design method we proposed, this PA not only delivers high output power, but also achieves wideband frequency response in W-band. C. D-Band PA With 8-Way Power Combining [22]

Fig. 28. The measured

vs.

diagram at 140 GHz and 150 GHz.

B. W-Band PA With 16-Way Power Combining [21] This PA is measured through the on-wafer probing testing. All of the transistors are biased with 1.2-V and 0.9-V . Anritsu 37397D VNA with external mixed module 3742A-EW from 70 GHz to 110 GHz is utilized for small signal measurement. The simulated and measured S-parameters of this chip are shown in Fig. 22. The small signal gain is 12.5 dB at 90 GHz, and above 10-dB gain from 75–100 GHz is achieved with 3-dB bandwidth about 26 GHz. To measure large signal performances, a Gunn oscillator connected to an isolator is used to provide enough input power

Fig. 26 presents the simulated and measured S-parameters of and using Agilent this PA biased at VNA 8361C together with OML Inc. D-band frequency extension module through on wafer probing testing. The maximum small signal gain is 16 dB at 150 GHz and the 3-dB bandwidth is wider than 30 GHz. Large signal measurement setup is much difficult in D-band. Fig. 27 shows the measurement setup. In order to measure the saturation power of the PA, the input power must be higher than 0 dBm, while the power source provides a maximum power of only 8 dBm at the input reference plane of DUT. Therefore, two identical PA chips are cascade-connected with bonding wires to support enough input power for the second PA chip. The measured vs. of this cascaded PA at 140 and 150 GHz with and is illustrated in Fig. 28. The highest overall small signal gain is 30.1 dB at 135 GHz under the low input power levels. The maximum is 13.2 dBm at 140 GHz. Because the first PA serves as the gain stage, the output power of the two identical PA chips will be the same as the single chip. The peak PAE of the single PA is 14.6% at 140 GHz, which is estimated from the power gain at with second PA consuming 115.2 mW dc power. The measured is 12 dBm or better and is above 7.5 dBm from

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Finally, we highlight the saturation output power and 3-dB bandwidth performances of these PAs and compare with other publish works using CMOS technology, which are illustrated in Fig. 30. Based on the developed methodology we proposed, these PAs simltaniously achieve high output power and wide 3-dB bandwidth in V-band, W-band, and D-band, respectively. V. CONCLUSIONS In this paper, we develop a methodology for wideband power combining network with impedance transformation. Based on the design procedure, large number transistors combining can be realized to promote saturation output power of PAs with wideband response using CMOS process. To demonstrate the proposed method, a 32-way V-band PA, a 16-way W-band PA, and an 8-way D-band PA are designed and fabricated in 65 nm CMOS technology. The V-band, W-band, and D-band PAs achieve 23.2-dBm, 18-dBm, and 13.2-dBm saturation output power at 64 GHz, 90 GHz and 140 GHz with 3-dB bandwidth of 25 GHz, 26 GHz and 30 GHz, respectively. Based on proposed design method, these PAs exhibit state-of-the-art output power of MMW CMOS PAs at these frequencies with wideband performances. ACKNOWLEDGMENT The authors would like to thank C.-C. Chiong and C.-C. Chuang, both from Academia Sinica Institute of Astronomy and Astrophysics (ASIAA), Taipei, Taiwan, for the assistance in measurement, and K.-Y. Kao and C.-F. Yeh, both from National Taiwan University, Taipei, Taiwan, for their helpful discussions and suggestions. Thanks also goes to Taiwan Semiconductor Manufacturing Company (TSMC), Hsinchu, Taiwan, for the sponsors of the chips fabrication through the TSMC University Shuttle Program. REFERENCES

Fig. 30. Highlight of the saturation output power versus 3-dB bandwidth compared with published CMOS PAs in (a) V-band (b) W-band and (c) D-band.

135–150 GHz, respectively. Fig. 29 presents the measured results of three test boards of cascaded PAs. Although the different gain results from the bonding wires, the power performances cosist under high power operation. Table III summarizes the performaences of this PA compared with other published works in this frequency.

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HSIAO et al.: MILLIMETER-WAVE CMOS POWER AMPLIFIERS

Yuan-Hung Hsiao (S’13) was born in Kaohsiung, Taiwan, in 1988. He received the B.S. degree in communication engineering from National Chung Cheng University, Chia-Yi, Taiwan, in 2010, and the M.S. degree from Graduate Institute of Communication Engineering, National Taiwan University, Taipei, Taiwan, in 2012, where he is currently working toward the Ph.D. degree in communication engineering. His research interests include MMW power amplifiers and MMW transceiver integrations.

Zuo-Min Tsai (S’03–M’07) was born in Maioli, Taiwan, in 1979. He received the B.S. degree in 2001 from the Department of Electrical Engineering, National Taiwan University, Taipei, Taiwain, and the Ph.D. degree in communication engineering from National Taiwan University, Taipei, Taiwan, in 2006. From 2006–2011, he was Postdoctoral Research Fellow with the Graduate Institute of Communication Engineering, National Taiwan University. In July 2011, he joined the faculty of the Department of Electrical Engineering, National Chung Cheng University, where he is currently an assistant professor. His research interests include the design of microwave integrated circuits and microwave systems.

Hsin-Chiang Liao (S’12) was born in Taichung, Taiwan, in 1987. He received the B.S. degree in electrical engineering from National Sun Yat-Sen University, Kaohsiung, Taiwan, in 2010, and the M.S. degree in communication engineering from National Taiwan University, Taipei, Taiwan, in 2012. He is currently with the HTC Corporation, New Taipei City, Taiwan, where he is engaged in the development of hardware RF design. His research interests include RF IC and system designs.

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Jui-Chih Kao (S’08) was born in Taipei, Taiwan, in 1985. He received the B.S. degree in communication engineering from National Central University, Taoyuan, Taiwan, in 2008, and is currently working toward the Ph.D. degree at National Taiwan University, Taipei, Taiwan. He is currently with the Graduate Institute of Communication Engineering, National Taiwan University. His research interests include monolithic microwave and millimeter-wave circuit design.

Huei Wang (S’83–M’87–SM’95–F’06) was born in Tainan, Taiwan, in 1958. He received the B.S. degree in electrical engineering from National Taiwan University, Taipei, Taiwan, in 1980, and the M.S. and Ph.D. degrees in electrical engineering from Michigan State University, East Lansing, MI, USA, in 1984 and 1987, respectively. During his graduate study, he was engaged in the research on theoretical and numerical analysis of electromagnetic radiation and scattering problems. He was also involved in the development of microwave remote detecting/sensing systems. He joined Electronic Systems and Technology Division of TRW Inc. since 1987. He has been an MTS and Staff Engineer responsible for MMIC modeling of CAD tools, MMIC testing evaluation and design and became the Senior Section Manager of MMW Sensor Product Section in RF Product Center. He visited the Institute of Electronics, National Chiao-Tung University, Hsin-Chu, Taiwan, in 1993 to teach MMIC related topics and returned to TRW in 1994. He joined the faculty of the Department of Electrical Engineering of National Taiwan University, Taipei, Taiwan, as a Professor in February 1998. He served as the Director of Graduate Institute of Communication Engineering of National Taiwan University from Aug. 2006 to July 2009. Dr. Wang is a member of the honor society Phi Kappa Phi and Tau Beta Pi. He received the Distinguished Research Award of National Science Council, Taiwan, at 2003. He was the Richard M. Hong Endowed Chair Professor of National Taiwan University in 2005–2007. He was elected as an IEEE Fellow in 2006, and has been appointed as an IEEE Distinguished Microwave Lecturer for the term of 2007–2009. Dr. Wang received the Academic Achievement Award from Ministry of Education, Taiwan, in 2007, and the Distinguished Research Award from Pan Wen-Yuan’s Foundation in 2008. He is currently a National Chair Professor of Ministry of Education, Taiwan, for the term from February 2011 to January 2014.