Chapter 4 Fault Simulation Jin-Fu Li Ad Advanced dR Reliable li bl S Systems t (ARES) Lab. L b Department of Electrical Engineering National Central University Jungli, Taiwan

Outline † Introduction † Fault Simulation „ Parallel Fault Simulation „ Deductive Fault Simulation „ Concurrent Fault Simulation

† Summary

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Simulation † Definition „ Simulation refers to modeling g of a design, g , its function and performance.

† A software simulator is a computer p program; an emulator is a hardware simulator † Simulator is used for design verification „ Validate assumptions „ Verify logic „ Verify performance (timing)

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Levels of Simulation † † † † † †

System level Architecture level Functional level/RTL level G t / t Gate/structural t l llevell Switch/transistor/circuit level Mixed level S stem level System le el

RTL level le el

Gate level le el clk

Reg A

Reg B

a b z

Adder

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c

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Simulation Process

Stimuli

Library

Model

Simulator

Response

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Modeling † Modules, blocks or components described by y „ Input/output (I/O) function „ Delays y associated with I/O / signals g „ Examples: binary adder, Boolean gate, etc.

† Interconnects represent „ Ideal signal carriers or ideal electrical conductors

† Netlist „ A format (or language) that describes a design as an interconnection of modules. Netlist may use hierarchy. y Advanced Reliable Systems (ARES) Lab.

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Example: Full-Adder Netlists c a

e d

b

A B C

HA1

D E

HA

HA2

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F

f

Carry Sum

Jin-Fu Li, EE, NCU

HA; i inputs: t a, b b; outputs: c, f; AND: A1, (a, b), (c); AND: A2,, (d, ( , e), ), (f); ( ); OR: O1, (a, b), (d); NOT: N1, (c), (e);

FA; inputs: A A, B B, C; outputs: Carry, Sum; HA: HA1, (A, B), (D, E); HA: HA2, HA2 (E, (E C), C) (F, (F Sum); OR: O2, (D, F), (Carry);

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Types of Simulation † Compiled simulation „ Applicable to zero-delay combinational logic „ Also used for cycle-accurate synchronous sequential circuits for logic verification „ Efficient for highly active circuits, circuits but inefficient for lowactivity circuits „ High-level (e.g., C language) models can be used

† Event-driven simulation „ Only gates or modules with input events are evaluated (event means a signal change) „ Delays can be accurately simulated for timing verification „ Efficient for low-activity low activity circuits „ Can be extended for fault simulation

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Compiled Simulation † Step 1: „ L Levelize li combinational bi ti l llogic i and d encode d iin a compilable programming language

† Step 2: 2 „

Initialize internal state variables (flip-flops)

† Step 3: „ For each input vector † Set primary input variables † Repeat (until steady-state or max. iterations) „ Execute compiled code

† Report or save computed variables

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Event-Driven Simulation

2

0

e =1

0

1 g =1

2

2

d=0 4

b =1

2

f =0

g 0

4

8

4

Jin-Fu Li, EE, NCU

d, e

d = 1, e = 0

f, g

g=0

5 f=1

g

7 8

Advanced Reliable Systems (ARES) Lab.

c=0

3

6

Time, t

Activity list

1

Time e stack

a =1 c =1

Scheduled events

g=1 10

Time Wheel (Circular Stack)

Current time pointer

max t=0 1

Event link-list

2 3 4 5 6 7

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Efficiency of Event-Driven Simulator † Simulates events (value changes) only † Speed up over compiled compiled-code code can be ten times or more; in large logic circuits about 0.1 to 10% gates become active for an input change

Steady y0 0 to 1 event

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Steady St d 0 (no event)

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Large logic block without activity

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Fault Simulation † Fault simulation „ In general, general simulating a circuit in the presence of faults is known as fault simulation

† The main goals of fault simulation „ Measuring the effectiveness of the test patterns „ Guiding the test pattern generator program „ Generating fault dictionaries

† Outputs O t t off fault f lt simulation i l ti „ Fault coverage - fraction (or percentage) of modeled d l d ffaults lt d detected t t db by test t t vectors t „ Set of undetected faults Advanced Reliable Systems (ARES) Lab.

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Elements of Fault Simulation † The fault simulation process is illustrated as below Fault List

Library

Test Set

Design Model

Fault Simulator

Evaluation

† The fault simulator affects the speed of overall fault simulation Advanced Reliable Systems (ARES) Lab.

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Fault Simulation Scenario † Circuit model: mixed-level „ Mostly y logic g with some switch-level for highg impedance (Z) and bidirectional signals

† Signal g states: logic g „ Two states (0, 1), three states (0, 1, X), four states (0, 1, X, Z), etc.

† Timing: „ Zero Zero-delay delay † For combinational circuits with no feedback

„ Unit-delay y † It can maintain the proper sequencing of signal changes

„ Multiple-delay Advanced Reliable Systems (ARES) Lab.

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Fault Simulation Scenario † Faults „ Mostly y single g stuck-at faults „ Sometimes stuck-open, transition, and pathdelay faults; analog circuit fault simulators are not yet in common use „ Equivalence fault collapsing of single stuck-at f l faults „ Fault dropping -- a fault once detected is d dropped d from f consideration id ti as more vectors t are simulated; fault-dropping may be suppressed for diagnosis „ Fault sampling -- a random sample of faults is simulated s u ated when e the t e circuit c cu t is s large a ge Advanced Reliable Systems (ARES) Lab.

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Serial Fault Simulation † Serial fault simulation algorithm „ Simulate fault-free circuit and save responses. p Repeat following steps for each fault in the fault list † Modify netlist by injecting one fault † Simulate modified netlist, vector by vector, comparing responses with saved responses † If response differs, report fault detection and suspend simulation of remaining vectors

† Advantages „ Easy to implement; needs only a true-value simulator „ Less memory is required Advanced Reliable Systems (ARES) Lab.

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Serial Fault Simulation † Disadvantages „ Much repeated p computation; p ; CPU time prohibitive for VLSI circuits

† Alternative „ Simulate many faults together Test vectors

Fault-free circuit

Comparator

f1 detected?

Comparator

f2 detected?

Comparator

fn detected?

Circuit with fault f1 Circuit with fault f2

Circuit with fault fn Advanced Reliable Systems (ARES) Lab.

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Parallel Fault Simulation † Assumptions „ The simulated circuit consists of only logic gates and all gates have the same delays „ Signals take only binary (0 and 1) values

† Main idea „ Take advantage of the bit-parallelism of logical operations in a digital computer † For a 32-bit machine word, an integer consists of a 32-bit binary vector † A logic AND or OR operation involving two words performs simultaneous AND or OR operations on all respective pairs of bits

† Storage requirement „ One word per line for two-state simulation Advanced Reliable Systems (ARES) Lab.

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Speedup † If the computer word size is N, then N-1 copies of faulty circuit are also generated „ For a total M faults in the circuit, ⎡M /( N − 1)⎤ simulation runs are then necessary

† Speedup over serial fault simulation about N-1 † Disadvantages „ Lacking k the h capability bl to simulate l accurate rise and fall delays of signals „ Not N t suitable it bl ffor circuits i it with ith non-Boolean B l logic l i

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An Example of Parallel Fault Sim. Bit 0: fault fault-free free circuit Bit 1: circuit with c s-a-0 Bit 2: circuit with f s-a-1 1

a

1 1

1

b

1

1

1

1

0

1

0

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c s-a-0 detected

1

e

c ss-a-0 a 0

d

0

0

f

1

0

1

g

0 s-a-1

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0

0

1

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Deductive Fault Simulation † Simulating only the behavior of the faultfree logic circuits † Need only one pass for each test pattern † All ll signal i l values l iin each h ffaulty l circuit i i are deduced from the fault-free circuit values and d the h circuit i i structure † For each test pattern, a deductive procedure is applied to all lines in a levelorder (for combinational logic) from inputs to outputs Advanced Reliable Systems (ARES) Lab.

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Deductive Fault Simulation † Definition „ The fault list LA is defined as the set containing the name or index of every fault that produces an error on line A when the circuit is in its current logic state

† Fault lists are to be propagated from PIs to the POs † A fault list is generated for each signal lines, and updated as necessary with every change in the logic state of the circuit † List events occur when a fault list changes Advanced Reliable Systems (ARES) Lab.

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An Example of Deductive Fault Sim † Consider a 4-input NOR gate with input {ABCD}={0011}, { } { }, given g the initial fault lists as show below LA={a,e}

A B C D

LB={b,c} {b c} E

LC={a,b,c,d} LD={a,d,f} { , ,}

„ The faults that propagate to E are those causing E to be complemented ' „ ∴ LE = ( LA ∪ LB ) ∩ LC ∩ LD = {α | α ∈ LC ∩ LD & α ≠ LA ∪ LB } „ We also have to consider internal faults producing incorrect output for the current good input „ ∴ LE = L'E ∪ {E / 1} = {d , E / 1} Advanced Reliable Systems (ARES) Lab.

Jin-Fu Li, EE, NCU

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Fault List Propagation † Let I be the set of inputs of a gate with output Z, controlling value c, and inversion i. Let C be the sett off iinputs t with ith value l c. The Th fault f lt list li t LZ is i computed as follows: if (C = φ )

then LZ = { ∪ L j } ∪ {Z /( c ⊕ i )}; j∈I

else LZ = ({ ∩ L j } − { ∪ L j }) ∪ {Z /(( c ⊕ i )} j∈C

j∈I −C

0 for 0, f AND/NAND gates t Controlling value:

c=

1, for OR/NOR gates 0, for AND/OR gates

inversion:

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i=

1, for NAND/NOR gates Jin-Fu Li, EE, NCU

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An Example of Deductive Fault Sim Notation: Lk is fault list for line k kn is s-a-n fault on line k

b

1 {b/0}

{a/0} {b/0, { / , c/0} / }

c d {b/0, d/0}

Le = La U Lc U {e/0} = {a/0, b/0, c/0, e/0}

e f

1 0

{b/0, d/0, f/1}

1

g

Lg = (Le Lf ) U {g/0} = {a/0, c/0, e/0, g/0} U

a

1 1

Faults detected by the input vector

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Concurrent Fault Simulation † Event-driven simulation of fault-free circuit and only those parts of the faulty circuit th t differ that diff in i signal i l states t t from f the th faultf lt free circuit. † A list li t per gate t containing t i i copies i off the th gate t from all faulty circuits in which this gate differs List element contains fault ID differs. ID, gate input and output values and internal states, if any. any † All events of fault-free and all faulty circuits are implicitly simulated † Faster than other methods, but uses most memory memory. Advanced Reliable Systems (ARES) Lab.

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An Example of Concurrent Fault Sim a/0 0

a b

1

1

1 1

c d

1

0

1

1 0

b/0 1

c/0 1

0

0

0

1 0

0

1

1

e

1 0

0

1

1

g

a/0

f

0 0

b/0

d/0 f/1

0 1

0 1

Advanced Reliable Systems (ARES) Lab.

e/0

b/0 0

0

1 1

Jin-Fu Li, EE, NCU

1 1 0

0

g/0

c/0 0

1

0 1 1

1

f/1

e/0 0

0

0 1 1

0

1

d/0

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Summary † Fault simulator is an essential tool for test d development l t † The main goals of fault simulation „ Measuring the effectiveness of the test patterns „ Guiding the test pattern generator program „ Generating fault dictionaries

† Concurrent fault simulation algorithm offers the best choice

Advanced Reliable Systems (ARES) Lab.

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