Impact of Thermal Processing on Silicon Wafer Surface Roughness Larry W. Shivea and Brian L. Gilmorea a MEMC Electronic Materials, Inc., St. Peters, MO 63376, USA Very flat silicon wafers with nanometer scale roughness are important during semiconductor device patterning onto the wafer. Recent reports have shown that thermal processing at high temperature in H2 or H2-Ar mixtures may be used to reduce roughness of silicon wafers at short length scales such as 1- 10μm. This paper reports the impact upon roughness of high temperature heat treatment in a diffusion furnace in mixtures of hydrogen and argon. Experiments show surface roughness is reduced during high temperature processing and is independent of argon or argonhydrogen processing environment for length scales in the range of 0.1-100μm. Introduction Most semiconductor devices must be built on very flat wafers with nanometer scale roughness in order that the region of the surface that is being processed at any given time is within the depth of field of the optics being used to image the device patterns onto the wafer (1). Chemo-mechanical polishing (CMP) is the standard method for reducing roughness but typically requires >0.5 microns of stock removal (2). Some recent reports have shown that thermal processing at high temperature in H2 or H2-Ar mixtures may be used to reduce roughness of finish polished, silicon wafers at length scales such as