ENEE 359a Lecture/s 3-5 Transistors & CMOS Inverter Bruce Jacob University of Maryland ECE Dept. SLIDE 1

ENEE 359a Digital VLSI Circuits P/N Junction, MOS Transistors, CMOS Inverter Prof. Bruce Jacob [email protected]

Credit where credit is due: Slides contain original artwork (© Jacob 2004) as well as material taken liberally from Irwin & Vijay’s CSE477 slides (PSU), Schmit & Strojwas’s 18-322 slides (CMU), Wolf’s slides for Modern VLSI Design, and/or Rabaey’s slides (UCB). Device physics: http://hyperphysics.phy-astr.gsu.edu/hbase/solids/sselcn.html UNIVERSITY OF MARYLAND

ENEE 359a Lecture/s 3-5 Transistors & CMOS Inverter

Overview

Bruce Jacob University of Maryland ECE Dept. SLIDE 2

UNIVERSITY OF MARYLAND

•

Electrons & holes, bands & band gaps, insulators, conductors, semiconductors

•

Silicon crystal lattice & doping

•

P/N junction & parasitic capacitance

•

n-type/n-channel MOSFET

•

Timing analysis of MOSFET, capacitance

•

Body effect, series-connected FETs

•

CMOS inverter: timing, switching threshold, transistor sizing

•

Dynamic behavior (preview)

ENEE 359a Lecture/s 3-5 Transistors & CMOS Inverter

What Is Conductivity?

Bruce Jacob University of Maryland ECE Dept.

Perspective from Band Theory of Solids:

Energy of electrons

Large band gap (not “Gap Band”) between valence and conduction bands in insulator material suggests that, at ordinary temperatures, no electrons can reach conduction band (i.e. material won’t conduct)

Conduction Band

In semiconductors, the band gap is small enough that thermal energy can bridge gap for small fraction of electrons.

SLIDE 3

In conductors, there is no band gap (conduction and valence bands overlap).

INSULATOR

SEMICONDUCTOR

Fermi level

CONDUCTOR Fermi level

Conduction Band Valence Band UNIVERSITY OF MARYLAND

Valence Band

Conduction Band Valence Band

ENEE 359a Lecture/s 3-5 Transistors & CMOS Inverter

Silicon, Specifically

Bruce Jacob University of Maryland ECE Dept. SLIDE 4

Si

14 protons in nucleus 4 valence electrons

UNIVERSITY OF MARYLAND

ENEE 359a Lecture/s 3-5 Transistors & CMOS Inverter

Silicon, Specifically

Bruce Jacob University of Maryland ECE Dept.

Si

SLIDE 5

Si

Shared electrons of covalent bonds

UNIVERSITY OF MARYLAND

Si

Si

Si

ENEE 359a Lecture/s 3-5 Transistors & CMOS Inverter

Silicon, Specifically

Bruce Jacob University of Maryland ECE Dept.

Silicon Lattice (artistic license exploited) Si

Si

Si

Si

Si

Si

Si

Si

Si

Si

Si

Si

Si

Si

Si

Si

Si

Si

Si

Si

SLIDE 6

UNIVERSITY OF MARYLAND

ENEE 359a Lecture/s 3-5 Transistors & CMOS Inverter

Silicon, Specifically

Bruce Jacob University of Maryland ECE Dept.

Silicon Lattice — It is a semiconductor Si

Si

Si

Si

Si

Si

Si

Si

Si

Si

Si

Si

Si

Si

Si

Free Si electron

Si

SLIDE 7

Hole Si UNIVERSITY OF MARYLAND

Si

Si

ENEE 359a Lecture/s 3-5 Transistors & CMOS Inverter

Silicon, Specifically

Bruce Jacob University of Maryland ECE Dept.

Semiconductor current: electron/hole flow

SLIDE 8

UNIVERSITY OF MARYLAND

Si

Si

Si

Si

Si

Si

Si

Si

Si

Si

Si

Si

ENEE 359a Lecture/s 3-5 Transistors & CMOS Inverter

Silicon, Specifically

Bruce Jacob University of Maryland ECE Dept.

Perspective from Band Theory of Solids: Energy of electrons

SLIDE 9

0K (no electrons in conduction band)

Conduction Band Fermi level

Valence Band

• UNIVERSITY OF MARYLAND

300K

Free electrons

Conduction Band

1.09 eV

Holes

Valence Band

Conductivity is non-zero; mobile electrons/holes in conduction/valence band; can be increased w/ doping

ENEE 359a Lecture/s 3-5 Transistors & CMOS Inverter

Silicon, Specifically

Bruce Jacob University of Maryland ECE Dept.

Doping: small % of foreign atoms in lattice

SLIDE 10

P

B

Breaks up regular lattice, produces dramatic changes in electrical properties •

•

UNIVERSITY OF MARYLAND

Donors: pentavalent impurities (5 valence electrons) produce n-type semiconductors by adding electrons. E.g. antimony, arsenic, phosphorus Acceptors: trivalent impurities (3 valence electrons) produce p-type semiconductors by adding electron deficiencies (“holes”). E.g. boron, aluminum, gallium

ENEE 359a Lecture/s 3-5 Transistors & CMOS Inverter

P-Type Semiconductor

Bruce Jacob University of Maryland ECE Dept.

Si

Acceptor impurity creates a hole

SLIDE 11

Si

B

Si

Si

Conduction Band Extra hole energy levels

Valence Band Addition of acceptor impurities contributes hole energy levels low in the semiconductor band gap so that electrons can be easily excited from the valence band into these levels, leaving mobile holes in the valence band. This shifts the effective Fermi level to a point about halfway between the acceptor levels and the valence band. Electrons can be elevated from the valence band to the holes in the band gap with the energy provided by an applied voltage. Since electrons can be exchanged between the holes, the holes are said to be mobile. Holes are said to be the “majority carriers” for current flow in a p-type semiconductor. UNIVERSITY OF MARYLAND

ENEE 359a Lecture/s 3-5 Transistors & CMOS Inverter

N-Type Semiconductor

Bruce Jacob University of Maryland ECE Dept.

Si Donor impurity creates free electron

SLIDE 12

Si

P

Si

Si

Conduction Band Extra electron energy levels

Valence Band Addition of donor impurities contributes electron energy levels high in the semiconductor band gap so that electrons can be easily excited into the conduction band. This shifts the Fermi level to a point about halfway between the donor levels and the conduction band. Electrons can be elevated to the conduction band with the energy provided by an applied voltage and move through the material. Electrons are said to be the “majority carriers” for current flow in an n-type semiconductor. UNIVERSITY OF MARYLAND

ENEE 359a Lecture/s 3-5 Transistors & CMOS Inverter

One Way to Think About It

Bruce Jacob University of Maryland ECE Dept.

Acceptor side

Donor side

Conduction Band

Conduction Band

SLIDE 13

Extra hole energy levels Extra electron energy levels

Valence Band

P-type •

•

UNIVERSITY OF MARYLAND

Valence Band

N-type

P-type: Conduction band is pulled down close to the valence band by the creation of available holes (willing acceptors of free electrons) N-type: Valence band is pushed up close to the conduction band by the addition of mobile electrons

ENEE 359a Lecture/s 3-5 Transistors & CMOS Inverter

The P/N Junction

Bruce Jacob University of Maryland ECE Dept.

Acceptor side

Donor side

Conduction Band

Conduction Band

SLIDE 14

Extra hole energy levels Extra electron energy levels

Valence Band

P-type •

•

UNIVERSITY OF MARYLAND

Valence Band

N-type

P-type: extra holes in band gap allow excitation of valence-band electrons, leaving mobile holes in valence band N-type: electron energy levels near the top of the band gap allow easy excitation of electrons into conduction band

ENEE 359a Lecture/s 3-5 Transistors & CMOS Inverter Bruce Jacob University of Maryland ECE Dept.

The P/N Junction Acceptor side Donor side

Conduction Band

SLIDE 15

Extra hole energy levels

Conduction Band Extra electron energy levels

Valence Band

Valence Band

Diode P-type silicon

N-type silicon

p-n junction

UNIVERSITY OF MARYLAND

ENEE 359a Lecture/s 3-5 Transistors & CMOS Inverter

The P/N Junction

Bruce Jacob University of Maryland ECE Dept.

DEPLETION REGION

SLIDE 16

If not touching, nothing happens

UNIVERSITY OF MARYLAND

ENEE 359a Lecture/s 3-5 Transistors & CMOS Inverter

The P/N Junction

Bruce Jacob University of Maryland ECE Dept.

DEPLETION REGION

SLIDE 17

With a connection, electrons from n-region in conduction band diffuse across junction and combine with holes in p-region (why doesn’t this continue indefinitely?) UNIVERSITY OF MARYLAND

ENEE 359a Lecture/s 3-5 Transistors & CMOS Inverter

The P/N Junction

Bruce Jacob University of Maryland ECE Dept.

DEPLETION REGION Negative ion

Positive ion

SLIDE 18

Mobile hole

depletion region

Mobile electron

Ions are formed on both sides of junction (negative ion from filled hole; positive ion from removed electron). This forms a space charge that impedes further electron flow. UNIVERSITY OF MARYLAND

ENEE 359a Lecture/s 3-5 Transistors & CMOS Inverter

The P/N Junction

Bruce Jacob University of Maryland ECE Dept.

DEPLETION REGION

SLIDE 19

Cj

UNIVERSITY OF MARYLAND

two plates of a capacitor

Parasitic capacitance:

Built-in junction potential:

C j0 C j = -----------------------m Vd 1 – -----φ0

N A N D  φ 0 = φ T ⋅ ln --------------- n2  i

ENEE 359a Lecture/s 3-5 Transistors & CMOS Inverter

The P/N Junction

Bruce Jacob University of Maryland ECE Dept.

BIAS EFFECT on DEPLETION REGION Equilibrium

SLIDE 20

P

N depletion region

Conduction Band Extra hole energy levels

Valence Band

Conduction Band Extra electron energy levels

Valence Band • • UNIVERSITY OF MARYLAND

Upward = increased electron energy (must supply energy to make electron go up or hole to go down) Drift-diffusion equilibrium (current is flowing)

ENEE 359a Lecture/s 3-5 Transistors & CMOS Inverter

The P/N Junction

Bruce Jacob University of Maryland ECE Dept. SLIDE 21

BIAS EFFECT on DEPLETION REGION Forward Bias P

N depletion region still exists

Conduction Band

Conduction Band

Extra hole energy levels Extra electron energy levels

Valence Band Valence Band P-side is made more positive relative to N-side, making it “downhill” to move an electron across the junction. Electron on N-side can fill a vacancy (“hole”) on P-side & move from hole to hole to the left to positive terminal (hole “moves” right).

UNIVERSITY OF MARYLAND

ENEE 359a Lecture/s 3-5 Transistors & CMOS Inverter

The P/N Junction

Bruce Jacob University of Maryland ECE Dept. SLIDE 22

BIAS EFFECT on DEPLETION REGION Reverse Bias P

N depletion region increases in size until new potential = applied bias

Conduction Band Extra hole energy levels

Valence Band Conduction Band P-side is made more negative relative to N-side, making it “uphill” to move an electron across the junction. Applied voltage impedes the flow of N-region electrons across the p/n junction. Initial transient electron flow is left to right; it stops when potential (widening depletion region) equals the applied voltage. UNIVERSITY OF MARYLAND

Extra electron energy levels

Valence Band

ENEE 359a Lecture/s 3-5 Transistors & CMOS Inverter Bruce Jacob

MOS Transistors MOS Transistor, reverse-biased:

University of Maryland ECE Dept. SLIDE 23

N-Doped Region [mobile electrons]

PN Junction

n

P-Doped Region [mobile holes]

p-doped semiconductor substrate UNIVERSITY OF MARYLAND

ENEE 359a Lecture/s 3-5 Transistors & CMOS Inverter Bruce Jacob

MOS Transistors MOS Transistor, reverse-biased:

University of Maryland ECE Dept. SLIDE 24

VDD

VDD P-Doped Region [acceptor holes]

n

N-Doped Regions [donor electrons]

n

p-doped semiconductor substrate UNIVERSITY OF MARYLAND

VSS

ENEE 359a Lecture/s 3-5 Transistors & CMOS Inverter Bruce Jacob

MOS Transistors MOS Transistor, reverse-biased:

University of Maryland ECE Dept. SLIDE 25

VDD

VDD Insulator (gate oxide)

n

n

p-doped semiconductor substrate UNIVERSITY OF MARYLAND

VSS

ENEE 359a Lecture/s 3-5 Transistors & CMOS Inverter Bruce Jacob

MOS Transistors NMOS Transistor with gate:

University of Maryland ECE Dept.

0

SLIDE 26

+

+ Conductor

Insulator (gate oxide)

n

n

p-doped semiconductor substrate UNIVERSITY OF MARYLAND

0

ENEE 359a Lecture/s 3-5 Transistors & CMOS Inverter Bruce Jacob

MOS Transistors NMOS Transistor with bias voltages:

University of Maryland ECE Dept.

0

SLIDE 27

0

+ Conductor

Insulator (gate oxide)

n

n

p-doped semiconductor substrate UNIVERSITY OF MARYLAND

0

ENEE 359a Lecture/s 3-5 Transistors & CMOS Inverter Bruce Jacob

MOS Transistors NMOS Transistor with bias voltages:

University of Maryland ECE Dept.

+

SLIDE 28

0

+ Gate (conductor)

Insulator (gate oxide)

n

n CURRENT

p-doped semiconductor substrate UNIVERSITY OF MARYLAND

0

ENEE 359a Lecture/s 3-5 Transistors & CMOS Inverter Bruce Jacob

MOS Transistors NMOS Transistor, two views:

University of Maryland ECE Dept.

Length

SLIDE 29

Width

TOP VIEW Gate

FOX n SIDE VIEW UNIVERSITY OF MARYLAND

Gate oxide n

p-doped semiconductor substrate

FOX

ENEE 359a Lecture/s 3-5 Transistors & CMOS Inverter Bruce Jacob

MOS Transistors NMOS Transistor with bias voltages:

University of Maryland ECE Dept.

Gate Source

Drain

SLIDE 30

n

channel

VSS

n

p-doped semiconductor substrate

Gate Source

0

Gate Drain

0

V>0

Source

0

Drain

V>0

Electron Flow UNIVERSITY OF MARYLAND

V>0

ENEE 359a Lecture/s 3-5 Transistors & CMOS Inverter Bruce Jacob

MOS Transistors PMOS Transistor with bias voltages:

University of Maryland ECE Dept.

Gate Drain

Source

SLIDE 31

p

channel

VDD

p

n-doped semiconductor substrate

Gate Drain

0

Gate Source

VDD

V>0

Drain

0

Source

V0

ENEE 359a Lecture/s 3-5 Transistors & CMOS Inverter Bruce Jacob University of Maryland ECE Dept.

MOS Transistors MOS Transistors: Gate

Gate Source

Source

Drain

Drain

SLIDE 32

n

channel

VSS

n

p-doped semiconductor substrate

p

PMOS

Gate

UNIVERSITY OF MARYLAND

Gate

Drain

Substrate

VDD

p

n-doped semiconductor substrate

NMOS Source

channel

Source

Drain

Substrate

ENEE 359a Lecture/s 3-5 Transistors & CMOS Inverter

0.25 µm transistor (Bell Labs)

Bruce Jacob University of Maryland ECE Dept.

Silicide

SLIDE 33

Poly Gate oxide

Source & Drain

Poly+silicide = “polycide gate” (lower R) UNIVERSITY OF MARYLAND

ENEE 359a Lecture/s 3-5 Transistors & CMOS Inverter Bruce Jacob

MOS Behavior VSource

University of Maryland ECE Dept.

VDrain

Gate n+

n+

SLIDE 34

p (bulk)

UNIVERSITY OF MARYLAND

VGate

Depletion Regions

ENEE 359a Lecture/s 3-5 Transistors & CMOS Inverter

MOS Behavior VGate

VSource

Bruce Jacob University of Maryland ECE Dept.

VDrain

Gate n+

n+

SLIDE 35

p (bulk)

VS = 0V

Depletion Regions

VG = 0.5V

VD = 0V

Charge Density Gate Oxide Substrate (p-type)

Depletion layer

x (depth) UNIVERSITY OF MARYLAND

ENEE 359a Lecture/s 3-5 Transistors & CMOS Inverter

MOS Behavior VSource

Bruce Jacob

Channel

University of Maryland ECE Dept.

VGate VDrain Free electrons

Gate n+

SLIDE 36

n+

Depletion Regions

p (bulk)

VS = 0V

Inversion Layer forms when

VGS > VT

Assume VT = 0.75V (threshold voltage)

VD = 0V

VG = 1V

Charge Density Gate Oxide Substrate (p-type)

Inversion layer

Depletion layer

x (depth) UNIVERSITY OF MARYLAND

ENEE 359a Lecture/s 3-5 Transistors & CMOS Inverter

MOS Behavior: linear region VGate

VSource

Bruce Jacob University of Maryland ECE Dept.

VDrain

Gate n+

SLIDE 37

n+

Inversion Layer existence requires VGS – VT > V(y)

p (bulk)

VD = 0.001V

VG = 1V

VS = 0V

Assume VT = 0.75V (threshold voltage)

ε ox  W  = µ n ------- ----- ( V GS – V T )V DS t ox  L  dielectric constant

electron mobility

I DS

oxide thickness

VGS – V(y)

V(y) 1V

VDS

0.75V

y (channel)

y (channel)

True when VGS > VT & VDS V(y)

p (bulk)

Assume VT = 0.75V (threshold voltage)

VD = 0.15V VG = 1V VS = 0V dielectric constant electron mobility ε ox W 1 2 I DS = µ n -------  ----- ( V GS – V T )V DS – --- V DS t ox  L  2 oxide thickness

VGS – V(y)

V(y) VDS

1V 0.85V 0.75V

y (channel)

y (channel)

True when VGS > VT & VDS ≤ VGS – VT UNIVERSITY OF MARYLAND

ENEE 359a Lecture/s 3-5 Transistors & CMOS Inverter

MOS Behavior: saturation VGate

VSource

Bruce Jacob University of Maryland ECE Dept.

VDrain

Gate n+

n+

SLIDE 39

Inversion Layer “pinched off” when

VDS = VGS – VT

p (bulk)

VS = 0V I DS

Assume VT = 0.75V (threshold voltage)

VD = 0.25V

VG = 1V

1  ε ox  W   2 = --- µ n ------- ----- ( V GS – V T ) 2  t ox  L   VGS – V(y)

V(y) VDS

1V 0.75V

y (channel)

y (channel)

True when VGS > VT & VDS = VGS – VT UNIVERSITY OF MARYLAND

ENEE 359a Lecture/s 3-5 Transistors & CMOS Inverter

MOS Behavior: modulation VGate

VSource

Bruce Jacob University of Maryland ECE Dept.

VDrain

Gate n+

n+

SLIDE 40

Inversion Layer does not exist here

VDS ≥ VGS – VT

p (bulk)

VS = 0V I DS V(y)

Assume VT = 0.75V (threshold voltage)

VD = 0.35V

VG = 1V

1  ε ox  W   2 ---------= µ ( V – V T ) ( 1 + λ V DS ) 2  n t ox  L   GS effective channel length decreases

VDS

1V

y (channel)

0.75V 0.65V

VGS – V(y)

length modulation factor

over this range, effective gate potential is not sufficient to create inversion layer

y (channel)

True when VGS > VT & VDS ≥ VGS – VT UNIVERSITY OF MARYLAND

ENEE 359a Lecture/s 3-5 Transistors & CMOS Inverter

Example of Drain Current

Bruce Jacob University of Maryland ECE Dept.

Values for generic 0.5 µm process: ε ox k’ (transconductance) = µ n ------t ox

VT

n-type

k’n = 73 µA/V2

0.7V

p-type

k’p = 21 µA/V2

-0.8V

SLIDE 41

Assume W/L = 3/2, VGS = 2V, find IDS for NMOS device at saturation point: 1 W 2 I DS = ---  k' ----- ( V GS – V T ) 2 L  1 µA 3 2 I DS = ---  73 -------2   --- ( 2V – 0.7V ) = 93µA 2  V   2 UNIVERSITY OF MARYLAND

ENEE 359a Lecture/s 3-5 Transistors & CMOS Inverter

NMOS I-V Plot

Bruce Jacob University of Maryland ECE Dept.

2.5

X 10-4

VGS = 2.5V

ID (A)

VGS = 2.0V

1.5 1

VGS = 1.5V

0.5

VGS = 1.0V

Linear dependence

2

SLIDE 42

0 0

0.5

1

1.5

2

2.5

VDS (V) NMOS transistor, 0.25um, Ld = 0.25um, W/L = 1.5, VDD = 2.5V, VT = 0.4V

UNIVERSITY OF MARYLAND

ENEE 359a Lecture/s 3-5 Transistors & CMOS Inverter Bruce Jacob University of Maryland ECE Dept.

PMOS I-V Plot l

All polarities of all voltages and currents are reversed -2

VDS (V)

-1

0 0

VGS = -1.0V

-0.2

VGS = -1.5V

-0.4 -0.6

ID (A)

SLIDE 43

VGS = -2.0V -0.8

VGS = -2.5V

-1 X 10-4

PMOS transistor, 0.25um, Ld = 0.25um, W/L = 1.5, VDD = 2.5V, VT = -0.4V

Note y-axis scale (because W/Lp = W/Ln) (drive current: ID when VGS = VDS = VDD) UNIVERSITY OF MARYLAND

ENEE 359a Lecture/s 3-5 Transistors & CMOS Inverter

Review: RC Circuits

Bruce Jacob University of Maryland ECE Dept. SLIDE 44

VC = ?

R

vc(t)

V

C t

v out(t) = ( 1 – e

–t ⁄ τ

)V

τ = RC

RC time-constant: dictates how rapidly the output voltage reacts to the voltage rise on input (step function). Larger RC, slower response

UNIVERSITY OF MARYLAND

ENEE 359a Lecture/s 3-5 Transistors & CMOS Inverter

Capacitances VGate

VSource

Bruce Jacob University of Maryland ECE Dept.

VDrain

Gate n+

SLIDE 45

n+ Gate is capacitor

p (bulk) Depletion Regions are capacitors

C gate

WLε ox = ----------------t ox

C SC

Aε si = ---------t si

C diff

I ⋅ τc = ----------V th

Yes, there are others … Result: parasitic capacitances hinder switching speeds UNIVERSITY OF MARYLAND

ENEE 359a Lecture/s 3-5 Transistors & CMOS Inverter

Body Effect

Bruce Jacob

VSource > 0

University of Maryland ECE Dept.

VGate

VDrain

Gate n+

SLIDE 46

n+

p (bulk/body)

•

•

Suppose source and body are not in equilibrium: reverse bias increases size of depletion region around that diode (and changes its parasitic capacitance) Called “body effect” … it changes the threshold voltage for that device 2qε si N A ∆V t = ------------------------- ( φ S + V SB – φ S ) C ox

But can it happen? UNIVERSITY OF MARYLAND

ENEE 359a Lecture/s 3-5 Transistors & CMOS Inverter

Body Effect

Bruce Jacob

NAND gate

University of Maryland ECE Dept.

VDD

SLIDE 47

A

B

A

output #A

GNDeffective for #A B

•

• UNIVERSITY OF MARYLAND

#B

If #B propagates signal in non-zero time, the effective source voltage for #A can go positive (higher than ground) Perspective: Things start to get interesting when you start connecting these things together …

ENEE 359a Lecture/s 3-5 Transistors & CMOS Inverter

CMOS Inverter Layout I

Bruce Jacob University of Maryland ECE Dept. SLIDE 48

N-regions for source, drain

Gate (poly)

P-regions and gate for PMOS device

input

GND NMOS

output

PMOS N-Well

Cut line

UNIVERSITY OF MARYLAND

VDD

ENEE 359a Lecture/s 3-5 Transistors & CMOS Inverter

CMOS Inverter Layout II

Bruce Jacob

VDD

University of Maryland ECE Dept.

+

SLIDE 49

a

tub ties out transistors a

out

GND

Another view (note: wells/tubs not shown) UNIVERSITY OF MARYLAND

ENEE 359a Lecture/s 3-5 Transistors & CMOS Inverter

CMOS Inverter: Analysis VDD

Bruce Jacob

Rp

University of Maryland ECE Dept.

VDD

SLIDE 50

Vin = 0 CL

Rp Vout VDD

Rn

CL (load) Vin = VDD CL Rn

• UNIVERSITY OF MARYLAND

Gate response time is determined by the time to charge CL through Rp or discharge CL through Rn

ENEE 359a Lecture/s 3-5 Transistors & CMOS Inverter

CMOS Inverter: Transfer Plot

Bruce Jacob University of Maryland ECE Dept.

NMOS off PMOS res

2.5

NMOS sat PMOS res

2

Vout (V)

SLIDE 51

1.5

NMOS sat PMOS sat

1 NMOS res PMOS sat

0.5

NMOS res PMOS off

0 0

0.5

1

1.5

Vin (V)

UNIVERSITY OF MARYLAND

2

2.5

ENEE 359a Lecture/s 3-5 Transistors & CMOS Inverter

CMOS Inverter: Current

Bruce Jacob University of Maryland ECE Dept.

NMOS off PMOS res

2.5

NMOS sat PMOS res

2

Vout (V)

SLIDE 52

1.5

NMOS sat PMOS sat

1 NMOS res PMOS sat

0.5

NMOS res PMOS off

0 0

0.5

1

1.5

Vin (V)

UNIVERSITY OF MARYLAND

2

2.5

ENEE 359a Lecture/s 3-5 Transistors & CMOS Inverter

Properties of CMOS

Bruce Jacob University of Maryland ECE Dept. SLIDE 53

•

Full rail-to-rail swing -> high noise margins

•

Logic levels not dependent upon the relative device sizes -> transistors can be minimum size -> ratioless Always a path to Vdd or GND in steady state -> low Ω range) -> output impedance (output resistance in kΩ large fan-out (albeit with degraded performance) Extremely high input resistance (gate of MOS transistor is near perfect insulator) -> nearly zero steady-state input current

•

•

UNIVERSITY OF MARYLAND

•

No direct path steady-state between power and ground -> no static power dissipation

•

Propagation delay function of load capacitance and resistance of transistors

ENEE 359a Lecture/s 3-5 Transistors & CMOS Inverter

Capacitive Load, etc.

Bruce Jacob University of Maryland ECE Dept. SLIDE 54

Fan-out Fan-in

Fan-out: number of gates connected to the output of the driving date •

Gates with large fan-out are slower

Fan-in: the number of inuts to the gate •

UNIVERSITY OF MARYLAND

Gates with large fan-in are bigger and slower

ENEE 359a Lecture/s 3-5 Transistors & CMOS Inverter Bruce Jacob

Aside:is capacitance all bad? Slows down output …

University of Maryland ECE Dept.

Bigger capacitor, more charge to change voltage => SLOWER

SLIDE 55

… but stabilizes power supply Bigger capacitor, more charge to change voltage => more stable power-supply voltage levels

Capacitors are de facto frequency filters … can be a good thing (“bypass caps”) UNIVERSITY OF MARYLAND

ENEE 359a Lecture/s 3-5 Transistors & CMOS Inverter

Transistor Sizing I

Bruce Jacob

W

University of Maryland ECE Dept. Source

SLIDE 56

L/Wmin

2W L

L Drain

(R1,C1)

(R2,C2)

The electrical characteristics of transistors determine the switching speed of a circuit •

Need to select the aspect ratios (W/L)n and (W/L)p of every FET in the circuit

Define Unit Transistor (R1, C1) • • • UNIVERSITY OF MARYLAND

L/Wmin-> highest resistance R2= R1 ÷ 2 and C2= 2 • C1 Separate nFET and pFET unit transistors

ENEE 359a Lecture/s 3-5 Transistors & CMOS Inverter Bruce Jacob University of Maryland ECE Dept.

Long MOSFETs poly

Short

S

Long

S

metal active

SLIDE 57

G

G

n-well via

D

D S

Really Long D UNIVERSITY OF MARYLAND

G

ENEE 359a Lecture/s 3-5 Transistors & CMOS Inverter Bruce Jacob University of Maryland ECE Dept.

Wide MOSFETs poly

Narrow

S

Wide

S

metal active

G

G

SLIDE 58

n-well via

D

G

D S

Really Wide UNIVERSITY OF MARYLAND

D

ENEE 359a Lecture/s 3-5 Transistors & CMOS Inverter

Transistor Sizing II

Bruce Jacob University of Maryland ECE Dept.

Resistance of MOSFET: 1 L  R n = ---------------------------------------------- ----µ n C ox ( V GS – V Tn )  W 

SLIDE 59

•

Increasing W decreases the resistance; allows more current to flow

Oxide capacitance C ox = ε ox ⁄ t ox [F/cm2] Gate capacitance C G = C ox WL [F] W W Transconductance β n = µ n C ox  ----- = k' n  -----  L  L (units [A/V2]) UNIVERSITY OF MARYLAND

ENEE 359a Lecture/s 3-5 Transistors & CMOS Inverter

Transistor Sizing II

Bruce Jacob University of Maryland ECE Dept. SLIDE 60

nFET vs. pFET 1 R n = ------------------------------------β n ( V DD – V Tn ) 1 R p = ---------------------------------------β p ( V DD – V Tp ) µn ----- = r µp

W  β n = µ n C ox ---- Ln W β p = µ p C ox  -----  Lp Typically (2 .. 3)

(µ is the carrier mobility through device)

UNIVERSITY OF MARYLAND

ENEE 359a Lecture/s 3-5 Transistors & CMOS Inverter

Inverter Switching Point

Bruce Jacob University of Maryland ECE Dept.

Where Vin = Vout NMOS off PMOS res

2.5

SLIDE 61

NMOS sat PMOS res

Vout (V)

2 1.5

NMOS sat PMOS sat

1 NMOS res PMOS sat

0.5

NMOS res PMOS off

0 0

0.5

1

1.5

Vin (V) UNIVERSITY OF MARYLAND

2

2.5

ENEE 359a Lecture/s 3-5 Transistors & CMOS Inverter

Inverter Switching Point

Bruce Jacob University of Maryland ECE Dept. SLIDE 62

At all points IDSn = IDSp (drain currents) At switching point, Vin = Vout = Vsp βn βp 2 2 ------ ( V SP – V Tn ) = ------ ( V DD – V SP – V Tp ) 2 2 βn ------ ⋅ V Tn + ( V DD – V Tp ) βp V SP = ------------------------------------------------------------βn 1 + -----βp For Vsp = Vdd/2, assuming VTn= VTp, ßn = ßp => Wp ≈ 2–3Wn (equal drive currents, equal Reff: Rn = Rp)

UNIVERSITY OF MARYLAND

ENEE 359a Lecture/s 3-5 Transistors & CMOS Inverter

The Result (Wp = 2Wn, .25µm)

Bruce Jacob University of Maryland ECE Dept.

In metal1-poly via

metal1

polysilicon

SLIDE 63

metal2

VDD

pdiff PMOS (4/.24 = 16/1) NMOS (2/.24 = 8/1) metal1-diff via ndiff GND metal2-metal1 via

UNIVERSITY OF MARYLAND

ENEE 359a Lecture/s 3-5 Transistors & CMOS Inverter

The Result II (Wp = 3Wn)

Bruce Jacob University of Maryland ECE Dept.

VDD

PMOS 1.125/0.25

SLIDE 64

1.2µm λ =2λ In

Out Metal1

Polysilicon

NMOS 0.375/0.25

GND

PMOS devices 3x larger than NMOS devices UNIVERSITY OF MARYLAND

ENEE 359a Lecture/s 3-5 Transistors & CMOS Inverter

Delay Definitions

Bruce Jacob

Vin University of Maryland ECE Dept.

Vout

Vin

Propagation Delay tp = (tpHL + tpLH) / 2

SLIDE 65

50%

Input Waveform

Vout

time

tpLH

tpHL

90%

50% Signal slopes Output Waveform UNIVERSITY OF MARYLAND

10% tf

tr

time

ENEE 359a Lecture/s 3-5 Transistors & CMOS Inverter

Inverter Switching Delay

Bruce Jacob VDD

University of Maryland ECE Dept. SLIDE 66

VDD

Rp CL

VOUT

VOUT

CL

CL

Rn Charging: Vout rising

Discharging: Vout falling

If (W/L)p = r(W/L)n then ßn = ßp (and Rn = Rp) … symmetric inverter Make pFET bigger (wider) by factor of r

UNIVERSITY OF MARYLAND

ENEE 359a Lecture/s 3-5 Transistors & CMOS Inverter

Inverter Switching Delay

Bruce Jacob VDD

University of Maryland ECE Dept. SLIDE 67

VDD

Rp CL

VOUT

VOUT

CL

CL

Rn Charging: Vout rising

Discharging: Vout falling

tpLH = ln(2) Rp CL = 0.69 Rp CL tpHL = ln(2) Rn CL = 0.69 Rn CL tp = (tpHL + tpLH)/2 = 0.69 CL(Rn + Rp)/2 (note: the ln(2)RC term comes from first-order analysis of simple RC circuit’s respose to step input ... time for output to reach 50% value)

UNIVERSITY OF MARYLAND

ENEE 359a Lecture/s 3-5 Transistors & CMOS Inverter

Inverter Pair

Bruce Jacob University of Maryland ECE Dept.

VDD

PMOS 1.125/0.25

SLIDE 68

1.2µm λ =2λ In

Out Metal1

Polysilicon

NMOS 0.375/0.25

UNIVERSITY OF MARYLAND

GND

ENEE 359a Lecture/s 3-5 Transistors & CMOS Inverter

Inverter Pair

Bruce Jacob

Vout

University of Maryland ECE Dept. SLIDE 69

Vout 2.5V Vh Vth

Vtl Vl Output Waveform

UNIVERSITY OF MARYLAND

ENEE 359a Lecture/s 3-5 Transistors & CMOS Inverter

Dynamic Power Dissipation

Bruce Jacob University of Maryland ECE Dept.

VDD

VDD

Rp

Ctot

SLIDE 70

VOUT

VOUT

CL

CL

Rn

T

Charging: Vout rising

I avg

Q Ctot V DD ⋅ C tot = ------------ = -----------------------T T 2

P avg = V DD ⋅ I avg UNIVERSITY OF MARYLAND

Discharging: Vout falling

C tot ⋅ V DD 2 = ------------------------ = C tot ⋅ V DD ⋅ f CLK T