EE251: Thursday October 15 • TIMER MODULE: SysTick – Section 12.4 and 18 in text describes our SysTick – Section 2.5 of Valvano’s Real Time Interfacing text – Several SysTick slides are from Dr. Jonathan Valvano, University of Texas

• Higher Frequency Clock via Phase Locked Loop • SysTick Using Interrupts • Lab Practical #1 in progress. • Lab 5 is due and Lab 6 starts NEXT week. – You may work on labs in pairs starting with Lab 6

• Homework #4 due next TUESDAY, 4 p.m. Lecture #14

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SysTick Timer • Timer/Counter operation – 24-bit counter decrements at system clock frequency (or precision clock frequency  4) • 16 MHz system clock  62.5 ns decrements • 16 MHz precision clock  ______ ns decrements

– Counting is from n  0 • Setting n appropriately will make the counter a modulo n+1 counter. That is: – next_value = (current_value-1) mod (n+1) – Sequence: n,n-1,n-2,n-3…2,1,0,n,n-1…

– E.g. Find n for a 1 ms. count to 0 at 16 MHz? For system clock: 1ms/62.5ns = 16,000 = n+1 or n = 15,999. Will this fit in 24 bits? How big can n be? Lecture #14

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SysTick Timer SysTick Registers Address $E000E010 $E000E014 $E000E018

31-24

23-17

0 0 0

0

16 COUNT

15-3 2 1 0 0 CLK_SRC INTEN ENABLE 24-bit RELOAD value 24-bit CURRENT value of SysTick counter

Name NVIC_ST_CTRL_R NVIC_ST_RELOAD_R NVIC_ST_CURRENT_R

• Initialization (4 steps) – Step1: Clear ENABLE bit to stop counter – Step2: Specify the RELOAD value (n) – Step3: Clear the counter by writing to register NVIC_ST_CURRENT_R – Step4: Set CLK_SRC=1 (system) or 0 (precision) and specify whether interrupt action via INTEN in NVIC_ST_CTRL_R

• For details, see the Tiva TM4C123GH6PM Microcontroller Data Sheet, Sect. 3.1.1, p. 123 and Section 3.3, pp. 137-141 Lecture #14

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SysTick Timer Setup Subroutine SysTick_Init ; disable SysTick during setup LDR R1, =NVIC_ST_CTRL_R MOV R0, #0 ; Clear Enable STR R0, [R1] ; set reload to maximum reload value LDR R1, =NVIC_ST_RELOAD_R LDR R0, =0x00FFFFFF; ; Specify RELOAD value STR R0, [R1] ; reload at maximum ; writing any value to CURRENT clears it LDR R1, =NVIC_ST_CURRENT_R STR R0, [R1] ; clear counter ; enable SysTick with core clock LDR R1, =NVIC_ST_CTRL_R MOV R0, #0x0005 ; Enable but no interrupts (later) STR R0, [R1] ; ENABLE with System Clock BX LR ; Return from subroutine

Lecture #14

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Time Delay Subroutine (Polling) ;------------SysTick_Wait-----------; Time delay using busy wait. ; Input: R0 delay parameter in units of the core clock ; At 16 MHz, tick is 62.5 nsec; at 80 MHz, 12.5 nsec ; Output: none ; Modifies: R1 SysTick_Wait SUB R0, R0, #1 ; delay-1 LDR R1, =NVIC_ST_RELOAD_R STR R0, [R1] ; time to wait LDR R1, =NVIC_ST_CURRENT_R STR R0, [R1] ; any value written to CURRENT clears LDR R1, =NVIC_ST_CTRL_R SysTick_Wait_loop LDR R0, [R1] ; read status ANDS R0, R0, #0x00010000 ; bit 16 is COUNT flag BEQ SysTick_Wait_loop ; repeat until flag set BX LR ; flag set, so return from sub Lecture #14

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Delay Using SysTick_Wait ;------------SysTick_Wait10ms-----------; Call this routine to wait for R0*10 ms ; Time delay using busy wait. This assumes 16 MHz clock ; Input: R0 number of times to wait 10 ms before returning ; Output: none ; Modifies: R0 DELAY10MS EQU 160000 ; clock cycles for 10 ms delay SysTick_Wait10ms PUSH {R4, LR} ; save R4 and LR MOVS R4, R0 ; R4 = R0 = remainingWaits BEQ SysTick_Wait10ms_done ; R4 == 0, done ; SysTick_Wait10ms_loop LDR R0, =DELAY10MS ; R0 = DELAY10MS BL SysTick_Wait ; wait 10 ms SUBS R4, R4, #1 ; remainingWaits-BHI SysTick_Wait10ms_loop ; if(R4>0), wait another 10 ms ; SysTick_Wait10ms_done POP {R4, PC} ; pop R4 and Return

• What would DELAY10MS be if an 80 MHz Clock were used? Lecture #14

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SysTick Timer • Using Phase Lock Loop frequency multiplier, clock may run 16 to 80 MHz – Will show how to set this up in following slides – Greater accuracy and resolution in time

• Method just shown uses polling. – When would using polling be appropriate?

• Will show how to initiate and use interrupts – Frees up processor for other tasks – Basis for Real-Time systems

• SysTick will be used in Lab 6 next week. – Interrupts and Precision Clock, but no PLL Lecture #14

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Lab 6 Fig. 6.9- Data Structures NVIC_ST_CTRL EQU 0xE000E010 NVIC_ST_RELOAD EQU 0xE000E014 NVIC_ST_CURRENT EQU 0xE000E018 SHP_SYSPRI3 EQU 0xE000ED20 RELOAD_VALUE EQU 0x00300000 Stack EQU 0x00000400 EXTERN OutStr ;********************************************************* ; Stack area ;********************************************************* AREA STACK, NOINIT, READWRITE, ALIGN=3 StackMem SPACE Stack ;********************************************************* ; Reset area ;********************************************************* AREA RESET, CODE, READONLY THUMB EXPORT __Vectors __Vectors DCD StackMem + Stack DCD Reset_Handler ... DCD SysTick_Handler

; Top of Stack ; Reset Handler ; SysTick Handler

Lecture #14

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Lab 6 Fig. 6.9 - Setup/Main ;********************************************************* ; Program area ;********************************************************* AREA |.text|, CODE, READONLY, ALIGN=2 THUMB EXPORT Reset_Handler Reset_Handler LDR R1, =NVIC_ST_CTRL MOV R0, #0 STR R0, [R1] LDR R1, =NVIC_ST_RELOAD LDR R0, =RELOAD_VALUE STR R0, [R1] LDR R1, =NVIC_ST_CURRENT MOV R0, #0 STR R0, [R1] LDR R1, =SHP_SYSPRI3 MOV R0, #0x40000000 STR R0, [R1] LDR R1, =NVIC_ST_CTRL MOV R0, #0x03 STR R0, [R1] ;********************************************************* ; End of Systick Setup. Main follows ;********************************************************* CPSIE I wait WFI B wait

Lecture #14

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Lab 6 Fig. 6.9 – SysTick ISR ;********************************************************* ; SysTick ISR ;********************************************************* EXPORT SysTick_Handler SysTick_Handler PUSH {LR} LDR R5,=hello BL OutStr POP {LR} BX LR ;********************************************************* ; Data area ;********************************************************* hello DCB "Hello from SysTick",13,4 ALIGN END

Lecture #14

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Enable SysTick Interrupts SysTickInts.s enables interrupts in SysTick from TI/Texas U ; **************SysTick_Init********************* ; Initialize SysTick periodic interrupts, priority 2 ; Input: R0 interrupt period Units of period are 1/clockfreq ; Maximum is 2^24-1 Minimum is determined by length of ISR ; Output: none Modifies: R0, R1, R2, R3 SysTick_Init ; start critical section MRS R3, PRIMASK ; save old status CPSID I ; mask all interrupts(except faults) ; disable SysTick during setup LDR R1, =NVIC_ST_CTRL_R ; R1 is pointer to NVIC_ST_CTRL_R MOV R2, #0 STR R2, [R1] ; disable SysTick ; maximum reload value LDR R1, =NVIC_ST_RELOAD_R ; R1 is pointer to NVIC_ST_RELOAD_R SUB R0, R0, #1 ; counts down from RELOAD to 0 STR R0, [R1] ; establish interrupt period ; any write to CURRENT_R clears it LDR R1, =NVIC_ST_CURRENT_R ; R1 is pointer to NVIC_ST_CURRENT_R STR R2, [R1] ; writing to counter clears it

Lecture #14

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Enable SysTick Interrupts SysTickInts.s continued ; set NVIC system interrupt 15 to priority 2 LDR R1, =NVIC_SYS_PRI3_R ; R1 = &NVIC_SYS_PRI3_R (pointer) LDR R2, [R1] ; friendly access AND R2, R2, #0x00FFFFFF ; R2 = R2&0x00FFFFFF (clear interrupt 15 ; priority) ORR R2, R2, #0x40000000 ; R2 = R2|0x40000000 (interrupt 15 priority ; is in bits 31-29) STR R2, [R1] ; set SysTick to priority 2 ; enable SysTick with core clock LDR R1, =NVIC_ST_CTRL_R ; R1 = &NVIC_ST_CTRL_R ; ENABLE SysTick (bit 0), INTEN enable interrupts (bit 1), and ; CLK_SRC (bit 2) is internal MOV R2, #(NVIC_ST_CTRL_ENABLE+NVIC_ST_CTRL_INTEN+NVIC_ST_CTRL_CLK_SRC) STR R2, [R1] ; store a 7 to NVIC_ST_CTRL_R ; end critical section MSR PRIMASK, R3 ; restore old status BX LR ; return

Lecture #14

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SysTick Interrupt Handler PeriodicSysTickInts.s SysTick Interrupt Handler from TI/Texas U EXPORT SysTick_Handler SysTick_Handler ; increment Counts LDR R2, =Counts LDR R3, [R2] ADD R3, R3, #1 STR R3, [R2] ; Change LED LDR R2, =GPIO_PORTF_DATA_R AND R3, #0x0000000E

BX

STR R3, [R2] LR

; SysTick Interrupt Service Routine

; R2 = &Counts (pointer) ; R3 = R3 + 1 (Counts = Counts + 1) ; (overflows after 49 days) ; R2 = &GPIO_PORTF_DATA_R (pointer) ; Keep LED bits only ; Store back into Port F Data Register ; return from interrupt

Lecture #14

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SysTick Main Program PeriodicSysTickInts.s Skeleton of main program from TI/ Texas U Start BL PLL_Init ; activate clock for Port F ; set direction register ; regular port function ; enable digital port ; configure as GPIO ; disable analog functionality ; initialize Counts LDR R1, =Counts MOV R0, #0 STR R0, [R1] ; enable SysTick MOV R0, #0x00FFFFFF BL SysTick_Init CPSIE I handlers (clear PRIMASK) loop WFI B loop

; 50 MHz clock

; R1 = &Counts (pointer) ; R0 = 0 ; [R1] = R0 (Counts = 0) ; initialize SysTick timer for slow interrupts ; enable SysTick ; enable interrupts and configurable fault

; wait for interrupt ; unconditional branch to 'loop'

Lecture #14

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PLL: Phase-Locked Loop OSCSRC

External crystal Main Osc 16 MHz Internal Osc

BYPASS

00

USESYSDIV

Mux 01

/4

30 kHz Internal Osc Ref Clk

1

DIV400

* can't drive the PLL

10* 11*

1

Phase-Lock-Loop Up

Phase/ Charge Freq Down Pump/ Detector LPF

/m

Mux

VCO 400 MHz

/2

0

Mux

0

0

Mux

/n

1

SYSDIV

200 MHz

XTAL

• • • •

Internal oscillator requires minimal power but is imprecise External crystal provides stable bus clock TM4C is equipped with 16 MHz crystal and bus clock can be set to a maximum of 80 MHz See Wikipedia’s entry on “Phase-Locked Loop” for explanation Lecture #14

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Phase-Locked Loop • Software to enable the phase-lock loop is not worth the effort to explain in this course. • Example source code to enable changing the system clock frequency is available in “Code Files” on our lab web page. We have tested this code. – PLL.s subroutine to enable PLL – PLL_main.s program to demonstrate its use Lecture #14

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SysTick Summary • SysTick can be used as a time delay • It is most powerful as method for creating interrupts on a fixed interval • Programming SysTick is straightforward – Creating a real-time system based on it is a bit more complex, but is required in many real system environments

• See both Lecture and Lab Examples • Next topic: Timer Module, a Major Topic and basis for Lab #7. Lecture #14

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