ECE7660 Advanced Computer Architecture MIPS Instruction Set Architecture
Why is MIPS a good example? Learn ISA further by this example. How does IS fill up the gap between HLL and machine?
2005-9-12
ECE7660 MIPS.1
Instruction Set Design
software
instruction set
hardware
An instruction is a binary code, which specifies a basic operation (e.g. add, subtract, and, or) for the computer • Operation Code: defines the operation type • Operands: operation source and destination
ECE4680 Lec 3 ISA.2
September 12, 2005
Execution Cycle Instruction
Obtain instruction from program storage
Fetch Instruction
Determine required actions and instruction size
Decode Operand
Locate and obtain operand data
Fetch Execute Result
Compute result value or status Deposit results in storage for later use
Store Next
Determine successor instruction
Instruction ECE4680 Lec 3 ISA.3
September 12, 2005
What Must be Specified? Instruction Fetch Instruction Decode Operand Fetch Execute Result Store Next
° Instruction Format or Encoding – how is it decoded? ° Data type and Size – what are supported ° Location of operands and result – addressing mode – where other than memory? – how many explicit operands? – how are memory operands located? – which can or cannot be in memory?
° Operations – what are supported ° Successor instruction – flow control – jumps, conditions, branches
Instruction - fetch-decode-execute is implicit! ECE4680 Lec 3 ISA.4
September 12, 2005
ISA Design Principle • ISA should reflect application characteristics: –Desktop computing » compute-intensive, thus focusing on features favoring Integer and FP ops;
–Server computing » data-intensive, focusing on integers and charstrings (yet FP ops are still standard in them)
–Embedded computing » time-sensitive, memory and power concious, thus focusing on code-density, real-time and media data streams. Slide 5
MIPS R2000 / R3000 Registers °32-bit machine --> Programmable storage:
232 x bytes
°31 x 32-bit GPRs (R0 = 0) °5 bit fields in instructions for register addressing °32 x 32-bit FP regs (f0 - f31, paired DP) °HI, LO, PC: SPRegisters °Big Endian °2 nomenclatures(next slide)
r0 r1 ° ° ° r31 PC lo hi
0
°See Fig. A.18 at P. A-50 for more details
°Addressing modes: • immediate • register • displacement °All instructions are 32-bit wide and must be aligned. ECE7660 MIPS.6
2005-9-12
2 Nomenclatures of MIPS Registers Name
number
Usage
Reserved on call?
zero
0
constant value =0
n.a.
at
1
reserved for assembler (p.147,157)
n.a.
v0 – v1
2–3
values for results and expression evaluation no
a0 – a3
4–7
arguments
no
t0 – t7
8 – 15
temporaries
no
s0 – s7
16 – 23
saved
yes
t8 – t9
24 – 25
more temporaries
no
k0 – k1
26 – 27
reserved for kernel (p.225)
n.a.
gp
28
global pointer
yes
sp
29
stack pointer
yes
fp
30
frame pointer
yes
ra
31
return address
yes
Registers are referenced either by number— number—$0… $0…$31, or by name —$t0,$s1… $t0,$s1…$ra. ra.
zero at v0-v1 a0 - a3 t0 - t7 s0 - s7 t8 - t9 k0 - k1 gp sp fp ra 0
1
2 - 3
4-7
8
--- 15 16 --- 23 24 - 25
26 - 27
28
29 30
31
2005-9-12
ECE7660 MIPS.7
MIPS arithmetic and logic instructions Instruction add subtract add immediate
Example add $1,$2,$3 sub $1,$2,$3 addi $1,$2,100
Meaning $1 = $2 + $3 $1 = $2 – $3 $1 = $2 + 100
multiply divide
mult $2,$3 div $2,$3
Move from Hi Move from Lo
mfhi $1 mflo $1
Hi, Lo = $2 x $3 64-bit signed product Lo = $2 ÷ $3, Lo = quotient, Hi = remainder Hi = $2 mod $3 $1=Hi get a copy of Hi $1=lo
Instruction and or xor nor ECE7660 MIPS.8
Example and $1,$2,$3 or $1,$2,$3 xor $1,$2,$3 nor $1,$2,$3
Meaning $1 = $2 & $3 $1 = $2 | $3 $1 = $2 ⊕ $3 $1 = ~($2 |$3)
Comments 3 operands; exception possible 3 operands; exception possible + constant; exception possible
Comment Logical AND Logical OR Logical XOR Logical NOR 2005-9-12
Example 1 E.g. f= (g+h) - (i+j), assuming f, g, h, i, j be assigned to $1, $2, $3, $4, $5 add $7, $2, $3 add $8, $4, $5 sub $1, $7, $8
2005-9-12
ECE7660 MIPS.9
MIPS data transfer instructions
ECE7660 MIPS.10
Instruction
Comment
SW 500($4), $3
Store word
SH 502($2), $3
Store half
SB 41($3), $2
Store byte
LW $1, 30($2)
Load word
LH $1, 40($3)
Load half a word
LB $1, 40($3)
Load byte
2005-9-12
Example 2 Assume A is an array of 100 words, and compiler has associated the varialbes g and h with the register $1 and $2. Assume the base address of the array is in $3. Translate g = h + A[8] lw $4, 8($3); add $1, $2, $4;
$4 =j) go to L1;
Assuming f, g, h, i, j ~ $1, $2, $3, $4, $5
L1:
beq $4, $5, L1 add $1, $2, $3 sub $1, $1, $4
pseudoinstruction
bge $4, $5, L1 assembler
slt $1, $4, $5 beq $0, $1, L1 Labels end in colons; they’re symbolic names for addresses ECE7660 MIPS.14
2005-9-12
Example 5 Loop: g = g +A[i]; i = i+ j; if (i != h) go to Loop: Assuming variables g, h, i, j ~ $1, $2, $3, $4 and base address of array is in $5 Loop: add $7, $3, $3; add $7, $7, $7; add $7, $7, $5 lw $6, 0($7); add $1, $1, $6; add $3, $3, $4 bne $3, $2, Loop;
i*2 i*4 $6=A[i] g= g+A[i]
2005-9-12
ECE7660 MIPS.15
Example 6 while (A[i]==k) i = i+j; Assume i, j, and k ~ $17, $18, $19 and base of A is in $3 Loop: add $20, $17, $17 add $20, $20, $20 add $20, $20, $3 lw $21,0($20) bne $21, $19, Exit add $17, $17, $18 j Loop Exit:
ECE7660 MIPS.16
2005-9-12
MIPS Addressing Modes/Instruction Formats R-format: Register (direct)
I-format: Immediate Base+index
6 op
5
5
5
5
rs
rt
rd
smt
6 func
Rd Års func rd
register op
rs
rt
immed
op
rs
rt
immed
register PC-relative
op
rs
Rt Års op immed Memory +
rt
immed
PC + 4
Memory +
J-format: op
Memory
addr.
2005-9-12
ECE7660 MIPS.17
Example: See machine code in memory while (A[i]==k) i = i+j; Assume i, j, and k ~ $17, $18, $19 and base of A is in $3
Loop: add $20, $17, $17 add $20, $20, $20 add $20, $20, $3 lw $21,0($20) bne $21, $19, Exit add $17, $17, $18 j Loop Exit:
Assume the loop is placed starting at loc 8000 8000: 0 17 17 20 0 32 0
20
20
20
0
32
0
20
3
20
0
32
35 20
21
5 0 2
21 17
0
19 18 8000
8 17
2 0 32 2000
Offset in branch is relative. Address in jump is absolute. Address in Branch or Jump instruction is word address so that they can go 4 times far as opposed to byte address. (p150) ECE7660 MIPS.18
2005-9-12
MIPS Circuits for Instructions
ECE7660 MIPS.19
2005-9-12
MIPS Circuits for Instructions (continue) Phase1: Preparation
Load instruction register Forward to the control logic: • op field • funct field • shmt field Forward to the register file: • First operand register number • Second operand register number • Target register number for the result
Phase: Execution Register numbers are forwarded to the selectors
Corresponding selector outputs are activated Outputs of the two chosen registers are switched to the data buses via AND gates Control logic provides • Correct code for the ALU to perform an operation • Write signal Result is written back into the register file ECE7660 MIPS.20
2005-9-12
Summary of MIPS Architecture ° Use general-purpose registers with a load-store architecture ° Support addressing modes: displacement, immediate, and register indirect ° Support data sizes and types: 8-, 16-, 32-, and 64-bit integers and 64-bit IEEE 754 floating-point numbers ° Support simple instructions like load, store, add, subtract, move register-register, and shift because they dominate the number of instructions executed ° Use fixed instruction encoding (32 bits) if interested in performance, and use variable instruction encoding if interested in code size ° MIPS32 provides 32 general-purpose 32-bit registers; MIPS64 has 32 64-bit registers. ° For more info, see Ch2.12 and Appendix C 2005-9-12
ECE7660 MIPS.21
Procedure Call and Stack Stacking of Subroutine Calls & Returns and Environments: A
A: CALL B B:
A B CALL C A B C
C: RET
A B RET A Some machines provide a memory stack(special hardware) as part of the architecture (e.g. the VAX). Use special instructions, e.g. pop, push. Sometimes stacks are implemented via software convention (e.g. MIPS). Use same data transfer instructions, e.g., lw, sw.
ECE7660 MIPS.22
2005-9-12
Example in C: swap (pp163-165) °Assume swap is called as a procedure °Assume temp is register $15; arguments v and k ~ $16 and $17; °Write MIPS code swap(int v[], int k) { int temp; temp = v[k]; v[k] = v[k+1]; v[k+1] = temp; }
sll addu lw lw sw sw
$18, $17, 2 $18, $18, $16 $15, 0($18) $19, 4($18) $19, 0($18) $15, 4($18)
; mulitply k by 4 ; address of v[k] ; load v[k] ; load v[k+1] ; store v[k+1] into v[k] ; store old v[k] into v[k+1]
Registers $15, $16, $17, $18, $19 are occupied by caller ??
2005-9-12
ECE7660 MIPS.23
Example: Swap Given a procedure swap(v, j) Calling swap is as simple as jal swap jal --- jump and link $31 = PC+4; goto swap
ECE7660 MIPS.24
$31=$ra : always store return address
2005-9-12
swap: MIPS swap: addi
$sp,$sp, –24
sw
$31, 20($sp)
; Save return address
sw
$15, 16($sp)
; Save registers on stack
sw
$16, 12($sp)
sw
$17, 8($sp)
sw
$18, 4($sp)
sw
$19, 0(sp)
; Make room on stack for 6 registers
.... lw
$19, 0($sp)
lw
$18, 4($sp)
lw
$17, 8($sp)
lw
$16, 12($sp)
lw
$15, 16($sp)
; Restored registers from stack
lw
$31, 20($sp)
; Restore return address
addi
$sp,$sp, 24
; restore top of stack
jr
$31
; return to place that called swap
ECE7660 MIPS.25
2005-9-12
