Chapter 5, The Instruction Set Architecture Level 5.1 Overview Of The ISA Level 5.2 Data Types 5.3 Instruction Formats 5.4 Addressing 5.5 Instruction Types 5.6 Flow Of Control 5.7 A Detailed Example: The Towers Of Hanoi 5.8 The Intel IA-64 5.9 Summary

Instruction Formats Opcode:

The operation to be performed

Source Operands:

The operand source address locations

Result Destination:

The result address location

Next Instruction:

Where does the next instruction come from

Explicit:

Instruction provides specific information

Implicit:

Based on the ISA or instruction, the appropriate information can be inferred (the next instruction is usually PC+1, stack based machine has no source/destination address for ALU operations, etc.)

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ECE 3570

Notes and figures are based on or taken from materials in the course textbook: A.S. Tanenbaum, Structured Computer Organization 5th ed., Prentice Hall, Upper Sable River, NJ, 2006. ISBN 0-13-148521-0.

Instruction Addressing and Machines: 4-, 3-, 2-,1-, and 0-Address Machines 4-Address:

Conventional ALU two addresses for the source one address for the destination one address for the next instruction

3-Address:

Conventional ALU two addresses for the source one address for the destination implied next instruction (or an alternate instruction format)

2-Address:

Conventional ALU two addresses for the source results overwrite one of the sources

1-Address:

Accumulator Based machines one address is used for one source the accumulator provides the other and the destination

0-Address:

Stack Based machines use the stack as both source and destination

Note: Once the number of address machine architecture is set, the machine may also include and use instructions of all lower number of addresses.

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ECE 3570

Notes and figures are based on or taken from materials in the course textbook: A.S. Tanenbaum, Structured Computer Organization 5th ed., Prentice Hall, Upper Sable River, NJ, 2006. ISBN 0-13-148521-0.

Instruction Size and Storage Simple RISC processors:

All instructions the same size The typical instruction is only one word

CISC processors:

Variable word size instructions Typically 1, 2, 3, or 4 words

Unique Languages:

Multiple Instructions per word ARM core 32-bit machine has some 16-bit instructions

VLIW:

Very Long Instruction Word Word contains one field for each processing element (TMS320C6701 has 8 units with 16-bits per unit or 128 bits)

Design Criteria for Instruction Formats (How to outlast the current processor.) 1.

Size of the Instructions balance instruction size vs. required capabilities, addressing, and inst. fetch times typically word length or multiple word lengths

1a.

Consider the instruction fetch and instruction building required multiple word fetches require more time … leading to fewer instructions per second (average mem. access time and I-cache make a difference)

2.

Include enough bits to define “ALL” operations allow for future growth provide some “unassigned” opcodes

3.

Determine any address range or size limitations a 32-bit address by byte accesses only 4GB of space the number of RISC registers defines the address field size (32 reg  5 bits each)

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ECE 3570

Notes and figures are based on or taken from materials in the course textbook: A.S. Tanenbaum, Structured Computer Organization 5th ed., Prentice Hall, Upper Sable River, NJ, 2006. ISBN 0-13-148521-0.

Example design: RISC based machine instruction set (Expanding Opcodes) Assume: 16-bit instruction 16 registers a mix of 3-, 2-, 1-, and 0-address instructions 3-address Instructions

Opcode

Source2

Source1

Dest

12-bits for addressing 4-bits for instructions  16 maximum instructions, but … that would be all Reserve 1 opcode that can be used for 2-address instructions (15 3-add inst plus 1) 2-address Instructions

1111

Opcode

Source1

Dest

8-bits for addressing fixed 1111 field to identify 2-address instructions 4-bits for instructions  16 maximum instructions, but … that would be all Reserve 1 opcode that can be used for 1-address instructions (15 2-add inst plus 1) 1-address Instructions

1111

1111

Opcode

Source/Dest

4-bits for addressing fixed 1111 1111 fields to identify 1-address instructions 4-bits for instructions  16 maximum instructions, but … that would be all Reserve 1 opcode that can be used for 0-address instructions (15 1-add inst plus 1) 0-address Instructions

1111

1111

1111

Opcode

0-bits for addressing fixed 1111 1111 1111 fields to identify 0-address instructions 4-bits for instructions  16 maximum instructions. 4 of 30

ECE 3570

Notes and figures are based on or taken from materials in the course textbook: A.S. Tanenbaum, Structured Computer Organization 5th ed., Prentice Hall, Upper Sable River, NJ, 2006. ISBN 0-13-148521-0.

Result: 

There are four instruction formats



One format for 3-, 2-, 1-, and 0- address instructions each



Formats 1, 2, and 3 have 15 instructions available



Format 0 has 16 instructions available

Total instructions 

15 3-address instructions



15 2-address instructions



15 1-address instructions



16 0-address instructions



Total of 61 instructions available

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ECE 3570

Notes and figures are based on or taken from materials in the course textbook: A.S. Tanenbaum, Structured Computer Organization 5th ed., Prentice Hall, Upper Sable River, NJ, 2006. ISBN 0-13-148521-0.

An Alternate Expanding Opcode Format 3: 3-address (12-bits) xxxx yyyy zzzz 15 instructions plus 1

Format 2: 2-address (8-bits) yyyy zzzz 14 instructions plus 2

Format 1: Use both of the fields from Format 2 2 x 16 opcodes available use 31 and reserve 1 1-address (4-bits) zzzz 31 instructions plus 1

Format 0 0-address (0-bits) 16 instructions

Total: 15 3-address inst. 14 2-address inst. 31 1-address inst. 16 0-address inst. Total of 76 instructions Other schemes are possible! (e.g. 14 3-add, 30 2-add, 31 1-add, 16 0-add)

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ECE 3570

Notes and figures are based on or taken from materials in the course textbook: A.S. Tanenbaum, Structured Computer Organization 5th ed., Prentice Hall, Upper Sable River, NJ, 2006. ISBN 0-13-148521-0.

Pentium II Instruction Formats INTEL http://support.intel.com/support/processors/index.htm

Prefix:

Describe the instruction in some way Includes branch prediction for example.

OPCODE:

Basic Instruction

MOD R/M or MODE Field The mod field combines with the r/m field to form 32 possible values: eight registers and 24 addressing modes. Note: one operand must always be a register. The reg/opcode field specifies either a register number or three more bits of opcode information. The purpose of the reg/opcode field is specified in the primary opcode. The r/m field can specify a register as an operand or it can be combined with the mod field to encode an addressing mode. Sometimes, certain combinations of the mod field and the r/m field are used to express opcode information for some instructions.

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ECE 3570

Notes and figures are based on or taken from materials in the course textbook: A.S. Tanenbaum, Structured Computer Organization 5th ed., Prentice Hall, Upper Sable River, NJ, 2006. ISBN 0-13-148521-0.

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ECE 3570

Notes and figures are based on or taken from materials in the course textbook: A.S. Tanenbaum, Structured Computer Organization 5th ed., Prentice Hall, Upper Sable River, NJ, 2006. ISBN 0-13-148521-0.

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ECE 3570

Notes and figures are based on or taken from materials in the course textbook: A.S. Tanenbaum, Structured Computer Organization 5th ed., Prentice Hall, Upper Sable River, NJ, 2006. ISBN 0-13-148521-0.

Certain encodings of the ModR/M byte require a second addressing byte, the SIB byte (Scale, Base, Index). The base-plus-index and scale-plus-index forms of 32-bit addressing require the SIB byte. The SIB byte includes the following fields:

• The scale field specifies the scale factor. • The index field specifies the register number of the index register. • The base field specifies the register number of the base register.

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ECE 3570

Notes and figures are based on or taken from materials in the course textbook: A.S. Tanenbaum, Structured Computer Organization 5th ed., Prentice Hall, Upper Sable River, NJ, 2006. ISBN 0-13-148521-0.

Recap – thank goodness for compilers!

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Notes and figures are based on or taken from materials in the course textbook: A.S. Tanenbaum, Structured Computer Organization 5th ed., Prentice Hall, Upper Sable River, NJ, 2006. ISBN 0-13-148521-0.

The UltraSPARC II (a 3-address machine) 32-bit RISC based instruction 32-registers Four basic formats using 2-bit format identification fields

Format 1: 

One bit to describe 3-address or immediate values

Format 2: 

ALU operations

Special instruction to help load 32-bit values

One bit to describe 3-address or immediate values

Format 3:

Branches



22-bit displacement/ Branch prediction&displacement



condition codes

Format 4: 

Calls

One bit to describe 3-address or immediate values

Current Definition actually has 31 formats that are derivatives of the original 4

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ECE 3570

Notes and figures are based on or taken from materials in the course textbook: A.S. Tanenbaum, Structured Computer Organization 5th ed., Prentice Hall, Upper Sable River, NJ, 2006. ISBN 0-13-148521-0.

The 8051 6 instruction formats Accumulator based machine (no 3 or 4 address instructions) 4 banks of 8 registers (2-bit bank select 3-bit register select)

(1) Just an opcode: simple operations or accumulator only (2) 5-bit opcode, 3-bit register instructions (3) 1-byte operand (immediate values or 8-bit offsets) (4) & (5) jumps and subroutine calls: memory addressing – all internal, 11-bits, or external, 16bits. (6) two 8-bit operands

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ECE 3570

Notes and figures are based on or taken from materials in the course textbook: A.S. Tanenbaum, Structured Computer Organization 5th ed., Prentice Hall, Upper Sable River, NJ, 2006. ISBN 0-13-148521-0.

JVM Instruction Format (a 0-address machine with some 1-address instructions)

9 Formats as defined IJVM uses Formats 1, 2, 3, and 4 (IINC) 6 Formats (4-9) are specific for 8 instructions! Note: The WIDE prefix may be required … format selection (2 or 3, 4 or 7) due to a modifier. Special Opcodes are allocated to instructions with high probability (frequency of use):  ILOAD_0, ILOAD_1, ILOAD_2, ILOAD_3  BIPUSH_-1, BIPUSH_0, and BIPUSH_(1-5)

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ECE 3570

Notes and figures are based on or taken from materials in the course textbook: A.S. Tanenbaum, Structured Computer Organization 5th ed., Prentice Hall, Upper Sable River, NJ, 2006. ISBN 0-13-148521-0.

Addressing The most significant part of the instruction! AST Addressing Modes 5.4.2 Immediate Addressing Value  #XXXX 5.4.3 Direct Addressing Value  M[ #XXXX ] 5.4.4 Register Addressing Value  R( a ) 5.4.5 Register Indirect Addressing Value  M[ R( a ) ] 5.4.6 Indexed Addressing Value  M[ R( a ) + #XXXX] 5.4.7 Based-Indexed Addressing Value  M[ R( a ) + R( b ) ] 5.4.8 Stack Addressing Value  from or to the stack 5.4.9 PC Relative Addressing NewPC  PC + #XXXX

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ECE 3570

Notes and figures are based on or taken from materials in the course textbook: A.S. Tanenbaum, Structured Computer Organization 5th ed., Prentice Hall, Upper Sable River, NJ, 2006. ISBN 0-13-148521-0.

Example Heuring and Jordan Immediate

5.4.2 Immediate Addressing Value  #XXXX

Direct, absolute indirect

5.4.3 Direct Addressing Value  M[ #XXXX ]

Register

5.4.4 Register Addressing Value  R( a )

Register indirect

5.4.5 Register Indirect Addressing Value  M[ R( a ) ]

Indexed, based, or displacement

5.4.6 Indexed Addressing Value  M[ R( a ) + #XXXX]

Not in H&J List

5.4.7 Based-Indexed Addressing Value  M[ R( a ) + R( b ) ]

(PC) Relative (similar)

5.4.9 PC Relative Addressing NewPC  PC + #XXXX

Notes note: Copy H&J 2-60 and 2-23

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ECE 3570

Notes and figures are based on or taken from materials in the course textbook: A.S. Tanenbaum, Structured Computer Organization 5th ed., Prentice Hall, Upper Sable River, NJ, 2006. ISBN 0-13-148521-0.

Motorola 68000 used about as many modes as possible!

5.4.4 5.4.5

5.4.6

“5.4.7”

5.4.3 5.4.2

Motorola M68000 Programmer’s Reference Manual http://www.freescale.com/webapp/sps/site/prod_summary.jsp?code=MC68000 http://www.freescale.com/files/archives/doc/ref_manual/M68000PRM.pdf

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ECE 3570

Notes and figures are based on or taken from materials in the course textbook: A.S. Tanenbaum, Structured Computer Organization 5th ed., Prentice Hall, Upper Sable River, NJ, 2006. ISBN 0-13-148521-0.

Addressing Mode Identification Practice

Register, Immediate Register, Immediate Register, Immediate Loop: Register, Indexed (Base and displacement) Register, Indexed (Base and displacement) Register, Register Register, Immediate Register, Register PC Relative

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ECE 3570

Notes and figures are based on or taken from materials in the course textbook: A.S. Tanenbaum, Structured Computer Organization 5th ed., Prentice Hall, Upper Sable River, NJ, 2006. ISBN 0-13-148521-0.

Stack Addressing When operators are placed within an equation, between the operands, it is called infix notation. When operators are placed after the operands, it is called postfix notation (or reverse Polish notation). Stacks operate as in postfix notation …. See the cute example in your text on how to convert from infix to postfix notation. Note: operations with specific order (subtraction and division) must be have operands pushed in the correct order!

Implementing Stack Based Computations (The HP way [stack based,postfix], before TI [infix] won the calculator wars) http://en.wikipedia.org/wiki/Calculator_input_methods

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ECE 3570

Notes and figures are based on or taken from materials in the course textbook: A.S. Tanenbaum, Structured Computer Organization 5th ed., Prentice Hall, Upper Sable River, NJ, 2006. ISBN 0-13-148521-0.

Orthogonality of Opcodes and Addressing Modes As a goal, all opcodes should allow all addressing modes. This would provide the most flexibility for software code generation and simple compiler design. In reality, they do not! 

Motorola has general purpose registers and index registers. They are not always interchangeable!



Intel P6 has defined segment and indexed registers. They should not be considered equivalent in use as general purpose registers.

Example 32-bit RISC (“reorganized UltraSPARC”)

3-address ISA Basis Format 1:

Arithmetic and Logic Operations Use 3 registers as per RISC philosophy

Format 2:

Load and Store or Conditional Branches Load/Store use a data source register and Indexed Addressing storage Conditional Branch uses either two registers and PC Relative Addressing or one register and “relative” addressing for next instruction

Format 3:

Immediate Load or Brach or Call Use immediate field as a value or as an absolute address PC Relative addressing could also be performed

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ECE 3570

Notes and figures are based on or taken from materials in the course textbook: A.S. Tanenbaum, Structured Computer Organization 5th ed., Prentice Hall, Upper Sable River, NJ, 2006. ISBN 0-13-148521-0.

Example 32-bit CISC (based on PDP-11/VAX but similar to a reorganized Pentium II)

2-Address ISA Basis A 12-bit Address Location Group MODE defines the type of addressing mode to be used (8 possible) REG defines which of 32 available registers to use in addressing OFFSET provides an offset or displacement for addressing Optional Words provide 32-bit immediate values for addressing, one for each operand as required.

Comparison of Addressing Modes

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ECE 3570

Notes and figures are based on or taken from materials in the course textbook: A.S. Tanenbaum, Structured Computer Organization 5th ed., Prentice Hall, Upper Sable River, NJ, 2006. ISBN 0-13-148521-0.

Instruction Types Instructions can be divided into multiple classes: Data Movement Instructions 

Load and Store operations



Push and Pop

Arithmetic and Logic Instructions (ALU) 

Combining operands according to math (+, -, *, / ) or logic (AND, OR, XOR, NOT)

Branch Instructions 

Conditional flow control

Floating Point Instructions (FPU) or Special Processing Instructions 

Special purpose registers and functional unit instructions



Floating Point math (+, -, *, / ), normalize and denormalize



Format conversion



Trigonometric functions

Multimedia Instructions (MMX, 3DNOW!, AltiVec, etc.) 

Using subword parallelism to operate on smaller-than-word data components



Math support for multimedia (graphics, pixels, etc.)

Single-Instruction Multiple-Data (SIMD, SSE) – scientific computations 

Special support for vector based data/signal processing



Useful for digital signal processing (DSP) and graphics

Subroutine Calls and Interrupt Service Routine Invoking 

Special instruction when normal processing flow is expected to return to the addressing following the current PC location.



Often requires storage or stack pushing of parameters for entering a routine



Often requires the handling of a return value or condition after routine completion

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ECE 3570

Notes and figures are based on or taken from materials in the course textbook: A.S. Tanenbaum, Structured Computer Organization 5th ed., Prentice Hall, Upper Sable River, NJ, 2006. ISBN 0-13-148521-0.

Instruction Types Detail Data Movement Instructions 

Use available addressing modes previously described to move data



It could be thought of as data copying or duplication

Arithmetic and Logic Instructions Dyadic Operations

combining two operands to make a result



always AND, OR, NOT … sometimes others (EXOR, NAND, NOR, etc.)



always + and - … sometimes x and /



sometimes Floating Point and MMX and SIMD

Critical instruction operations: 

masking and packing  masking involves removing bit fields  packing involves ORing in bit fields



setting and clearing control registers



efficient packing of ASCII characters



preparing data for modem or other forms of transmission

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ECE 3570

Notes and figures are based on or taken from materials in the course textbook: A.S. Tanenbaum, Structured Computer Organization 5th ed., Prentice Hall, Upper Sable River, NJ, 2006. ISBN 0-13-148521-0.

Arithmetic and Logic Instructions Monadic Operations one operand manipulations Critical instruction operations: 

Shifting  Typically performed on arithmetic values  Shift left requires zero filling and may change the sign of the value (overflow concerns)  Shift right is the equivalent of 2^n division and requires sign extension (negative number rounding concerns)  Also used when masking and packing Note: shifting and adding can be more efficient than multiplying!



Rotating  Typically performed on logical values  Circular operations that may or may not be in conjunction with the carry bit flag  Rotating through the carry bit allows conditional detection of single bit values Used for multiplication/division algorithms or bit level decision/detection packing



Special arithmetic operations  NEG – additive inverse  NOT – one’s complement  MODULO – support modulo arithmetic (Residue Number Systems)

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ECE 3570

Notes and figures are based on or taken from materials in the course textbook: A.S. Tanenbaum, Structured Computer Organization 5th ed., Prentice Hall, Upper Sable River, NJ, 2006. ISBN 0-13-148521-0.

Comparisons and Conditional Branches Comparison 

Comparison results may not have to be written as results, but they must set the condition code or program status registers



Condition Codes: Zero, Negative, Carry, oVerflow, etc.



A subtraction is typically required by the ALU



Results may be dependent upon the data type (e.g. signed vs. unsigned integers)

Procedure Call Instructions Invoking Methods and Return 

IJVM invoke saved the (1) local variable space and the register LV, (2) all values on the stack and can restore the registers SP and TOS (3)and the return value of the PC



Does the ISA provide “automatic” storage of registers and pointers?



If so, is everything saved or is it a limited set

Call and Return from Subroutines 

Again, partial storage or complete storage of registers, PSW/condition codes, and PC.



How is data passed from the main routine to the subroutine and back?

Concern: processing time required (overhead) 

Invoke and return required 30 clock cycles where “no functional processing” is done



If a high computation rate is desired, overhead clock cycles for calls are a waste!

Recursion or recursive calling capability 

Can a procedure be allowed to call itself?



Do intermediate results overwrite previous register values? Is it desirable?



Do successive calls/returns overwrite prior call computations or either the return address or return data?



Note: pushing and popping from a stack is one of the safer procedures! (IJVM)

The same issues will come up when we consider Exceptions and Interrupts

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ECE 3570

Notes and figures are based on or taken from materials in the course textbook: A.S. Tanenbaum, Structured Computer Organization 5th ed., Prentice Hall, Upper Sable River, NJ, 2006. ISBN 0-13-148521-0.

Loops Loop implementation may be done multiple ways: 

Test at the end of the loop (a)



Test at the beginning of the loop (b)

Test at the end of the loop The loop operations will be executed at least once … is it desirable? This structure allows static branch prediction Test at the beginning of the loop The loop instructions will not be executed if the conditional does not pass. This structure does not allow static branch prediction

Questions: What does the following high-level-language code compile to? for (i = 0; i