ECE2274 Pre-Lab for MOSFET logic LTspice NAND Gate, NOR Gate, and CMOS Inverter 1. NMOS NAND Gate Use Vdd = 9.0Vdc. For the NMOS NAND gate shown below gate, using the 2N7000 MOSFET LTspice model such that Vto = 2.0. The input logic “1” = 9 volt and ground as a logic “0”. Make a truth table showing the four possible combinations of Vin1 and Vin2 and the outputs. Choose Rd (drain current limit resistor) such that the drain currents of the NMOS devices will be about 30mA when the Vout is in a low state. Then run a DC Bias Point simulation (use the added 2N7000 model in LTspice) on your design with the four possible input combinations for Vin1 and Vin2 to verify your gate. Observe the output voltage value for each input combination. Print your circuit schematic showing voltages for all four input combination.
Vdd
Rd Vout
Q1
Vin1
D NMOS
G S Q2
Vin2
D NMOS
G S
Nmos NAND GATE
2. NMOS NOR Gate Use Vdd = 9.0Vdc. Design an NMOS NOR gate using the 2N7000 MOSFET the model has Vto = 2.0 . Limit the drain current total to 30mA with a drain resistor (Rd). Show all work for your design and drawing. Then simulate your design in LTspice with DC Bias Point simulations as you did for the NAND gate. Print out your circuit schematic showing voltages for all four input combination add from the view menu node voltage and drian current to display on the schematic. Also, fill in the truth table with all of the Bias Point simulation voltage values. Page 1 of 6 MOSFET Logic Revised: November 7, 2016
3. CMOS Inverter Use VDD = 9.0Vdc. Design a CMOS inverter using a NMOS and PMOS FET. The drain current will be limited by the two external 100Ω source resistors (RSnmos, RSpmos). The MOSFETs that we use in the lab both have a VGS threshold voltage of about │2.0V│and internal resistance is RS = 0.2Ω. Assume that there is a input voltage level 2.0V < Vin < VDD – 2.0V that will turn on both FETs at the same time. This will cause a large current flow that could damage the two devices. Because there is period of time when both devices on we will use a 1kHz triangle waveform as input so the time the devise send in a high current state will short in LTspice. (Triangle Wave) Use LTspice to plot the input triangle waveform (PULSE) 0 to 9v, output voltage waveform, and the current thru the devices. (DC sweep) Plot CMOS Transfer characteristic curve use DC sweep Vin from 0V to 9V. Plot Vout vs Vin mark on plot VOH , VOL , VIL and VIH.
VDD Vin (Triangle Wave) set PULSE
Vin (DC Sweep) Q1 PMOS Q2 NMOS
9Vdc 1kHz amplitude 0v to 9v Triangle wave PULSE 0V, 9V Tr=0.5ms Tf=0.5ms Tper=1ms, Td=0, Ton =1ns 0V to 9V 200mv step LTspice (TP0606) Lab (TP0606) LTspice (2N7000) Lab (2N7000)
LTspice TP0606 PMOS Internal resistance
Vto=-2 volts RS =0.2 ohms
LTspice 2N7000 NMOS Internal resistance
Vto = 2 volts RS = 0.2 ohms
Page 2 of 6 MOSFET Logic Revised: November 7, 2016
.dc Vin 0 9 .1
RSpmos 100
TP0606
Vdd
Vout
.include 2N7000.sub .include TP0606.sub
9V
Vin
M1 Rin 10k
M2
Vin
2N7002
Rload 10k
0 Rser=50
RSnmos 100
CMOS inverter for LTspice
Cmos Transfer characteristic curve.
Required Attachments: NAND Truth table Four schematics with voltages and currents of nodes and branches NOR Truth table Four schematics with voltages and currents of nodes and branches 5. Cmos Transfer characteristic curve (Triangle Wave), (DC sweep) 2 plots Page 3 of 6 MOSFET Logic Revised: November 7, 2016
Laboratory Exercise MOSFET logic NAND GATE, NOR GATE, and CMOS inverter 1. You must test your 2N7000 NMOS with the curve tracer before build your experiment. Set curve trace to N-FET, Is Max = 10ma, Vds max =10V, Vg/step = 0.1V, Offset = 1.8V, Rload = 10, N Steps = 10 2. You must test your TP0606 PMOS with the curve tracer before build your experiment. Set curve trace to P-FET, Is Max = 10ma, Vds max =10V, Vg/step = 0.1V, Offset = - 1.8V, Rload = 10, N Steps = 10
3. Build the NAND gate. Measure the output voltage levels with 10k load resistor connected to ground. You will use the voltmeter to verify the NAND gate’s operation. Try all of the input combinations. 4. Build the NOR gate that you designed in the Pre-Lab. Use VDD = 9.0Vdc Again, use an 10k load resistor connected to ground to determine the output states. Verify the truth table for a NOR gate. 5. Build CMOS Inverter with both the external 100Ω source resistors to limit the current. DC sweep the input from 0V to 9V in 200mv steps to plot the Cmos inverter no-load transfer characteristic curve, print the plot and mark the VOH, VOL, VIL and VIH
Page 4 of 6 MOSFET Logic Revised: November 7, 2016
DATA SHEET MOSFET logic DATA SHEET Name: ____________________________ Name: _________________________ Instructor: __________________________ Class day and time: __________________ Date: ______________________ Bench number: __________________ NAND GATE, NOR GATE, and COMS Inverter
1. NAND GATE static test. Vdd = 9Vdc Vin1
Vin2
0Vdc 0Vdc 9Vdc 9Vdc
0Vdc 9Vdc 0Vdc 9Vdc
Vout
2. NOR GATE static test. Vdd = 9Vdc Vin1
Vin2
0Vdc 0Vdc 9Vdc 9Vdc
0Vdc 9Vdc 0Vdc 9Vdc
Vout
Page 5 of 6 MOSFET Logic Revised: November 7, 2016
3. CMOS Inverter
VDD
100 current limit G
S
PMOS Q1
Vin
10K Rin
Q2
D
Vout
D NMOS
G
S
10K Rload
100 Shunt and current limit
Table CMOS inverter static test. Vdd = 9Vdc Vin 0v 9v
Vout
From DC sweep of CMOS inverter Vout to Vin Mark on plot, include the plot. Name Voltage VOH VOL VIL VIH
Page 6 of 6 MOSFET Logic Revised: November 7, 2016
