Benchmark NAND gate 1

Model

Most of the industrially integrated circuits contain NAND- and NOR-gates as basic elements. These types of gates may be economically produced and universally used. Figure 1 displays a circuit simulating a NAND-gate (see [GR94]). It consists of two n-channel enhancement MOSFETs (ME), one n-channel depletion MOSFET (MD), and a load capacitor C (cf. [SH68]). Digital MOS-circuits contain no other elements besides the MOSFETs as a rule. MOSFETs also take the function of controlled resistors. In our example, gate and source of the depletion transistor MD are connected, i.e., this MOSFET works as a controlled resistor here. The drain voltage of MD is constant at VDD = 5V . The bulk voltages are not at ground, VBB = −2.5V . The source voltages of both MEs are at ground. The gate voltages are controlled by the voltage sources V1 and V2 . The response at node 1 is only LOW (FALSE) if both, the input signal V1 and the input signal V2 , are HIGH (TRUE). The circuit model for the MOSFETs MD and ME is given in Figure 2 (see [SH68]). Later, we will show that the model leads to an index-2 DAE for the NAND-gate. The model used in [FG94] and [G¨ un95] is a regularization of this model and of index-1. The transistors MD and ME differ only in parameter values (see Table 1). The current ids flows from drain to source if and only if the controlling voltage Ugs between gate and source is larger than a technology dependent threshold voltage UT . The gate is isolated from the channel DS by a thin SiO2 -layer, i.e., the resistance Rsd between source and drain is almost infinitely high (∼ 1015 Ω). Using the charge-oriented modified nodal analysis we obtain the following DAE system u1 − u2 u7 − u1 − + Q˙ + Q˙ 1gd + Q˙ 1gs = 0 Rs Rd u2 − u1 u2 − u3 − Q˙ 1gs + Q˙ 1sb + + + iD bs (u12 − u2 ) Rs Rsd + iD ds (u3 − u2 , u1 − u2 , u12 − u2 ) = 0 1

(1)

(2)

VDD 4

3

MD

2 1

ME

7 5 6

11

V1 10 ME 8 9

V2

VBB 12

Figure 1: NAND-gate model u3 − u4 u2 − u3 − Q˙ 1gd + Q˙ 1db + − + iD bd (u12 − u3 ) Rd Rsd − iD ds (u3 − u2 , u1 − u2 , u12 − u2 ) = 0 u4 − u3 + IDD = 0 Rd +Q˙ 2gd + Q˙ 2gs + I1 = 0 u6 − u11 u6 − u7 − Q˙ 2gs + Q˙ 2sb + + + iE bs (u12 − u6 ) Rs Rsd + iE ds (u7 − u6 , u5 − u6 , u12 − u6 ) = 0 u7 − u1 u6 − u7 − + iE − Q˙ 2gd + Q˙ 2db + bd (u12 − u7 ) Rd Rsd − iE ds (u7 − u6 , u5 − u6 , u12 − u6 ) = 0 +Q˙ 3gd + Q˙ 3gs + I2 = 0 u9 u9 − u10 − Q˙ 3gs + Q˙ 3sb + + + iE bs (u12 − u9 ) Rs Rsd + iE ds (u10 − u9 , u8 − u9 , u12 − u9 ) = 0 2

(3) (4) (5)

(6)

(7) (8)

(9)

corresponds to

Figure 2: MOSFET model u10 − u11 u9 − u10 − + iE − Q˙ 3gd + Q˙ 3db + bd (u12 − u10 ) Rd Rsd − iE ds (u10 − u9 , u8 − u9 , u12 − u9 ) = 0 u11 − u6 u10 − u11 − =0 Rs Rd D − Q˙ 1db − Q˙ 1sb − iD bs (u12 − u2 ) − ibd (u12 − u3 ) − Q˙ 2db − Q˙ 2sb − iE (u12 − u6 ) − iE (u12 − u7 ) bs

− Q˙ 3db − Q˙ 3sb −

iE bs (u12

(10) (11)

bd

− u9 ) −

iE bd (u12

− u10 ) + IBB = 0 Q − C u1 = 0 Q1gd − qgd (u1 − u3 ) = 0 Q1gs − qgs (u1 − u2 ) = 0 Q1db − qdb (u3 − u12 ) = 0 Q1sb − qsb (u2 − u12 ) = 0 Q2gd − qgd (u5 − u7 ) = 0 Q2gs − qgs (u5 − u6 ) = 0 Q2db − qdb (u7 − u12 ) = 0 Q2sb − qsb (u6 − u12 ) = 0 Q3gd − qgd (u8 − u10 ) = 0 Q3gs − qgs (u8 − u9 ) = 0

3

(12) (13) (14) (15) (16) (17) (18) (19) (20) (21) (22) (23)

Q3db − qdb (u10 − u12 ) = 0 Q3sb − qsb (u9 − u12 ) = 0 u4 − VDD = 0 u12 − VBB = 0 u5 − V1 = 0 u8 − V2 = 0

(24) (25) (26) (27) (28) (29)

The current through the diode between bulk and source as well as the current through the diode between bulk and drain is given by the function   ( −is · exp( UUT ) − 1 for U ≤ 0 ibs (U ) = ibd (U ) = . (30) 0 for U > 0 The current through the controlled current source between drain and source is modelled by the function ids (Uds , Ugs , Ubs ) =   for Ugs − UT E ≤ 0 0 −β · (1 + δ · Uds ) · (Ugs − UT E ) for 0 < Ugs − UT E ≤ Uds   −β · Uds · (1 + δ · Uds ) · [2(Ugs − UT E ) − Uds ] for 0 < Uds < Ugs − UT E √ √  with UT E = UT 0 + γ · Φ − Ubs − Φ . The technical parameters for the MOSFETs MD and ME are given in Table 1.

is UT UT 0 β γ δ Φ

ME 10−14 A 25.85V 0.8V 1.748 · 10√−3 A/V2 0.0 V 0.02V−1 1.01V

MD 10−14 A 25.85V −2.43V −4 5.35 · 10√ A/V2 0.2 V 0.02V−1 1.28V

Table 1: Technical parameters The values for the resistances are chosen for all MOSFETs as Rs = Rd = 4Ω, 4

Rsd = 1015 Ω.

The load capacitance is constant of size C = 0.5 · 10−13 F . The capacitance between gate and source as well as that between gate and drain are modelled as linear capacitors, i.e., qgs (u) = qgd (u) = C1 · u with C1 = 0.6 · 10−13 F. The capacitance between bulk and drain as well as that between bulk and source may be modelled on two levels (see [GR94]): • Level A: Linear capacitances qdb (u) = qsb (u) = − C0 · u with C0 = 0.24 · 10−13 F. • Level B: Nonlinear capacitances   q  − C0 · ΦB · 1 − 1 −   qdb (u) = qsb (u) =  − C0 · 1 + u · u 4ΦB

u ΦB



with C0 = 0.24 · 10−13 F and ΦB = 0.87V.

2

Numerical results

Figure 3: Input signals V1 and V2

5

for u ≤ 0 for u > 0

Figure 4: Response at node 1

Figure 5: Current I1

References [FG94] U. Feldmann and M. G¨ unther. The DAE-index in electric circuit simulation. In I. Troch and F. Breitenecker, editors, Proc. IMACS Symposium on Mathematical Modelling, 4, pages 695–702, 1994. [GR94] M. G¨ unther and P. Rentrop. Suitable one-step methods for quasilinear-implicit ODEs. Technical Report TUM-M9405, Mathematisches Institut, TU M¨ unchen, 1994. [G¨ un95] M. G¨ unther. A joint DAE/PDE model for interconnected electrical networks. Mathematical Modelling of Systems, 1(1):000–111, 1995.

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Figure 6: Current I2 [SH68]

H. Shichman and D. A. Hodges. Insulated-gate field-effect transistor switching circuits. IEEE J. Solid State Circuits, SC-3:285–289, 1968.

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