ECE 342 Solid‐State Devices & Circuits 17. Differential Amplifiers
Jose E. Schutt-Aine Electrical & Computer Engineering University of Illinois
[email protected]
ECE 342 – Jose Schutt‐Aine
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Background • Differential Amplifiers – The input stage of every op amp is a differential amplifier – Immunity to temperature effects – Ability to amplify dc signals – Well-suited for IC fabrication because – (a) they depend on matching of elements – (b) they use more components
– Less sensitive to noise and interference – Enable to bias amplifier and connect to other stage without the use of coupling capacitors
ECE 342 – Jose Schutt‐Aine
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Differential Amplifiers • Practical Considerations – Both inputs to a differential amplifier may have different voltages applied to them – In the ideal situation with perfectly symmetric stages, the common-mode input would lead to zero output – Temperature drifts in each stage are often common-mode signals – Power supply noise is a common-mode signal and has little effect on the output signal
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MOS Differential Pair Assume current source is ideal Transistors should not enter triode region
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Common-Mode Operation
Input voltage vcm to both gates Difference in voltage between the two drains is zero
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Differential Input Voltage
Differential pair responds to differntial input signals by providing corresponding differential output signal between the two drains.
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MOS Differential Pair Assume current source is ideal vID=vgs1-vgs2 Output is collected as vD2-vD1
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MOS Differential Pair - If vID is positive, vD2-vD1 is positive vID>0 vgs1>vgs2 ID1 > ID2 vD1 lower voltage point than vD2 For proper operation, MOSFETS should not enter triode region
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DC Analysis IRD VD1 VDD 2 ID
VGS
CoxW 2L
VGS VT
LI VT CoxW
2
IRD VD 2 VDD 2 I ID 2
VSQ
ECE 342 – Jose Schutt‐Aine
LI VT CoxW
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Incremental Analysis 1 1 vg 2 vcm vid vg1 vcm vid 2 2 Neglecting the body effect
vin vo1 g m R 2
vin vo 2 g m R 2
R RD || rout
vo 2 vo1 AD g m RD' vin
' D
' D
' D
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Frequency Response
When driven by a low-impedance signal source, the upper corner frequency is determined by the output circuit
f high
1 2 Cout RD'
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Common-Mode Rejection Ratio
vo1 vo 2 RD 1 vicm vicm 2 RSS gm
Assume RSS >> 1/gm
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Common-Mode Rejection Ratio (a) For single-ended output:
vo1 vo 2 RD vicm vicm 2 RSS Acm
RD 1 , Ad g m RD 2 RSS 2
Ad CMRR g m RSS Acm ECE 342 – Jose Schutt‐Aine
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Common-Mode Rejection Ratio (b) For differential output:
vo 2 vo1 Acm 0 vicm vo 2 vo1 g m RD Ad vid CMRR ECE 342 – Jose Schutt‐Aine
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BJT Differential Pair
Assume perfect match between the devices and symmetry in the circuit
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BJT Differential Pair Rin 2r Base currents:
vin iin 2r vin ib1 2r
R rout1 || Rc1 rout 2 || Rc 2 ' C
Rc1 Rc 2 RC vin ib 2 2r
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BJT Differential Pair – Incremental Model ' v r g R vo1 g m v 1RC' g m RC' in m C vin 2 r ' v r g R vo 2 g m v 2 RC' g m RC' in m C vin 2 r ' Single-ended gain of first stage: AS 1 g m RC Double-ended differential gain (with vout=vo2-vo1): ' C
gm R AD 2
g
' C
mR
2
g
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m
R ' C
R
' C
r 17
BJT Differential Pair – General RB1 RB 2 RB RC1 RC 2 RC
Rin 2 RB 2 RE 1 2r AD
RC'
RE 1 r RB
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Differential Amplifiers - Observations • Observations – The differential pair attenuates the input signal of each stage by a factor of one-half cutting the gain of each stage by one-half – The double-ended output causes the two singleended gains to be additive – Thus, the voltage gain of a perfectly matched differential stage is equal to that of a single stage
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Remarks on Differential Amplifiers 1. In many applications, the differential amplifier is not fed in a complementary fashion 2. Rather, the input signal may be applied to one of the input terminals while the other terminal is grounded 3. In this case, the signal voltage at the emitters will not be zero and thus the resistor REE will have an effect on the operation 4. However, if REE is large (REE >> re) as is usually the case, vid will still divide equally between the 2 junctions 5. The operation of the differential amplifier will still be almost identical to that of the symmetrical feed and the CE equivalence can still be employed ECE 342 – Jose Schutt‐Aine
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Common Mode RC 2 RC RC RC1 RC Can show that
vc1 vicm
vc 2 vicm ECE 342 – Jose Schutt‐Aine
RC 2 REE re
RC RC 2 REE re 21
BJT Diff Pair - Common Mode vo vc1 vc 2 vicm
Acm
RC 2 REE re
Acm
RC 2 REE re
RC 2 REE
RC RC 2 REE
RC
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Example - I
=100 Collector resistance accurate within 1% Early voltage = 100V
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Example – I (cont’) Emitter current in both transistors is: 0.5 mA
VT 25 mV re 50 I E 0.5 mA Rid 2 1 re RE 2 101 50 150 40 k
vid Rid 40 0.8 vsig Rsig Rid 5 5 40 vo Total resistance in the collectors vid Total resistance in the emitters ECE 342 – Jose Schutt‐Aine
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Example - I (cont’) vo 2 RC 2 10 50 3 vid 2 re RE 2 50 150 10 Overall differential gain:
vo vid vo Ad 0.8 50 40 vsig vsig vid
RC RC Acm 2 REE RC common-mode gain
Where RC is the worst case variation in collector resistance
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Example – I (cont’) 10 Acm 0.02 5 104 2 200 Common-Mode Rejection ratio CMRR
Ad CMRR 20 log Acm 40 CMRR 20 log 98 dB 4 5 10
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Example – I (cont’) Input common-mode resistance: Ricm
Ricm
VA 100 ro 200 k I / 2 0.5 ro 1 REE || 101 200 k ||100k 6.7 M 2
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Example - II In the circuit shown, the dc bias current is 4 mA. If = 0.993, RB1 = RB2 = RB3 = 1,000 , RE = 30 , RC = 1.6 k, VCC = 10 V, and VBE(on) = 0.7 V, (a) Calculate the dc collector currents (b) Calculate the dc or quiescent collector voltages (c) Calculate the maximum peak value of vout before serious distortion results (d) Calculate the incremental differential voltage gain of the circuit (e) If the base resistor of Q2 is changed to RB2= 400 , calculate the dc collector current through each device
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Example - II
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Example - II (a) Assuming perfect match between Q1 and Q2, DC bias current will split equally IE1 = IE2 = 2mA. IC=IE=1.986 mA (b) The quiescent collector voltages will equal
VCC I C RC 10 1.986 1.6 6.82 V (c) Maximum collector voltage is 10 V (at cutoff) minimum is 0 V (at saturation).Therefore, positive peak voltage is 10-6.82 = 3.18 V, and negative peak is 6.82 V p-p voltage = 6.36 V ECE 342 – Jose Schutt‐Aine
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Example - II (d) The incremental differential voltage gain of the circuit is defined as: Calculate re and
vout vo 2 vo1 AD vin vin
26 26 re 13 2 IE
0.993 142 1 0.007
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Example - II Applying the gain equation and assuming rout >> 1.6 k gives
142 1600 AD 31.8 V / V 143 13 30 1000 (e) The voltage at the node above the dc current source can be found from
V1 I B1RB1 VBE ( on ) 1 I B1RE V2 I B 2 RB 2 VBE ( on ) 1 I B 2 RE ECE 342 – Jose Schutt‐Aine
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Example - II Effects of non-balance
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Example - II
1 I B1 1 I B 2 4 mA I B 2 14.8 A
I B1 13.1 A
The corresponding emitter and collector currents are
I E1 1.88 mA I C1 1.86 mA
I E 2 2.12 mA I C 2 2.10 mA
The two quiescent collector voltages are no longer equal, resulting in a nonzero quiescent output voltage
VCQ 2 10 1.6 2.1 6.64 V VCQ1 10 1.6 1.86 7.02 V ECE 342 – Jose Schutt‐Aine
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Example - II VoutQ VCQ 2 VCQ1 6.64 7.02 0.38 V Nonzero quiescent voltage serious consequences when this stage is followed by additional gain stages, creating an output offset voltage when the inputs are shorted together
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Nonideal Characteristics Input offset voltage of MOS differential pair
Mismatch can result in a dc output voltage Vo (output dc offset voltage)
Vos=Vo/Ad is input offset voltage ECE 342 – Jose Schutt‐Aine
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Nonideal Characteristics If Vos is applied (differentially) at the input, a zero voltage difference should result at the output •
Factors contributing to dc offset voltage 1. 2. 3.
Mismatch in load resistance Mismatch in W/L Mismatch in VT
2 Vov RD Vov W / L Vos VT 2 2 W /L 2 2
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Input Offset Voltage for BJT Diff Pair •
Offset results from 1. 2. 3.
Mismatch in RC’s Mismatch in Mismatch in junction area
2
Vos VT
ECE 342 – Jose Schutt‐Aine
RC I S RC I S
2
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Offset Current for BJT Diff Amp In a perfectly symmetric differential pair, the 2 input terminals carry equal dc current to support bias I /2 I B1 I B 2 1 Mismatches (primarily from ) make the 2 input dc currents unequal
I os I B1 I B 2
I os I B ECE 342 – Jose Schutt‐Aine
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Differential-to-Single-Ended Conversion
ECE 342 – Jose Schutt‐Aine
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Beyond first stage, signal can be converted from differential to single-ended
-
Simply ignore the drain current in Q1 and eliminate its drain resistor
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Differential-to-Single-Ended Conversion • Limitations – Factor of 2 (6 dB) is lost in the gain if drain current of Q1 is not used – Much better approach consists of using drain current of Q1 – Active load approach allows to perform conversion without loss of gain by making use of drain current in Q1
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MOS Differential Amp with Active Load Replacing drain resistances with current sources, results in much higher voltage gain and savings in chip area in diff amp
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MOS Differential Amp - Equilibrium
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MOS Differential Amp with Active Load Current mirror action makes it possible to convert the signal to single-ended form without loss of gain.
The differential gain is:
vo Ad g m ro 2 || ro 4 vid If ro 2 ro 4 ro
1 Ad g m ro 2 ECE 342 – Jose Schutt‐Aine
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MOS Differential Amp with Active Load The active-loaded MOS differential amplifier has a low common-mode gain high CMRR
The common-mode gain is:
vo ro 4 1 Acm vicm 2 RSS 1 g m 3ro 3
RSS is internal impedance of current Usually, g m 3ro 3 1 and ro 3 ro 4 source
Acm
1 2 g m 3 RSS ECE 342 – Jose Schutt‐Aine
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MOS Differential Amp with Active Load Since RSS is large, Acm will be small
Ad g m ro 2 || ro 4 2 g m 3 RSS CMRR Acm If ro 2 ro 4 ro and g m 3 g m CMRR g m ro g m RSS ECE 342 – Jose Schutt‐Aine
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BJT Differential Amp with Active Load
Current mirror & active load
Differential stage
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Active Loaded BJT Pair – Incremental Model
Virtual ground develops at common-emitter terminal
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BJT Differential Amp with Active Load Output resistance is parallel equivalent of the output resistance of the differential pair and the output resistance of the current mirror
The differential gain is:
vo Ad g m ro 2 || ro 4 vid If ro 2 ro 4 ro
1 Ad g m ro 2
The differential input impedance is:
Rid 2r ECE 342 – Jose Schutt‐Aine
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BJT Differential Amp with Active Load The active-loaded BJT differential amplifier has a low common-mode gain high CMRR
The common-mode gain is:
vo ro 4 Acm 3 REE vicm It is assumed that , g m 3 g m 4
REE is internal impedance of current source
and r 4 r 3 and ro 3 r 3 , r 4 ECE 342 – Jose Schutt‐Aine
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BJT Differential Amp with Active Load Ad 3 REE CMRR g m ro 2 || ro 4 Acm ro 4 If ro 2 ro 4 ro 1 CMRR 3 g m REE 2 For large CMRR, bias current source should have large output resistance REE ECE 342 – Jose Schutt‐Aine
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Frequency Response of MOS Diff Amp •
Resistively Loaded 1. Resistance RSS is between node S and ground 2. Capacitance CSS is between node S and ground 3. CSS includes Cdb, Cgd, and Csb
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Frequency Response – Differential Half Gain function of differential half will be identical to that of common-source amplifier
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Frequency Response – Common-Mode CSS/2 will form dominant real‐axis zero at much lower frequency Zero dominates frequency dependence of Acm
Common-mode gain is found by analyzing the effect of a mismatch RD in RD ECE 342 – Jose Schutt‐Aine
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Frequency Response – Common-Mode RD RD Acm ( s ) 1 sCSS RSS 2 RSS RD Acm picks up a zero on the negative real axis of the complex s-plane. The frequency is Z
1 Z CSS RSS 1 fZ 2 CSS RSS ECE 342 – Jose Schutt‐Aine
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Frequency Response – Common-Mode Gain
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Frequency Response – Differential Gain
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Frequency Response – CMRR
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Frequency Response – Actively Loaded MOS
Cm Cgd 1 Cdb1 Cdb 3 Cgs 3 Cgs 4
Capacitance at input node
CL Cgd 2 Cdb 2 Cgd 4 Cdb 4 Cload
Capacitance at output node
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Frequency Response – Actively Loaded MOS Cm 1 s 2 g m3 vo 1 Ad ( s ) g m Ro vid 1 sCL Ro 1 s Cm g m3 1 First pole: f P1 2 CL Ro Second pole: f P 2 Zero at:
g m3 g m3 fT / 2 2 Cm 2 2C gs 3 2 g m3 fZ fT 2 Cm
Mirror pole and zero occur at very high frequencies ECE 342 – Jose Schutt‐Aine
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Actively Loaded MOS - Transconductance
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CMOS OP Amp Example In the differential amplifier shown, Q1 and Q2 form the differential pair while the current source transistors Q4 and Q5 form the active loads for Q1 and Q2 respectively. The dc bias circuit that establishes an appropriate dc voltage at the drains of Q1 and Q2 is not shown. The following specifications are desired: differential gain Ad = 80V/V, IREF = 100 A, the dc voltage at the gates of Q6 and Q3 is +1.5V; the dc voltage at the gates of Q7, Q4 and Q5 is –1.5V. The technology available is specified as follows: nCox=3pCox = 90A/V2; Vtn=|Vtp|=0.7V, VAn=|VAp| = 20V. Specify the required value of R and the W/L ratios for all transistors. Also, specify ID and VGS at which each transistor is operating. For dc bias calculations, you may neglect channel-length modulation. Fill in the entries in the table provided to show your results. ECE 342 – Jose Schutt‐Aine
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CMOS OP Amp Example
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CMOS OP Amp Example I REF
1.5 ( 1.5) 3V 100 A R 30k 0.1mA R
Drain currents are determined by symmetry and inspection VGS values are also determined by inspection for all transistors except Q1 and Q2. To determine VGS for Q1 and Q2, we do the following: the equivalent load resistance will consist of ro1 in parallel with ro4 for Q1 and ro2 in parallel with ro5 for Q5. Since the ro’s are equal, this corresponds to ro/2. We have:
ro 2 Ad 2 80 g m Ad g m 0.4mA / V ro 2 400k ECE 342 – Jose Schutt‐Aine
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CMOS OP Amp Example 2I D 2 I D 2 0.05 gm Vov 0.25 Vov gm 0.4 Take polarity into account for PMOS
VGS 1,2 0.25 VT 0.95 To find W/L ratios, use
2I D W W 2 I D Cox (VGS VT ) 2L L Cox (VGS VT ) 2 taking into account PMOS and NMOS devices separately ECE 342 – Jose Schutt‐Aine
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CMOS OP-AMP DESIGN TABLE Q1
Q2
Q3
Q4
Q5
Q6
Q7
Units
Cox
30
30
30
90
90
30
90
A/V2
ID
50
50
100
50
50
100
100
A
VGS
-.95
-.95
-1
+1
+1
-1
+1
V
W/L
57.3
57.3
74 1.
12.3
12.3
73.1
24.7
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2-Stage CMOS Op Amp
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2-Stage CMOS Op Amp Two-stage configuration with two power supplies which can range from +/- 2.5 V for 0.5 m technology to +/- 0.9 V for 0.18 m technology. IREF is generated either externally or using on-chip CKT. Current mirror formed by Q5-Q8 supplies differential pair Q1-Q2 with bias current. The W/L of Q5 is selected to control I. The diff pair is actively loaded by current mirror Q3-Q4
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2-Stage CMOS Op Amp Second stage is Q6 which is a CS amplifier for which Q7 is the current source. A capacitor Cc is included for negative feedback to enhance the Miller effect through Q6 compensation. This op amp does not have a low output impedance and is thus not suited for driving a lowimpedance load. The W/L ratios are given and listed below:
W/L
Q1
Q2 Q3
Q4
Q5
Q6
Q7
Q8
20/0.8
20/0.8 5/0.8
5/0.8
40/0.8
10/0.8
40/0.8
40/0.8
Let I REF 90 A, Vtn 0.7 V , Vtp 0.8 V
nCox 160 A / V , p Cox 40 A / V 2
ECE 342 – Jose Schutt‐Aine
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2-Stage CMOS Op Amp | VA | for all devices 10 V , VDD VSS 2.5 V •
Voltage Gain
First stage: A1 g m1 ro 2 || ro 4 Since Q8 and Q5 are matched, I = IREF, Q1, Q2, Q3 and Q4 will have I/2 = 45 A. IQ7=IREF = 90 A = IQ6 Let VGS - VT = Vov (overdrive voltage) ECE 342 – Jose Schutt‐Aine
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2-Stage CMOS Op Amp 1 2 From I D Cox W / L Vov 2 We find Vov for each transistor.
2I D Transconductance is: g m Vov VA ro ID ECE 342 – Jose Schutt‐Aine
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2-Stage CMOS Op Amp – Voltage Gain Gain for first stage: A1 g m1 ro 2 || ro 4
A1 0.3 222 || 222 33.3 V / V Gain for second stage: A2 g m 6 ro 6 ro 7
A2 0.6 111||111 33.3 V / V Overall dc open loop gain is (-33.3)(-33.3) = 1109 V/V 20 log1109 = 61 dB ECE 342 – Jose Schutt‐Aine
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2-Stage Op Amp Design Table Q1
Q2 Q3
Q4
Q5
Q6
Q7
Q8
W/L
20/0.8
20/0.8 5/0.8
5/0.8
40/0.8
10/0.8
40/0.8
40/0.8
ID(A)
45
45
45
45
90
90
90
90
|Vov| (v)
0.3
0.3 0.3
0.3
0.3
0.3
0.3
0.3
|VGS| (v)
1.1
1.1 1.0
1.0
1.1
1.0
1.1
1.1
gm(mA/V)
0.3
0.3 0.3
0.4
0.6
0.6
0.6
0.6
ro(k)
222 222 222
222
111
111
111
111
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2-Stage Op Amp – Frequency Response Incremental Circuit
Gm1 g m1 g m 2 R1 ro 2 || ro 4 , C1 C gd 4 Cdb 4 C gd 2 Cdb 2 C gs 6 ECE 342 – Jose Schutt‐Aine
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2-Stage Op Amp – Frequency Response Gm 2 g m 6 R2 ro 6 || ro 7 , C2 Cdb 6 Cdb 7 C gd 7 CL CL is the load capacitance (usually large) C2 C1 Vo Gm1 Gm 2 sCC R1 R2 1 sA s 2 B Vid ECE 342 – Jose Schutt‐Aine
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2-Stage Op Amp – Frequency Response A C1 R1 C2 R2 CC Gm 2 R1 R2 R1 R2
B C1C2 CC C1 C2 R1 R2 Transmission zero at s = sZ with
Gm 2 Z CC Two poles that are the root of the denominator
1 p1 R1CC Gm 2 R2
p2 ECE 342 – Jose Schutt‐Aine
Gm 2 C2 76
