Digital to Analog Converter Design Douglas A. Mercer (’77) Fellow Analog Devices Inc. Wilmington, MA USA ([email protected]) RPI IEEE Student Chapter October 22, 2008

RPI IEEE Student Chapter October 2008

Content The tutorial will concentrate on D/A converter design in MOS process technologies and cover these three broad topics. 1) A brief look at Digital to Analog conversion first principles including a description of the D/A function and the key specifications that define the performance of a D/A. 2) Common D/A architectures will be explored with these first principles in mind. The advantages and disadvantages of each will discussed. 3) Case studies of example CMOS implementations will be included. RPI IEEE Student Chapter October 2008

D/A Converter Applications Used at the end of a digital processing chain where analog signals are required. • Digital Audio – CD / MP3 Players, HD radio, Digital telephones

• Digital Video – DVD Players, DTV, Computer displays

• Industrial Control Systems – Motor control, valves, transducer excitation

• Waveform Function Generators, test equipment • Calibration / tuning in embedded systems, built-in self test RPI IEEE Student Chapter October 2008

D/A Transfer function Analog output is represented as a fraction of the Reference

Di Ao = N Ref 2

Where: Ao = Analog output Di = Digital input code N = Number of digital input bits ( resolution ) Ref = Reference Value ( full-scale )

RPI IEEE Student Chapter October 2008

D/A Transfer function (graphic form) Full Scale

Ideal relationship

7/8 6/8 1 LSB 5/8

Offset error

4/8 Gain error

3/8 2/8 1/8 0

000 001 010 011 100 101 110 111 Digital Input Code

RPI IEEE Student Chapter October 2008

D/A Transfer function Differential Nonlinearity (DNL) Integral Nonlinearity (INL) The maximum deviation of the analog output from the ideal straight line passing through the end points

The maximum deviation of the difference in the analog output between two adjacent codes from the ideal step size

Monotonicity A D/A is monotonic if the output either increases or remains constant as the input code increases

-INL -DNL= 1LSB Monotonic +INL

RPI IEEE Student Chapter October 2008

ANALOG OUTPUT

Digital Input can’t precisely represent continuous analog output: Quantization Noise The noise power due to quantization is:

7/8 6/8

q2/12

5/8 4/8

Where: q = 1 LSB 1 LSB = Full-scale Span / 2N

3/8 2/8 1/8 001 010 011 100 101 110 111

SNR = N * 6.02 dB + 1.7 dB ( quantization noise limit )

Digital INPUT

+/- ½ LSB quantization noise error RPI IEEE Student Chapter October 2008

D/A First Principles What Components do we need: • Reference • May be either Voltage or Current

• Reference Divider ( Voltage or Current, Time ) • May be Resistor, Capacitor, or Transistor based

• Switches and, or combiner

RPI IEEE Student Chapter October 2008

MOS device as a voltage switch NMOS I/V curves For accurate transfer of the Voltage, Vsource should equal Vdrain, i.e. current through switch should be zero For NMOS, Vcontrol should be much greater than Voutput For a fixed gate voltage, Ron of switch will depend on Voutput 40 35 30

Control

25

Output

Id 20 uA 15 10 5

Voltage Mode

0 0

.2

.4

.6

RPI IEEE Student Chapter October 2008

.8 1 Vdrain

1.2

1.4

1.6

1.8

MOS device as a voltage switch PMOS I/V curves For accurate transfer of the Voltage, Vsource should equal Vdrain, i.e. current through switch should be zero For PMOS, Vcontrol should be much less than Voutput For a fixed gate voltage, Ron of switch will depend on Voutput 0

-2.5

Control

-5 -7.5

Output Id -10 uA -12.5 -15 -17.5 -20

Voltage mode

-1.6

-1.2

RPI IEEE Student Chapter October 2008

-.8 Vdrain

-.4

0

MOS device as a current switch NMOS I/V curves For accurate transfer of the Current, Isource should equal Idrain, i.e. leakage current to control node should be zero For NMOS, Vcontrol should be equal to or greater than Voutput When sinking current, Vgs will be what ever is needed to support Iref 40 35

Sink 30 25

Iref Control Output

Id 20 uA 15 10 5 0

Current mode

0

.2

.4

.6

Source RPI IEEE Student Chapter October 2008

.8 1 Vdrain

1.2

1.4

1.6

1.8

MOS device as a current switch PMOS I/V curves For accurate transfer of the Current, Isource should equal Idrain, i.e. leakage current to control node should be zero For PMOS, Vcontrol should be equal to or less than Voutput When sourcing current, Vgs will be what ever is needed to support Iref 0 -2.5

Sink

-5 -7.5

Iref Control

Id -10 uA -12.5 -15

Output

Source

-17.5 -20

Current mode

-1.6

-1.2

RPI IEEE Student Chapter October 2008

-.8 Vdrain

-.4

0

D/A First Principles MOS device as a switch Things to keep in mind when using MOS device as a switch. 1. Will the switch have current flowing through it? 2. If so, which direction source, sink , or both? 3. Where is the on/off control voltage with respect to the input and output of the switch? RPI IEEE Student Chapter October 2008

D/A First Principles Time Reference Divider “One Bit” DAC Pulse Width Modulation

RPI IEEE Student Chapter October 2008

D/A First Principles Voltage Reference Divider Vout

+Vref

Standard resistor divider uses 2N equal resistors ( and switches ).

Vgnd R1 R2 R3 R4 R

Vout must be buffered to drive a load.

Rn R

2R 2R 2R

R 2R

Vout 2R

+Vref Vgnd RPI IEEE Student Chapter October 2008

R/2R ladder uses fewer unit resistors (3N+1), but current flows through switches, so Ron is of concern.

D/A First Principles Current Reference Divider R

Iref (Vref) 2R

R

R

2R

2R

R/2R ladder can be used for current division as well

2R

All the switches are referenced to the same voltage

2R

Voltage at Iout must equal Vgnd Iout Vgnd

Ron of switch is in series with 2R leg. Ron should be small with respect to 2R. Should Ron be constant, or scaled with bit position? RPI IEEE Student Chapter October 2008

D/A First Principles R/2R driven with equal currents I

I

I

I

R

I

R

I

Alternatively, R/2R ladder can be driven at each splitting node.

I

R

R

Iout

Simple to make all currents and switches the same size and scale them with divider network.

2R

2R

2R

2R

RPI IEEE Student Chapter October 2008

2R Vgnd

Transistors As Current Source W/L

Iout IoutB

• Weighted unit currents ( equal or binary ) – MOS matching is a function of gate area and gate voltage, Vgs - Vt – Statistical averaging across large collection of smaller devices will result in improved matching performance. Pelgrom, JSSC Oct 1989

RPI IEEE Student Chapter October 2008

Matching of MOS Transistors VT0 = zero bias threshold voltage

2 A 2 2 σ 2 (VT 0 ) ∝ VT 0 + SVT D 0 WL

2

β = µCox

W L

σ (β ) ∝ 2

Aβ

WL

+ S β2 D 2

Where: AVT0 , Aβ, SVT0, Sβ are process constants W, L gate dimensions, D distance between devices Pelgrom, JSSC Oct 1989

RPI IEEE Student Chapter October 2008

Current Source Array Layout Simple Diagonal used for spatial averaging to remove errors from process gradients. This method can be implemented with the fewest inter-connect layers. Source Drain Source Drain Source US Patent 5,568,145 1996

RPI IEEE Student Chapter October 2008

Design Topics CMOS Current steering D/A • • • •

Basic structure Matching and DC linearity Output Impedance Switch Gate Driver

RPI IEEE Student Chapter October 2008

CMOS Current steering D/A • Fine Line CMOS technologies are the process of choice for switched current D/As. • Thermometer coding and unit elements used extensively to improve DNL and reduce nonlinear output glitches. • D/As with resolutions from 8 bits to 16 bits are split into two or more segments. • PMOS current sources and switches have been more common than NMOS.

RPI IEEE Student Chapter October 2008

CMOS D/A Basic Structure AVdd 1.0V

Ref Amp

Current Source Array Reference ACom

31 MSB Switches

15 ISB Switches

5 LSB Switches

Switch Drivers / Decode DVdd

DCom

CMOS Data Inputs

Three major functional blocks: 1) CMOS decode Logic / Clock / switch drivers 2) Output current source array 3) Analog bias blocks, Band-gap reference RPI IEEE Student Chapter October 2008

I out

Clock

Comparison of Segmentation Approaches Paper Reference

Segmentation

Process node

14 bit DNL

14 bit INL

Mercer, 1996

ISLPED 5 – 4 – 3 (5)

0.6u

+4.0 LSB

-3.6 LSB

Mercer, 2006

CICC 5 – 4 – 5

0.18u

-2.6 LSB

+3.0 LSB

Schafferer, ISSCC 6 - 8 2004

0.18u

-0.7 LSB

-1.2 LSB

Lin, JSSC 8 - 2 Dec. 1998

0.35u

-1.6 LSB

-3.6 LSB

Van der Plas, JSSC 8 - 6 Dec 1999

0.5u

+0.15 LSB

+0.3 LSB

(Un-calibrated) RPI IEEE Student Chapter October 2008

Chip Photographs AD9707 (2005)

AD9764 (1995)

2 mm 0.6u process

1.5 mm 0.18u process RPI IEEE Student Chapter October 2008

Current Source Architecture Current Source Bias

VDD

31 MSBs

Cascode Bias

MP1

ISB,LSB Splitter MP2 15 ISBs 5 LSBs

Analog Outputs

• 5-4-5 Segmentation • Splitter servo matches MSB current source bias • Monotonicity guaranteed if MSB currents match Schofield, et al., ISSCC, 2003

RPI IEEE Student Chapter October 2008

Topics CMOS Current steering D/A • • • •

Basic structure Matching and DC linearity Output Impedance Switch Gate Driver

RPI IEEE Student Chapter October 2008

Scaling PMOS current sources • Larger Vgs – Vt → Better Matching, but larger supply headroom required – 0.6u, 5V supply, Vgs – Vt = 600 mV (AD9764,54) – 0.35u, 3.3V supply, Vgs – Vt = 450 mV (AD9744) – 0.18u, 1.8V supply, Vgs – Vt = 260 mV (AD9707)

• PMOS Vt scaling also helps headroom, – 0.6u, Vt = 935 mV – 0.18u, Vt = 675 mV ( thick oxide device ) RPI IEEE Student Chapter October 2008

DNL (14b)

INL (14b)

Linearity From Raw Matching

( 0.18u process ) RPI IEEE Student Chapter October 2008

Self Calibration Current Source Bias

1. Master calibrated to To Lower and mid-scaled MSB source Cascode Switches 2. MSBs, ISB-LSB sub-DAC calibrated to master Schofield, et al., IEEE ISSCC, Feb 2003 RPI IEEE Student Chapter October 2008

Master

CAL SAR

• 6b 2-4 segmented CALDAC • Cascode bias switched Cascode to replica Bias • 6b SAR calibrates to 14b in two steps:

VDD

6 Bit Calibration DAC VDD Current Source Bias

MP1

MP2

512 LSBs

16 LSBs

MSB Cell 16X

16X

16X

8X

4X

2X

1X

Switches

Cascode Bias

Return current common to all Cal DACs

Cascode Bias

Analog Outputs

•+/- 8 LSB trim range •Discarded current returned to voltage equal to drain of MP1 to insure proper current split RPI IEEE Student Chapter October 2008

Self Calibrated INL/DNL

INL

DNL

• 0.25 LSB calibration resolution should at best provide 0.25 LSB DNL RPI IEEE Student Chapter October 2008

Calibration DAC Values 10 8

25C 6 4 2 0 15 12

85C

9 6 3 0 8 6

-40C 4 2 0 25

26

27

28

29

30

31

32

33

34

35

• Device calibrated at three temperatures. • 25C distribution 7 codes majority in just three. • 85C distribution tighter at 4 codes. • Wider at -40C due in part to temperature dependence of mobility. • Center shift due to comparator offset shift.

RPI IEEE Student Chapter October 2008

Topics CMOS Current steering D/A • • • •

Basic structure Matching and DC linearity Output Impedance Switch Gate Driver

RPI IEEE Student Chapter October 2008

Code Dependent Output Impedance Unit Current Cell

Aim is to make Rsw much larger than RL.

Rsw

RL

Varying numbers of Rsw in parallel with RL results in a non-linear output voltage. RPI IEEE Student Chapter October 2008

Code Dependent Output Impedance 2

I unit RL N u INL = 4 Rsw

2

Where: Iunit is the magnitude of the unit current source RL is the load impedance Nu is the number of unit current elements Rsw is the impedance of a unit current source

What we actually need to know is Rsw to design the DAC unit element. Rearranging the formula gives us the required Rsw for a given overall DAC resolution and ½ LSB INL error:

Rsw = RL N u 2

N R −1

Where: RL is the load impedance Nu is the number of unit current elements NR is the number of bits for the overall DAC

RPI IEEE Student Chapter October 2008

Code Dependent Output Impedance Range

ZSW

ZSW

ZSW

ZSW

p1 IMD gds C 1

ZL

gm z1

Double Cascode Single Cascode

• Zout = (code dependent Zsw) || ZL • # elements changing in a sinewave→ diff IMD • Pole/Zero analysis for IMD in range of interest – Double cascode provides best IMD Van den Bosch, et al., Proc. ICECS, 1999 Luschas, et al., Proc. ISCAS, 2003 RPI IEEE Student Chapter Schofield, et al., IEEE ISSCC, 2003 October 2008

Freq

Active Second Cascode AVDD MP1 AVDD

MASTER

MP2

FCAS

AVDD

MP6

(3.3V to 1.8V) AVDD

MP7 AVDD

MP3 AVDD MP4

G1

AVDD

ACAS MP5

G2

MP8 AVDD

• Back gate bias of MP3,4,5,8 a function of AVDD • Active cascode, MP3, driven to maintain Vds just in saturation for all AVDD RPI IEEE Student Chapter October 2008

Topics CMOS Current steering D/A • • • •

Basic structure Matching and DC linearity Output Impedance Switch Gate Driver

RPI IEEE Student Chapter October 2008

Driving The Current Switch CS

Q

QB

Constant ZSWITCH VSB

VSB generator

VSB generator

• VSB generator mimics switch diode to ground
Limits swing to be no more than needed • Low switch crossover → constant ZSWITCH
Constant ZSWITCH = low VCS/output glitch energy = symmetric output → low HD2 Mercer, IEEE JSSC, vol. 29, no. 10, October 1994

RPI IEEE Student Chapter October 2008

Sensitivity to VSB Activity Low Activity SWDRV

VSB

High Activity

Time

• Would like to have local Vsb generator for isolation • Local VSB = Small Area, Low Power Low Power = High ZOUT → long settling time • Incomplete settling at high activity = code dependent switching delay RPI IEEE Student Chapter October 2008

Switch Driver Bias VDD MP3

MP2 VSB

MN2

MP1

Bias1

Bias2

MN1 17uA

• VSB generator, MP1 mimics switch diode with respect to ground • MN1 ( Bias2 ) sets current level • Feedback through MN2 helps transient recovery Mercer, IEEE JSSC, vol. 29, no. 10, October 1994

RPI IEEE Student Chapter October 2008

Output Current Switch Driver VDD

• NMOS switches (MN1,4) draw pulse of current from driver bias. • PMOS devices replace current pulse from VDD.

MP2

MP3

MP4

VSB

• Net current supplied by bias much smaller leading to lower standing current while also providing faster recovery time. • Power more dynamic, now more a function of sample rate and data pattern.

MP1

MN1

Q

Switch Driver Bias G1

MN2

AGND QB From Latch

MN3

G2 MN4

RPI IEEE Student Chapter October 2008

Performance Summary Max Fsample Resolution DNL INL SFDR ( at 10MHz) IMD (to 70MHz) NSD

200 14