Fast Analog to Digital Converter Developments

LAB : Laboratoire d’Astrophysique de Bordeaux Fast Analog to Digital Converter Developments Stephane GAUFFRE, Philippe CAÏS, Benjamin Quertier Labora...
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LAB : Laboratoire d’Astrophysique de Bordeaux

Fast Analog to Digital Converter Developments Stephane GAUFFRE, Philippe CAÏS, Benjamin Quertier Laboratoire d’Astrophysique de Bordeaux

AAVP workshop

8-10 December 2010, University Of Cambridge

LAB : Laboratoire d’Astrophysique de Bordeaux

Outline  ADC designed by LAB Herschel  ALMA

 Ultra fast ADC

Current Design Future Design

 AAVP context

Low Power ADC

AAVP workshop

8-10 December 2010, University Of Cambridge

LAB : Laboratoire d’Astrophysique de Bordeaux



ADC designed by LAB: –

Flash architecture used for our applications.  Ultra fast ADC (>1GS/s)  Large analog bandwith (≥1 octave)  Low resolution (≤6-bit)

AAVP workshop

8-10 December 2010, University Of Cambridge

LAB : Laboratoire d’Astrophysique de Bordeaux



ADC designed by LAB: Herschel Space Observatory (HiFi) – – – –

Cooperation between three groups from Bordeaux (LAB, IMS) and Toulouse (CESR), 2002 2-bit ADC at 500MS/s designed in 0.8µm BiCMOS Technology from AMS for ESA space program (HSO). Flash architecture Power consumption: ≈280mW

AAVP workshop

8-10 December 2010, University Of Cambridge

LAB : Laboratoire d’Astrophysique de Bordeaux



ADC designed by LAB: ALMA – – – –

Cooperation between two groups from Bordeaux (LAB, IMS), 2005 3-bit ADC at 4GS/s designed in 0.25µm SiGe BiCMOS Technology from STm Flash architecture Power consumption: ≈1.45W

VH

2-4 GHz

Amplifier

OTA

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D-Latch

Output buffer

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D-Latch

Output buffer

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D-Latch

Output buffer

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Bandgap Adaptater amplifier

4 GHz

Clock buffer

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VL

AAVP workshop

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FDL encoder

8-10 December 2010, University Of Cambridge

LAB : Laboratoire d’Astrophysique de Bordeaux



ADC designed by LAB: ALMA – – – –

The 4GS/s 3-bit ADC runs with 3 1:16 DMUX circuits designed by LAB with STm 0.25µm SiGe BiCMOS technology. Total power consumption: 1.45+0.7×3=3.55W (power supply at 2.5V) Wafers specialy manufactured for the ALMA project (>800 sampler chips and >2000 DMUX chips) Around 300 Digitizer modules assembled, tested and validated to equip 66 antennas

AAVP workshop

8-10 December 2010, University Of Cambridge

LAB : Laboratoire d’Astrophysique de Bordeaux



Ultra fast ADC: – – – –

To design an ultra fast ADC, we must find a finer technology. We can have access to the 65nm CMOS technology from STm via the broker in IC, the CMP. ⇒ multi-projects wafer Ft=210GHz ⇒ high speed component CMOS tech. & Power supply=1.2V ⇒ low power consumption

AAVP workshop

8-10 December 2010, University Of Cambridge

LAB : Laboratoire d’Astrophysique de Bordeaux



Ultra fast ADC: Track And Hold Circuit (65nm CMOS techn.) – – – – – –

Cooperation between three groups from Bordeaux (LAB, IMS, CENBG), 2010 8GS/s Track and Hold circuit with an analog bandwith of 7.5GHz (0.5-8GHz) Designed with 65nm CMOS technology from STm ENOB≈4.5bit, Input Refllexion3W)

Internal DMUX

AAVP workshop

DMUX

8-10 December 2010, University Of Cambridge

LAB : Laboratoire d’Astrophysique de Bordeaux



Ultra fast ADC: Future design in 65nm CMOS Technology – –

In 2011, a new 8GS/s Track and Hold circuit will be designed to improve the linearity in order to obtain an ENOB superior to 6 bits. This new Track and Hold circuit will be:  designed with 65nm CMOS technology from STm.  used in a new ultra fast ADC. • A 8GS/s 6-bit flash ADC (2012): prototype version in which will be implemented  Calibration circuit to compensate the comparator offsets deviation due to the small size of the NMOS transistor  Add scrambler circuit to mix a pseudo random pattern to digital data in order to capture ADC outputs using high speed receivers of standard FPGA (6.5GS/s) ⇒ Internal 1:4 DMUX will be replaced by 1:2 DMUX ⇒ No need of external DMUX  Chip-On-Board • A 8GS/s 6-bit flash ADC (2013): Final version  Packaged version (fcBGA)

AAVP workshop

8-10 December 2010, University Of Cambridge

LAB : Laboratoire d’Astrophysique de Bordeaux



Ultra fast ADC: 8GS/s 6-bit ADC (65nm CMOS techn.) –

Rough estimation of power consumption if 6-bit designed with the same flash architecture as 3-bit ADC (with scrambler circuit and internal1:2 DMUX circuits) 1750

Power in mW

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Resolution (Number of bit) AAVP workshop

8-10 December 2010, University Of Cambridge

LAB : Laboratoire d’Astrophysique de Bordeaux



AAVP Context –

ADC technical parameter requirements:  Resolution : 4-6bit  Sample rate: ≥3GS/s  Bandwith: • AA-lo: 70MHz to 450MHz • AA-mid: 400MHz to 1.4GHz  Power: 250k€ (to be confirmed), depends on the number of ADC needed

AAVP workshop

8-10 December 2010, University Of Cambridge

LAB : Laboratoire d’Astrophysique de Bordeaux

Thank you for your ATTENTION AAVP workshop

8-10 December 2010, University Of Cambridge