MIT International Journal of Electronics and Communication Engineering, Vol. 4, No. 1, January 2014, pp. 1–6 ISSN 2230-76 72 © MIT Publications

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Design of CMOS Full Adder Application Specific Integrated Circuit Neha Rani Department of E & C Assistant Professor, MIT Moradabad, U.P., INDIA [email protected]

Alpana Singh Department of E & C Assistant Professor, MIT Moradabad, U.P., INDIA [email protected]

Ritika Tandon Department of E & C Assistant Professor, MIT Moradabad, U.P., INDIA [email protected]

Priyanka Saxena Department of E & C Assistant Professor, MIT Moradabad, U.P., INDIA [email protected]

ABSTRACT Application specific full custom design integrated circuit is a methodology for making a logic cell, circuit or layout specification. Full custom design circuit is the part of Application specific integrated circuit. A gate array or uncommitted logic array as an approach to the design and manufacture of application specific integrated circuit. It requires custom chip fabrication using a complete set of unique masks which define the semiconductor processing of the design. A full custom IC includes some logic cells that are customised using microprocessor full custom IC. In most recent CMOS feature sizes (e.g., 90 nm and 45 nm); leakage power dissipation has become an overriding concern for VLSI circuit designers. A goal of this paper is to evaluate the performance of one-bit Hybrid full adder cell, provide the technical community with a basic understanding of the technologies and options available in the Integrated Circuits (ICs) that they design and use. Hybrid-CMOS design styles utilize various CMOS logic style circuit to build new Full Adder with desired performance. Keywords: Power consumption, ASIC, full custom circuit CMOS CAD tool, and Programmable gate array.

I. INTRODUCTION An integrated circuit (IC) customized for a particular use, rather than intended for general-purpose use. For example, a chip designed solely to run a cell phone is an ASIC. Full-custom IC design is limited to ICs that are to be fabricated in extremely high volumes. “Application Specific Integrated Circuits” (ASICs) are changing the way electronic systems are designed, manufactured, and marketed. Thus, it is important in this competitive environment to understand the nature, options, design styles, and costs of ASIC technology and of the related programmable logic IC families. ASIC chips are not generally just application specific, they are customer specific. It can be argued that customer programmable logic devices are the only true ASICs. To compound this problem, the term is used differently by different people in different contexts. ASIC is defined variously as gate array, any custom, semi-custom, or programmable technology, and as a design methodology [1]. An Application specific integrated circuit is a kind of integrated circuit that is specially built for a specific application or purpose, an ASIC can improve speed because it is specially designed to do one thing and it does this one thing well. It can also be made smaller and use less electricity. The disadvantage of this circuit is that it can be more expensive to design and manufacture, particularly if only a few units are needed.

An ASIC can be found in almost any electronic device and its uses can range from custom rendering of image to sound conversion. Because ASICs are all custom made and thus only available to the company that designed them, they are considered to be proprietary technology. In full custom design, custom logic cells are designed, starting at the lowest level (i.e., transistor-based cell design) and extending to higher levels (e.g., combinations of cells for higher level functions) to create the overall IC function. A full custom IC are the most expensive to manufacture and to design. The manufacturing lead time is typically eight week for a full custom IC. One of the exciting ASIC areas undergoing rapid development is the addition of analog integrated circuits to the standard digital VLSI ASIC, corresponding to mixed-signal VLSI. Mixed-signal ICs allow the IC to interact directly with the real physical world. Library cells representing various analog circuit functions supplement the usual digital circuit cells of the library, allowing the ASIC designer to add needed analog circuits within the same general framework as the addition of digital circuit cells. Automotive electronics is a representative example, with many sensors providing analog information which is converted into a digital format and analyzed using microcomputers or other digital circuits. Mixed-signal library cells include A/D and D/A converters, comparators,

MIT International Journal of Electronics and Communication Engineering, Vol. 4, No. 1, January 2014, pp. 1–6 ISSN 2230-76 72 © MIT Publications

analog switches; sample-and-hold circuits, etc., while analog library cells include op amps, precision voltage sources, and phase-locked loops. As such mixed-signal VLSI ASICs evolve, EDA/CAD tools will also evolve to address the performance and design issues related to analog circuits and their behaviour in a digital circuit environment. In addition, analog high-level description languages (AHDLs) are being developed to support high level specifications of mixed-signal circuits [2]. II. TYPES OF ASIC DESIGN ASIC describes a methodology (or group of methodologies) for designing electronic systems, and it describes a technology (or group of technologies) used to build electronic systems. Most of today’s flexible and cost effective electronic systems are designed using ASIC methodologies and built using ASIC technology. ICs are made on a thin (a few hundred microns thick), circular silicon wafer, with each wafer holding hundred of die. The transistor and wiring are made from many layers (usually between 10 and 15 distinct layers) built on top of one another. Each successive mask layer has a pattern that is defined using a mask similar to a glass photographic slide. The first half-dozen or so layers define the metal wires between the transistors. ASIC design can be classified as: Application Specific ICs

Full Custom

Semicustom

Standard Cell

Gate Array

Silicon

FPL

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Full-custom ASIC cannot be modified to suit different applications, and is generally produced as a single, specific product for a particular application only. The designer must manipulate the individual geometric shapes which represent the features of each transistor on the chip; hence the often applied term for full custom design: “polygon pushing”. A relatively simple 3000 gate design might require the handling of 300,000 rectangles per chip.1 although this design style was used exclusively in early ICs; engineers rarely use it for today’s ASICs due to the high engineering costs and low designer productivity. Productivity for full custom logic designs is typically only 6 to 17 transistors per day. The exception is in high volume commodity products such as memories which must be hand-crafted to meet density and performance requirements [4]. In addition, at least portions of high-end products such as microprocessors are full custom designed for performance reasons. Worldwide sales of full custom ASIC designs are predicted to grow only slightly from the current level of $2.7 Billion to $2.9 Billion in 1998 (a declining market share from 23% to 16%). (ii) Semi-custom Design Semi custom design is realised solely with standard integrated circuits may be inappropriate for an application due to cost, size, power consumption, complexity, maintainability, or speed. For example the gate array, a chip which contains several identical cells of uncommitted transistors and resistors. These may be connected in different ways to perform assorted logical function. This provides the benefits of integrating entire printed circuit board assemblies onto a single chip, while sharing the time and costs of mask and wafer development and circuit characterisation among several small to moderate volume users. Semicustom custom design circuit can be further divided in to:

(i) Full Custom Design

Standard Cell Design

In the classic full custom design style, each primitive logic function or transistor is manually designed and optimized. This results in the most compact chip design with the highest possible speed and lowest power dissipation. However, the initial investment or Non-Recurring Engineering (NRE) cost is highest compared to all other design styles.

In the standard cell design methodology, pre-defined logic and function blocks are made available to the designer in a cell library.

Fig. 2. Designing of gate array and standard cells

Fig. 1. Full custom layout circuit using CAD Tool

Typical libraries begin with gate level primitives such as AND, OR, NAND, NOR, XOR, Inverters, flip-flops, registers, and the like. Libraries generally include more complex functions such as adders, multiplexers, decoders, ALUs, shifters, and memory (RAM, ROM, FIFOs, etc.). In some cases, the standard cell

MIT International Journal of Electronics and Communication Engineering, Vol. 4, No. 1, January 2014, pp. 1–6 ISSN 2230-76 72 © MIT Publications

library may include complex functions such as multipliers, dividers, microcontrollers, microprocessors, and microprocessor support functions (parallel port, serial port, DMA controller, event timers, real-time clock, etc.). Standard cell designs are created using schematic capture tools or via synthesis from a Hardware Description Language (HDL). Automated tools are then used to place the cells on a chip image and wire them together. Standard cell layouts are easily identified by rows of equal height cells separated by wiring channels. Large macrocells such as multipliers or microcontrollers may span multiple cell rows and block some of the wiring channels [5]. Standard cell designs operate a lower clock rates and are generally less area efficient than a full custom design due to the fixed cell size constraints and requirements for dedicated wiring channels. It is basic building blocks have been custom designed and are available in a library of parts. Designer takes these blocks and connects them together to make a circuit with the required function. More expensive than GAs because each design will use a different configuration of standard cells requiring thus a full mask set.

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both time to market and financial risk can be substantially reduced. The Field Programmable Gate Array (FPGA), like the gate array, places fixed cells on the wafer and the FPGA designer constructs more complex functions from these cells. However, the cells provided on the FPGA can be substantially more complex than the simple gates provided on the gate array. In addition, the term field programmable” highlights the customizing of the ASIC by the user, rather than by the foundry manufacturing the FPGA. The mask-programmable gate array (MPGA) is similar to the FPGA (using more complex cells than the gate array) but the programming is performed by addition of the metal layer by the FPGA manufacturer [6]. FPGAs and PLDs are similar, except that the FPGA is usually larger and more complex than the PLD. In fact, some companies that manufacture programmable ASICs call their products FPGAs, while some call them complex PLDs (CPLDs).

Gate Arrays (GAs) A Gate Array is a standard LSI chip that consists of gates and the designer has to do the interconnections between them to customise the chip. Full custom and standard cell design methodologies require custom chip fabrication using a complete set of unique masks which define the semiconductor processing of the design. The gate array technology [3] is based on partially prefabricated (up to but not including the final metallization layer) wafers with simple gate cells. Such non-customized wafers are stockpiled and the ASIC designer specifies the final metallization layer added to customize the gate array.

Fig. 3. Cell of gate array and sea-of-gate

Fig. 4. Programmable ICs

The Two major classes of field programmable logic, Programmable Logic Devices (PLDs) and Field Programmable Gate Arrays (FPGAs), have emerged as cost effective ASIC solutions because they provide low-cost prototypes with nearly instant “manufacturing”. This class of device consists of an array of uncommitted logic elements whose interconnect structure and/ or logic structure can be personalized on-site according to the user’s specification. Although field programmable logic represents only a small percentage of total ASIC market sales, statistics indicate that approximately one half of all chip design projects today are begun using FPGAs.

* GAs is available in ECL, CMOS and bipolar technologies.

(iii) Silicon Compilation

* GAs is available in a variety of gate counts from a few hundred up to 40000.

Silicon compilation takes place in three major steps: •

It Convert a hardware-description language such as Verilog or VHDL or FPGA into logic (typically in the form of a “net list”).

•

Place equivalent logic gates on the IC. Silicon compilers typically use standard-cell libraries so that they do not have to worry about the actual integrated-circuit layout and can focus on the placement.

•

Routing the standard cells together to form the desired logic.

* Designer needs to know nothing about the transistor and circuit level. Field Programmable Logic A field programmable logic device is a chip whose final logic structure is directly configured by the end user. By eliminating the need to cycle through an integrated circuit production facility,

MIT International Journal of Electronics and Communication Engineering, Vol. 4, No. 1, January 2014, pp. 1–6 ISSN 2230-76 72 © MIT Publications

III. ASIC DESIGN FLOW ASIC Design is based on a flow that uses HDL as the entry level for design, which applies for both Verilog and VHDL [8]. The following description describes the flow from specification of design up to tapeout, which is the form sent to silicon foundry for fabrication.

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be a possibility of the loop in this process, until the RTL code correctly describes the required logical behaviour of the design. (d) Synthesis: This process is conducted on the RTL code. This is the process whereby the RTL code is converted into logic gates. The logic gate produced is the functional equivalent of the RTL code as intended in the design. The synthesis process however requires two input files: firstly, the “standard cell technology files” and secondly the “constraints file”. A synthesised database of the design is created in the system. (e) Pre-Layout Timing Analysis: When synthesis is completed, the synthesized database along with timing information from the synthesis process is used to perform a Static Timing Analysis (STA). Tweaking (making small changes) has to be done to correct any timing issues. (f) APR: This is the Automatic Place and Route process whereby the layout is being produced. In this process, the synthesized database together with timing information from synthesis is used to place the logic gates. Most designs have critical paths whose timings required them to be routed first. The process of placement and routing normally has some degree of flexibility.

Fig, 5. Block Diagram of ASIC Design Flow

The steps are listed below with brief description: (a) Specification: This is the beginning and most important step towards designing a chip as the features and functionalities of the chip are defined. Both design at macro and micro level are taken into consideration which is derived from the required features and functionalities. Speed, size, power consumption are among the considerations on which the accepted range of values is specified. Other performance criteria are also set at this point and deliberated on its viability; some form of simulation might be possible to check on this. (b) RTL Coding: The micro architecture at specification level is then transformed in RTL code which marks the beginning of the real design phase towards realising a chip. As a real chip is expected, so the code has to be a synthesizable RTL code. (c) Simulation and Test bench: RTL code and test bench are simulated using HDL simulators to check on the functionality of the design. If Verilog is the language used a Verilog simulator is required while VHDL simulator for a VHDL code. Some of the tools available at CEDEC include: Cadence’s Verilog XL, Synopsys’s VCS, and Mentor Graphic’s Modelsim. If the simulation results do not agree with the intended function expected, the test bench file or the RTL code could be the cause. The process of debugging the design has to be done if the RTL code is the source of error. The simulation has to be repeated once either one of the two causes, or both, have been corrected. There could

(g) Back Annotation: This is the process where extractions for RC parasitic are made from the layout. The path delay is calculated from these RC parasitic. Long routing lines can significantly increase the interconnect delay for a path and for sub-micron design parasitic cause significant increase in delay. Back annotation is the step that bridges synthesis and physical layout. (h) Post-Layout: Timing Analysis: This step in ASIC flow allows real timing violations such as hold and setup to be detected. In this step, the net interconnect delay information is fed into the timing analysis and any setup violation should be fixed by optimizing the paths that fail while hold violation is fixed by introducing buffers to the path to increase the delay. The process between APR, back annotation and post-layout timing analysis go back and forth until the design is cleared of any violation. Then it will be ready for logic verification. (i) Logic Verification: This step acts as the final check to ensure the design is correct functionally after additional timing information from layout. Changes have to be made on the RTL code or the post-layout synthesis to correct the logic verification. (j) Tapeout: When the design passed the logic verification check, it is now ready for fabrication. The tapeout design is in the form of GDSII file, which will be accepted by the foundry. IV. FULL ADDER SCHEMATIC AND SIMULATION OF CIRCUIT The Full-adder is one of the most used basic circuits since addition of binary numbers are one of the most used operations in

MIT International Journal of Electronics and Communication Engineering, Vol. 4, No. 1, January 2014, pp. 1–6 ISSN 2230-76 72 © MIT Publications

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digital electronics. Full-adders exist everywhere in electronic systems and a large amount of research has been done in this area in order to achieve best possible performance. The ultimate goal of a binary full-adder (BFA) is to implement the following truth table for each bit: Table 1. Truth Table for 1bit adder Slice Cin 0 0 0 0 1 1 1 1

Logically

A 0 0 1 1 0 0 1 1

B 0 1 0 1 0 1 0 1

Sum 0 1 1 0 1 0 0 1

Cout 0 0 0 1 0 1 1 1

Ck+1 = AkBk + Ck( Ak + Bk)

(1)

Sum = Ak  Bk Ck

(2)

Where k is an integer 0 to n for an n-bit adder. Generally, adders of n-bits are created by chaining together n of these 1-bit adder slices. There are three major components of power dissipation in CMOS Circuits [5]. (a) Switching power: power consumed by circuit node capacitance during transistor switching. (b) Short-circuit power: power consumed due to current flowing from Vdd to Gnd when both transistors are ON. (c) Static power: Due to Leakage and static currents. The simulations have been performed in Cadence with the Spectre simulator in a 120 nm CMOS process technology and the used transistors are of low-leakage type. The transistors using minimum gate lengths, 120 nm (effective), and a width of 150 nm for NMOS and a width of 380 nm for the PMOS. The threshold voltage, Vth, for these low-leakage transistors are 383 mV for NMOS and -368 mV for PMOS according to the simulations [9].

Fig. 7. EDP for Floating-gate and CMOS full-adders at 150 mV.

The plots show the limit of how large the floating-gate voltage can be while the circuit’s gain is higher than one. If the floating-gate voltage, VFGp, is set more negative than in these plots, there will be an attenuation of the signal for each gate. Figure 7 shows the PDP (at 150 mV) which is almost constant for all applied different floating-gate voltages and is approximately 4 times worse than PDP for each of the CMOS full-adders [10]. IV. CONCLUSION A full custom IC includes some logic cells that are customised using microprocessor full custom IC. VLSI is an IC manufacturing technology, and VHDL and Verilog are the hardware description languages (programming languages) used to describe digital circuits. This Full adder has better noise immunity as compared to the standard adder such as static CMOS, making it suitable for deep-sub micrometer operation. We recommend the use of hybrid-CMOS design style for the design of high-performance circuits. The characteristics of the proposed full adders are compared against previous designed full adders based on the worst case delay time, power consumption and power delay product. REFERENCES [1] M.J.S. Smith, Application-Specific Integrated Circuits. Reading, MA: Addison-Wesley, 1997. [2] W.J. Dally and A. Chang, “The role of custom design in ASIC chips,” in Proc. 37th Des. Auto. Conf., 2000, pp. 643–647. [3] Baker, R. Jacob (2005). CMOS Circuit Design, Layout and Simulation (Second Edition). p. 368.

Fig 6. Schematic of floating gate Full Adder Circuit

[4] T. Shibata and T. Ohmni, “A Functional MOS Transistor Featuring Gate-Level Weighted Sum and Threshold Operations,” IEEE Transactions on Electron Devices 39, 1992.

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