Design Example: Level-to-Pulse •
A level-to-pulse converter produces a singlecycle pulse each time its input goes high.
•
It’s a synchronous rising-edge detector.
•
Sample uses: – Buttons and switches pressed by humans for arbitrary periods of time – Single-cycle enable signals for counters
Level to L P Pulse Converter Whenever input L goes from low to high...
6.111 Fall 2007
CLK
...output P produces a single pulse, one clock period wide.
Lecture 7, Slide 1
Step 1: State Transition Diagram •
Block diagram of desired system:
unsynchronized user input
Synchronizer
Edge Detector
D Q
L
D Q
Level to Pulse FSM
P
CLK
• State transition diagram is a useful FSM representation and design aid: “if L=1 at the clock edge, then jump to state 01.”
L=0
00
“if L=0 at the clock edge, then stay in state 00.”
L=1
High input, Waiting for fall
Edge Detected!
P=1 L=0
Binary values of states
11
01
Low input, Waiting for rise
P=0
6.111 Fall 2007
L=1
L=1
P=0 L=0
This is the output that results from this state. (Moore or Mealy?)
Lecture 7, Slide 2
Step 2: Logic Derivation Curren In t State
Transition diagram is readily converted to a state transition table (just a truth table) L=1
L=1 L=0
00 P=0
Edge Detected!
P=1 L=0
S0
L
0 0 0 0 1 1
0 0 1 1 1 1
0 1 0 1 0 1
L=1
11
01
Low input, Waiting for rise
S1
High input, Waiting for fall
P=0 L=0
Next State
Out
S1+ S0+
P
0 0 0 1 0 1
0 1 0 1 0 1
0 0 1 1 0 0
• Combinational logic may be derived using Karnaugh maps +
S1S0 for S1 : 00 01 11 10 L
0 0 0 0 X 1 0 1 1 X +:
S1S0 for S0 00 01 11 10 L
0 0 0 0 X 1 1 1 1 X
6.111 Fall 2007
L
S+ Comb. Logic
S1+ = LS0 S0 + = L
n CLK
D Flip- Q
Comb. Logic
Flops n
S
P = S1S0
P S0
S1
for P:
0 1 0 0 X 1 1 0
Lecture 7, Slide 3
Moore Level-to-Pulse Converter inputs x0...xn
next state S+ Comb. Logic
D
n
Flip- Q Flops
Comb. Logic
CLK
S1 = LS0 S0 + = L +
outputs yk = fk(S)
n
present state S P = S1S0
Moore FSM circuit implementation of level-to-pulse converter: L
S0 +
D
CLK
S1 +
6.111 Fall 2007
Q
S0
P
Q D
Q Q
S1
Lecture 7, Slide 4
Design of a Mealy Level-to-Pulse direct combinational path!
S+ Comb. Logic
n
Comb. Logic
D Flip- Q
Flops
CLK
n
S
•
Since outputs are determined by state and inputs, Mealy FSMs may need fewer states than Moore FSM implementations 1. When L=1 and S=0, this output is asserted immediately and until the state transition occurs (or L changes).
L P
L=1 | P=1 L=0 | P=0
1
2
Clock
0
1
Input is low
Input is high L=0 | P=0 L=1 | P=0
State Output transitions immediately. State transitions at the clock edge.
2. While in state S=1 and as long as L remains at 1, this output is asserted. 6.111 Fall 2007
Lecture 7, Slide 5
Mealy Level-to-Pulse Converter L=1 | P=1
0
1
Input is low
Input is high L=0 | P=0
L=0 | P=0
L=1 | P=0
Pres. State
In
S 0 0 1 1
L 0 1 0 1
Next Out State S+ 0 1 0 1
P 0 1 0 0
Mealy FSM circuit implementation of level-to-pulse converter: P L
S+ CLK
D
Q
S
Q
S
• FSM’s state simply remembers the previous value of L • Circuit benefits from the Mealy FSM’s implicit singlecycle assertion of outputs during state transitions 6.111 Fall 2007
Lecture 7, Slide 6
Moore/Mealy Trade-Offs •
How are they different?
– Moore: outputs = f( state ) only – Mealy outputs = f( state and input ) – Mealy outputs generally occur one cycle earlier than a Moore:
Moore: delayed assertion of P
Mealy: immediate assertion of P
L
L
P
P
Clock
Clock
State[0]
State
• Compared to a Moore FSM, a Mealy FSM might... – Be more difficult to conceptualize and design – Have fewer states 6.111 Fall 2007
Lecture 7, Slide 7
Light Switch Revisited
0 1
BUTTON
D Q
LIGHT
D Q Q
CLK Level-to-Pulse FSM
6.111 Fall 2007
Light Switch FSM
Lecture 7, Slide 8
FSM Example GOAL: Build an electronic combination lock with a reset button, two number buttons (0 and 1), and an unlock output. The combination should be 01011. RESET “0” “1”
UNLOCK
STEPS: 1.Design lock FSM (block diagram, state transitions) 2.Write Verilog module(s) for FSM
6.111 Fall 2007
Lecture 7, Slide 9
Step 1A: Block Diagram lock Clock generator
fsm unlock
Button Enter
reset button
reset
Button 0
b0_in button
b0
Button 1
6.111 Fall 2007
fsm_clock
b1_in
state button
Unlock LED
LED DISPLAY
b1
Lecture 7, Slide 10
Step 1B: State transition diagram RESET 1
0
1 0
RESET Unlock = 0
“0” Unlock = 0
1
“01” Unlock = 0 0
1
0
0 “01011” Unlock = 1
1
“0101” Unlock = 0
1
“010” Unlock = 0
0 6 states → 3 bits 6.111 Fall 2007
Lecture 7, Slide 11
Step 2: Write Verilog module lock(clk,reset_in,b0_in,b1_in,out); input clk,reset,b0_in,b1_in; output out; // synchronize push buttons, convert to pulses // implement state transition diagram reg [2:0] state,next_state; always @ (*) begin // combinational logic! next_state = ???; end always @ (posedge clk) state
