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EE6301 – DIGITAL LOGIC CIRCUITS UNIT I – BOOLEAN ALGEBRA AND COMINATIONAL CIRCUITS PART A 1. How can an OR gate be realized using NAND gates?

(M-13)

2. Define – Multiplexer (M-13) A multiplexer is a digital switch which allows digital information from several sources to be routed into a single output line. The basic multiplexer has several data input lines and a single data output line. The selection of a particular input line is controlled by a set of selection lines. Normally there are 2n input lines and n selection lines.

3. What is meant by priority encoder? (M-12) A priority encoder is an encoder that includes the priority function. The operation of the priority encoder is such that if two or more inputs are equal to 1 at the same time, the input having the highest priority will take precedence. D0 0 1 X X X

Inputs D1 D2 0 0 0 0 1 0 X 1 X X

D3 0 0 0 0 1

Y0 X 0 0 1 1

Outputs Y1 X 0 1 0 1

V 1 0 0 0 0

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4. Distinguish between decoder and demultiplexer.

(N-11)

5. State De-Morgan’s theorem. (A-11) De - Morgan suggested two theorems that form an important part of Boolean algebra. They are, 1) The complement of a product is equal to the sum of the complements. തതതതതത ഥ +‫ܤ‬ ഥ ‫ܣ‬Ǥ ‫ܣ =ܤ‬ 2) The complement of a sum term is equal to the product of the complements. തതതതതതതത ഥ Ǥ ‫ܤ‬ ഥ= ‫ܣ‬ ‫ܣ‬ ൅ ‫ܤ‬ 6. Draw the truth table and logic circuit of half adder. Inputs A 0 0 1 1

B 0 1 0 1

Outputs Sum (S) 0 1 1 0

Carry (C) 0 0 0 1

(A-10)

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7. What is meant by decoder? (M-09) A decoder is a combinational circuit that decodes the binary information on ‘n’ input lines to a maximum of 2n unique output lines. The general structure of decoder circuit is

8. What is meant by encoder? (M-10) An encoder is a combinational circuit that converts binary information from 2n input lines to a maximum of ‘n’ unique output lines. The general structure of encoder circuit is

9. List out the applications of multiplexers. 1. Data routing 2. Logic function generator 3. Control sequencer 4. Parallel-to-serial converter.

(M-09)

10. What is meant by demultiplexer? (M-08) n A demultiplexer is a combinational logic circuit with an input line, 2 output lines and n select lines. It routes the information present on the input line to any of

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the output lines. The output line that gets the information present on the input line is decided by the bit status of the selection lines.

UNIT II –SYNCHRONOUS SEQUENTIAL CIRCUITS PART A 1. Define – Flip Flop (M-13) Flip flop is defined as the basic unit for storage. A flip-flop maintains its output state either at 1 or 0 until directed by an input signal to change its state. 2. What is meant by race around condition? (N-12) In JK flip-flop output is fed back to the input. Therefore change in the output results leads to change in the input. Due to this, in the positive half of the clock pulse if both J and K are high then output toggles continuously. This condition is called race around condition’. 3. Compare combinational circuits with sequential circuits. S. No. Combinational circuits Sequential circuits 1. Memory unit is not required Memory unity is required 2. Parallel adder is a combinational circuit Serial adder is a sequential circuit 4. What are the various classifications of sequential circuits? (N-11) The sequential circuits are classified on the basis of timing of their signals into two types. They are as follows: 1) Synchronous sequential circuit 2) Asynchronous sequential circuit

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5. What is the operation of D flip-flop? (M-11) In D flip-flop during the occurrence of clock pulse if D=1, the output Q is set and if D=0, the output is reset. 6. What is meant by master-slave flip-flop? (M-10) A master-slave flip-flop consists of two flip-flops where one circuit serves as a master and the other as a slave.

7. Write the excitation tables for a JK flip-flop. (N-09) In JK flip-flop there are four possible transitions from the present state to the next state. They are as follows:, _ 0_0 transition: This can happen when J=0 and K=1 or K=0. _ 0_1 transition: This can happen either when J=1 and K=0 or when J=K=1. _ 1_0 transition: This can happen either when J=0 and K=1 or when J=K=1. _ 1_1 transition: This can happen when K=0 and J=0 or J=1. 8. Compare synchronous counters with asynchronous counters.

(M-10)

9. What is meant by edge-triggered flip-flop? (M-09) The problem of race around condition can be solved by edge triggering flip flop. The term edge triggering means that the flip-flop changes state either at the positive edge or negative edge of the clock pulse and it is sensitive to its inputs only at this transition of the clock.

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10. What are the different types of flip-flop? There are various types of flip flops. They are as follows: 1) RS flip-flop 2) SR flip-flop 3) D flip-flop 4) JK flip-flop 5) T flip-flop UNIT III – ASYNCHRONOUS SEQUENCITIAL CIRCUIT 1. What is meant by race condition in an asynchronous sequential circuit? A race condition is said to exist in an asynchronous sequential circuit when two or more binary state variables changed value in response to a change in an input variable. The order by which the state variables change may not be known in advance if the final stable state that the circuit reaches does not depend on the order in which the state variable changes. The race is called a non-critical race. 2. What are called hazards? Hazards are unwanted switching transients that may appear at the output of a circuit because different paths exhibit different propagation delays. The 3 types of hazards are 1. Static hazards Static – 0 hazards Static – 1 hazard 2. Dynamic hazards 3. Essential hazards 3. What are the assumptions made for fundamental mode circuit? The assumptions made for fundamental mode circuit are 1. The input variables change only when the circuit is stable 2. Only one input variable can change at a given time 3. Inputs are levels and not pulses

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4. Define – Flow Table in an asynchronous sequential circuit During the design of asynchronous sequential circuits, it is more convenient to name the states by letter symbols without making specific reference to their binary values. Such a table is called a flow table. 5. What are the steps to be followed in the designing of a asynchronous sequential circuit? The steps to be followed in the design of asynchronous sequential circuit are 1. Construction of a primitive flow table from the problem statement 2. Primitive flow table is reduced by eliminating redundant states using the state reduction 3. State assignment is made 4. The primitive flow table is realized using appropriate logic elements 6. Define – Static 0-Hazard, Static 1-Hazard and Dynamic Hazard (A-09) Static-1 hazard: In a combinational circuit, if output goes momentarily 0 when it should remain a1, the hazard is known as static-1 hazard. Static-0 hazard: In a combinational circuit, If the output goes momentarily 1 when it should remain a 0, the hazard is known as static-0 hazard. Dynamic hazard: When the output changes three or more times when it should change from 1 to 0 or from 0 to 1, it is known as dynamic hazard.

7. What is meant by critical race? Why should it be avoided? Race exists in synchronous sequential circuits when two or more binary state variables charge during a state transition. A race becomes critical if the correct next value is not reached during a state transition. For the proper operation of the circuits, the critical races must be avoided. 8. What is meant by cycle? A cycle occurs when an asynchronous circuit makes a transition through a series of unstable states. If a cycle does not contain a stable state, the circuit will go from one unstable to stable, until the inputs are changed.

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9. How does an essential hazard occur? (A-12) An essential hazard occurs due to unequal delays along two or more paths that originate from the same input. An excessive delay through an inverter circuit in comparison to the delay associated with the feedback path causes essential hazard. 10. What are the significances of state assignment? In synchronous circuits-state assignments are made with the objective of circuit reduction. In asynchronous circuits its objective is to avoid critical races. UNIT IV PROGRAMMABLE LOGIC DEVICES, MEMORY AND LOGIC FAMILIES 1. Explain ROM. (N/D-12) A read only memory (ROM) is a device that includes both the decoder and the OR gates within a single IC package. It consists of n input lines and m output lines. Each bit combination of the input variables is called an address. Each bit combination that comes out of the output lines is called a word. The number of distinct addresses possible with n input variables is 2n. 2. What are the various types of ROM? 1. Masked ROM 2. Programmable Read only Memory 3. Erasable Programmable Read only memory 4. Electrically Erasable Programmable Read only Memory

(M/J-11)

3. What is meant by programmable logic array? How does it differ from ROM? In some cases the number of don’t care conditions is excessive. It is more economical to use a second type of LSI component called a PLA. A PLA is similar to a ROM in concept. However it does not provide full decoding of the variables and does not generate all the min-terms as in the ROM. 4. What is meant by CPLD? CPLDs are Complex Programmable Logic Devices. They are larger versions of PLDs with a centralized internal interconnect matrix used to connect the device macro cells together.

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5. Define – Cache Memory (M/J-13) It is a relatively small, high-speed memory that can store the most recently used instructions or data from larger but slower main memory. 6. Compare PROM with PLA. PROM 1. AND array is fixed and OR array is programmable. 2. Cheaper and simple to use.

PLA Both AND and OR arrays are programmable. Costliest and more complex than PROMS

7. List out the classifications of a saturated bipolar logic families. The bipolar logic family is classified as follows: 1. RTL- Resistor Transistor Logic 2. DTL- Diode Transistor logic 3. I2L- Integrated Injection Logic 4. TTL- Transistor Transistor Logic 5. ECL- Emitter Coupled Logic 8. Define – Fan-out Fan out specifies the number of standard loads that the output of the gate can drive With out impairment of its normal operation. 9. Define – Noise Margin It is the maximum noise voltage added to an input signal of a digital circuit that does not cause an undesirable change in the circuit output. It is expressed in volts. . 10. How are Schottky transistors formed? A schottky diode is formed by the combination of metal and semiconductor. The presence of schottky diode between the base and the collector prevents the transistor from going into saturation. The resulting transistor is called schottky transistor. The use of Schottky transistor in TTL decreases the propagation delay without a sacrifice of power dissipation

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UNIT V –VHDL PART A 1. What is meant by Verilog? (N/D-12) Verilog is a general purpose hardware descriptor language. It is similar in syntax to the C programming language. It can be used to model a digital system at many levels of abstraction ranging from the algorithmic level to the switch level. 2. What is meant by switch-level modeling? (M/J-10) Verilog allows switch-level modeling that is based on the behavior of MOSFETs. Digital circuits at the MOS-transistor level are described using the MOSFET switches. 3. What are called value sets in verilog? (N/D-11) Verilog supports four levels for the values needed to describe hardware referred to as value sets. Value levels Condition in hardware circuits 0- Logic zero, false condition 1 -Logic one, true condition X -Unknown logic value Z -High impedance, floating state 4. List out the various classifications of timing control. The various classifications of timing control are as follows: 1. Delay-based timing control 2. Event-based timing control 3. Level-sensitive timing control Types of delay-based timing control: 1. Regular delay control 2. Intra-assignment delay control 3. Zero delay control Types of event-based timing control: 1. Regular event control 2. Named event control 3. Event OR control 4. Level-sensitive timing control

(M/J-11)

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5. What are the various types of conditional statements? (M/J-12) The types of conditional statements are as follows: 1. No else statement Syntax: if ([expression]) true – statement; 2. One else statement Syntax: if ([expression]) true – statement; else false-statement; 3. Nested if-else-if Syntax : if ( [expression1] ) true statement 1; else if ( [expression2] ) true-statement 2; else if ( [expression3] ) true-statement 3; else default-statement; The [expression] is evaluated. If it is true (1 or a non-zero value) truestatement is executed. If it is false (zero) or ambiguous (x), the false-statement is executed. 6. What are the various types of ports in verilog? The various types of ports in verilog are as follows: Types of port Keyword Input port Input Output port Output Bidirectional port In out

(N/D-13)

7. What are the various modeling used in verilog? The various modeling used in verilog are as follows: 1. Gate-level modeling 2. Data-flow modeling 3. Switch-level modeling 4. Behavioral modeling

(M/J-09)

8. What is meant by structural gate-level modeling? (M/J-11) Structural modeling describes a digital logic network in terms of the components that make up the system. Gate-level modeling is based on using primitive logic gates and specifying how they are wired together.

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9. What are called gate primitives? (N/D-12) Verilog supports basic logic gates as predefined primitives. Primitive logic function keyword provides the basics for structural modeling at gate level. These primitives are instantiated like modules except that they are predefined in verilog and do not need a module definition. The important operations are and, nand, or, xor, xnor, and buf (non-inverting drive buffer). 10. What are the various types of procedural assignments? The various types of procedural assignments are as follows: 1. Blocking assignment 2. Non-blocking assignment

(M/J-13)