CPU Control

Lecture 16 CDA 3103 07-14-2014

Review • CPU design involves Datapath, Control – 5 Stages for MIPS Instructions 1. 2. 3. 4. 5.

Instruction Fetch Instruction Decode & Register Read ALU (Execute) Memory Register Write

• Datapath timing: single long clock cycle or one short clock cycle per stage Dr Dan Garcia

Datapath and Control

+4

ALU

Data memory

rd rs rt

registers

PC

instruction memory

• Datapath based on data transfers required to perform instructions • Controller causes the right transfers to happen

imm opcode, funct

Controller Dr Dan Garcia

Copyright © 2014 Elsevier Inc. All rights reserved.

4

Review CPU Clocking (1/2) • For each instruction, how do we control the flow of information though the datapath? • Single Cycle CPU: All stages of an instruction completed within one long clock cycle – Clock cycle sufficiently long to allow each instruction to complete all stages without interruption within one cycle 1. Instruction Fetch

2. Decode/ Register Read

3. Execute 4. Memory

5. Reg. Write

Dr Dan Garcia

Review CPU Clocking (2/2) • Alternative multiple-cycle CPU: only one stage of instruction per clock cycle – Clock is made as long as the slowest stage 1. Instruction 2. Decode/ Fetch Register Read

3. Execute

4. Memory

5. Register Write

– Several significant advantages over single cycle execution: Unused stages in a particular instruction can be skipped OR instructions can be pipelined (overlapped) Dr Dan Garcia

Agenda • Stages of the Datapath • Datapath Instruction Walkthroughs • Datapath Design

Dr Dan Garcia

Five Components of a Computer Computer Processor

Control

Datapath

Memory (passive) (where programs, data live when running)

Devices Input Output

Keyboard, Mouse Disk (where programs, data live when not running)

Display, Printer Dr Dan Garcia

Processor Design: 5 steps Step 1: Analyze instruction set to determine datapath requirements

– Meaning of each instruction is given by register transfers – Datapath must include storage element for ISA registers – Datapath must support each register transfer

Step 2: Select set of datapath components & establish clock methodology Step 3: Assemble datapath components that meet the requirements Step 4: Analyze implementation of each instruction to determine setting of control points that realizes the register transfer Step 5: Assemble the control logic Dr Dan Garcia

Processor Design: Step 1 Step 1: Analyze instruction set to determine datapath requirements

– Meaning of each instruction is given by register transfers – Datapath must include storage element for ISA registers – Datapath must support each register transfer

Step 2: Select set of datapath components & establish clock methodology Step 3: Assemble datapath components that meet the requirements Step 4: Analyze implementation of each instruction to determine setting of control points that realizes the register transfer Step 5: Assemble the control logic Dr Dan Garcia

The MIPS Instruction Formats • All MIPS instructions are 32 bits long. 3 formats: – R-type

31

26 op

rs

6 bits 31

– I-type

26

op 31

16 rt

5 bits

5 bits 21

rs

6 bits

– J-type

21

5 bits

11

6

rd

shamt

funct

5 bits

5 bits

6 bits

16

0 address/immediate

rt 5 bits

16 bits

26 op

6 bits

0

0 target address

26 bits

• The different fields are: – – – – – –

op: operation (“opcode”) of the instruction rs, rt, rd: the source and destination register specifiers shamt: shift amount funct: selects the variant of the operation in the “op” field address / immediate: address offset or immediate value target address: target address of jump instruction Dr Dan Garcia

The Main Control Unit 

Control signals derived from instruction

R-type

Load/ Store

Branch

0

rs

rt

rd

shamt

funct

31:26

25:21

20:16

15:11

10:6

5:0

35 or 43

rs

rt

address

31:26

25:21

20:16

15:0

4

rs

rt

address

31:26

25:21

20:16

15:0

opcode

always read

read, except for load

write for R-type and load

sign-extend and add

Chapter 4 — The Processor — 12

Datapath With Control

Chapter 4 — The Processor — 13

The MIPS-lite Subset • ADDU and SUBU

31 op

– addu rd,rs,rt – subu rd,rs,rt

• OR Immediate:

26 rs

6 bits 31 op

31

– lw rt,rs,imm16 – sw rt,rs,imm16

• BRANCH:

31

26 op

– beq rs,rt,imm16 6 bits

5 bits

rd

shamt

funct

5 bits

5 bits

6 bits 0

16 bits 0

immediate

5 bits

21 rs

0

16

rt

5 bits

6

immediate

5 bits

21

rs

11

16 rt

5 bits

26 6 bits

5 bits

21 rs

op

16 rt

5 bits

26

– ori rt,rs,imm16 6 bits

• LOAD and STORE Word

21

16 bits

16 rt 5 bits

0 immediate 16 bits Dr Dan Garcia

Register Transfer Language (RTL) RTL gives the meaning of the instructions All start by fetching the instruction {op , rs , rt , rd , shamt , funct}  MEM[ PC ] {op , rs , rt ,

Imm16}  MEM[ PC ]

Inst

Register Transfers

ADDU

R[rd]  R[rs] + R[rt]; PC  PC + 4

SUBU

R[rd]  R[rs] – R[rt]; PC  PC + 4

ORI

R[rt]  R[rs] | zero_ext(Imm16); PC  PC + 4

LOAD

R[rt]  MEM[ R[rs] + sign_ext(Imm16)]; PC  PC + 4

STORE

MEM[ R[rs] + sign_ext(Imm16) ]  R[rt]; PC  PC + 4

BEQ

if ( R[rs] == R[rt] ) then PC  PC + 4 + (sign_ext(Imm16) || 00) else PC  PC + 4 Dr Dan Garcia

Step 1: Requirements of the Instruction Set • Memory (MEM) – Instructions & data (will use one for each)

• Registers (R: 32 x 32) – Read RS – Read RT – Write RT or RD

• PC • Extender (sign/zero extend) • Add/Sub/OR unit for operation on register(s) or extended immediate • Add 4 (+ maybe extended immediate) to PC • Compare registers? Dr Dan Garcia

Processor Design: Step 2 Step 1: Analyze instruction set to determine datapath requirements

– Meaning of each instruction is given by register transfers – Datapath must include storage element for ISA registers – Datapath must support each register transfer

Step 2: Select set of datapath components & establish clock methodology Step 3: Assemble datapath components that meet the requirements Step 4: Analyze implementation of each instruction to determine setting of control points that realizes the register transfer Step 5: Assemble the control logic Dr Dan Garcia

Step 2: Components of the Datapath • Combinational Elements • Storage Elements + Clocking Methodology • Building Blocks OP CarryIn A

A CarryOut

32

Adder

B

32

32

Y

B

32

Multiplexer

32

ALU

32

Sum

A

MUX

Adder

B

32

Select

32

Result

32

ALU

Dr Dan Garcia

ALU Needs for MIPS-lite + Rest of MIPS • Addition, subtraction, logical OR, ==: ADDU SUBU ORI

R[rd] = R[rs] + R[rt]; ... R[rd] = R[rs] – R[rt]; ... R[rt] = R[rs] | zero_ext(Imm16)...

BEQ

if ( R[rs] == R[rt] )...

• Test to see if output == 0 for any ALU operation gives == test. How? • P&H also adds AND, Set Less Than (1 if A < B, 0 otherwise) • ALU follows Chapter 5 Dr Dan Garcia

Storage Element: Idealized Memory Write Enable

Address

• Memory (idealized) – One input bus: Data In – One output bus: Data Out

• Memory word is found by:

Data In 32 Clk

DataOut 32

– Address selects the word to put on Data Out – Write Enable = 1: address selects the memory word to be written via the Data In bus

• Clock input (CLK) – CLK input is a factor ONLY during write operation – During read operation, behaves as a combinational logic block: Address valid  Data Out valid after “access time” Dr Dan Garcia

Storage Element: Register (Building Block) Write Enable

• Similar to D Flip Flop except – N-bit input and output – Write Enable input

• Write Enable:

Data In

Data Out

N

N clk

– Negated (or deasserted) (0): Data Out will not change – Asserted (1): Data Out will become Data In on positive edge of clock

Dr Dan Garcia

Storage Element: Register File RW RA RB Write Enable 5 5 5

• Register File consists of 32 registers: – Two 32-bit output busses: busA and busB – One 32-bit input bus: busW

• Register is selected by:

busW 32 Clk

32 x 32-bit Registers

busA 32 busB 32

– RA (number) selects the register to put on busA (data) – RB (number) selects the register to put on busB (data) – RW (number) selects the register to be written via busW (data) when Write Enable is 1

• Clock input (clk) – Clk input is a factor ONLY during write operation – During read operation, behaves as a combinational logic block: • RA or RB valid  busA or busB valid after “access time.”

Dr Dan Garcia

Clocking Methodology Clk . . .

. . .

. . .

. . .

• Storage elements clocked by same edge • Flip-flops (FFs) and combinational logic have some delays – Gates: delay from input change to output change – Signals at FF D input must be stable before active clock edge to allow signal to travel within the FF (set-up time), and we have the usual clock-to-Q delay

• “Critical path” (longest path through logic) determines length of clock period Dr Dan Garcia

Register-Register Timing: One Complete Cycle (Add/Sub) Clk PC Old Value Rs, Rt, Rd, Op, Func

Old Value

ALUctr

Old Value

RegWr

Old Value

busA, B

Old Value

busW

Old Value

New Value Instruction Memory Access Time New Value Delay through Control Logic New Value New Value Register File Access Time New Value ALU Delay New Value

ALUctr

RegWr Rd Rs Rt 5

Rw

busW

5

Ra Rb

busA

32

ALU

RegFile clk

5

busB

32

Register Write Occurs Here

32 Dr Dan Garcia

Register-Register Timing: One Complete Cycle Clk PC Old Value Rs, Rt, Rd, Op, Func

Old Value

ALUctr

Old Value

RegWr

Old Value

busA, B

Old Value

busW

Old Value

New Value Instruction Memory Access Time New Value Delay through Control Logic New Value New Value Register File Access Time New Value ALU Delay New Value

ALUctr

RegWr Rd Rs Rt 5

Rw

busW

5

Ra Rb

busA

32

ALU

RegFile clk

5

busB

32

Register Write Occurs Here

32 Dr Dan Garcia

Register-Register Timing: One Complete Cycle Clk PC Old Value Rs, Rt, Rd, Op, Func

Old Value

ALUctr

Old Value

RegWr

Old Value

busA, B

Old Value

busW

Old Value

New Value Instruction Memory Access Time New Value Delay through Control Logic New Value New Value Register File Access Time New Value ALU Delay New Value

ALUctr

RegWr Rd Rs Rt 5

Rw

busW

5

Ra Rb

busA

32

ALU

RegFile clk

5

busB

32

Register Write Occurs Here

32 Dr Dan Garcia

Processor Design: Step 3 Step 1: Analyze instruction set to determine datapath requirements

– Meaning of each instruction is given by register transfers – Datapath must include storage element for ISA registers – Datapath must support each register transfer

Step 2: Select set of datapath components & establish clock methodology Step 3: Assemble datapath components that meet the requirements Step 4: Analyze implementation of each instruction to determine setting of control points that realizes the register transfer Step 5: Assemble the control logic Dr Dan Garcia

Putting it All Together:A Single Cycle Datapath

RegDst

32

Equal

0 5

5

5

Rw Ra Rb

busA

RegFile

busB 32

16

Extender

imm16

MemtoReg MemWr

Rs Rt

clk clk

ALUctr

32

= ALU

busW

PC

PC Ext

Adder

Mux

00

RegWr Adder

4

Rt Rd Imm16

Rd Rt 1

Instruction



nPC_sel

Rs



Adr





Inst Memory

0 32 1

32

Data In clk

32 0 WrEn Adr

Data Memory

1

imm16 ExtOp

ALUSrc

Dr Dan Garcia

Peer Instruction • Our ALU is synchronous device? • We should use the main ALU to calculate PC = PC + 4? • The ALU is inactive for memory reads or writes ? Dr Dan Garcia

Processor Design: Step 4 Step 1: Analyze instruction set to determine datapath requirements

– Meaning of each instruction is given by register transfers – Datapath must include storage element for ISA registers – Datapath must support each register transfer

Step 2: Select set of datapath components & establish clock methodology Step 3: Assemble datapath components that meet the requirements Step 4: Analyze implementation of each instruction to determine setting of control points that realizes the register transfer Step 5: Assemble the control logic Dr Dan Garcia

Step 3a: Instruction Fetch Unit • Register Transfer Requirements  Datapath Assembly • Instruction Fetch • Read Operands and Execute Operation • Common RTL operations clk – Fetch the Instruction: mem[PC] – Update the program counter: • Sequential Code: PC  PC + 4 • Branch and Jump: PC  “something else”

PC Next Address Logic

Address

Instruction Word

Instruction Memory

32 Dr Dan Garcia

Step 3b: Add & Subtract • R[rd] = R[rs] op R[rt] (addu rd,rs,rt) – Ra, Rb, and Rw come from instruction’s Rs, Rt, and Rd fields 31

26 op 6 bits

21 rs 5 bits

16 rt 5 bits

11 rd 5 bits

6 shamt 5 bits

0 funct 6 bits

– ALUctr and RegWr: control logic after decoding the instruction Rd Rs Rt RegWr 5 5 5

clk

Rw Ra Rb 32 x 32-bit Registers

busA 32 busB

ALU

busW 32

ALUctr Result 32

32

• … Already defined the register file & ALU Dr Dan Garcia

R-Type Instruction

Chapter 4 — The Processor — 33

3c: Logical Op (or) with Immediate • R[rt] = R[rs] op ZeroExt[imm16] 31

26

21

op

rs

31 6 bits

RegDst

RegWr

Rw

Rs Rt

5 bits 16 15

16 bits

0

immediate 16 bits

5

ALUctr

5

Ra Rb

busA busB 32

clk 16

ZeroExt

imm16

32

ALU

RegFile

32

5 bits

immediate

Writing to Rt register (not Rd)!!

0

5

0

rt

0000000000000000 16 bits

Rd Rt 1

16

0

32

What about Rt Read?

1

32

ALUSrc Dr Dan Garcia

3d: Load Operations • R[rt] = Mem[R[rs] + SignExt[imm16]] Example: lw rt,rs,imm16 31

26

21

op

16

rs

6 bits

0

rt

5 bits

immediate

5 bits

16 bits

RegDst Rd Rt 1

RegWr

0

5 Rw

Rs Rt 5

ALUctr

5

Ra Rb

busA busB 32

clk 16

ZeroExt

imm16

ALU

RegFile

32

32 32

0

1

32

ALUSrc Dr Dan Garcia

3d: Load Operations • R[rt] = Mem[R[rs] + SignExt[imm16]] Example: lw rt,rs,imm16 31

26

21

op

16

rs

6 bits

0

rt

5 bits

immediate

5 bits

16 bits

1

RegWr

0

Rs Rt

5

5

Rw

busW

5

Ra Rb

busA

busB 32

imm16 16

ExtOp

Extender

clk

32

ALU

RegFile

32

MemtoReg

ALUctr

RegDst Rd Rt

32 0

0 Adr 1

32

ALUSrc

clk

Data Memory

1

Dr Dan Garcia

3e: Store Operations • Mem[ R[rs] + SignExt[imm16] ] = R[rt] Ex.: sw rt, rs, imm16 31

26

21

op 6 bits

16

rs 5 bits

rt 5 bits

immediate 16 bits

RegDst Rd Rt 1

RegWr

ALUctr

0 5

5

5

busA busB 32

imm16

16

ExtOp

Extender

clk

32

0

ALU

RegFile

32

MemtoReg MemWr

Rs Rt

Rw Ra Rb

busW

0

32 0

32 WrEn Adr

1 32

ALUSrc

Data In clk

Data Memory

1

Dr Dan Garcia

3e: Store Operations • Mem[ R[rs] + SignExt[imm16] ] = R[rt] Ex.: sw rt, rs, imm16 31

26

21

op 6 bits

16

rs 5 bits

rt 5 bits

immediate 16 bits

RegDst Rd Rt 1

RegWr

ALUctr

0 5

5

5

busA busB 32

imm16

16

ExtOp

Extender

clk

32

0

ALU

RegFile

32

MemtoReg MemWr

Rs Rt

Rw Ra Rb

busW

0

32 0

32 WrEn Adr

1 32

ALUSrc

Data In clk

Data Memory

1

Dr Dan Garcia

Load Instruction

Chapter 4 — The Processor — 39

3f: The Branch Instruction 31

26

op 6 bits

21

rs 5 bits

16

rt 5 bits

immediate 16 bits

0

beq rs, rt, imm16 – mem[PC] Fetch the instruction from memory – Equal = R[rs] == R[rt] Calculate branch condition – if (Equal) Calculate the next instruction’s address • PC = PC + 4 + ( SignExt(imm16) x 4 )

else • PC = PC + 4

Dr Dan Garcia

Copyright © 2014 Elsevier Inc. All rights reserved.

41

Datapath for Branch Operations beq rs, rt, imm16

31

26 op 6 bits

21 rs 5 bits

16

0

rt 5 bits

immediate 16 bits

Datapath generates condition (Equal) Inst Address

00

RegWr

clk

busW

clk

5

Rs Rt 5

ALUctr

5

Rw Ra Rb

busA

RegFile

busB

32

= ALU

PC

Mux

Adder

PC Ext

imm16

nPC_sel Adder

4

Equal

32

32

Already have mux, adder, need special sign extender for PC, need equal compare (sub?) Dr Dan Garcia

Instruction Fetch Unit including Branch 31

26 op

21 rs

16 rt

0 immediate

• if (Zero == 1) then PC = PC + 4 + SignExt[imm16]*4 ; else PC = PC + 4 Inst Instruction

Memory Adr

nPC_sel Equal

MUX ctrl nPC_sel

• How to encode nPC_sel? • Direct MUX select?

0

00

• Branch inst. / not branch inst. Mux

PC

Adder

PC Ext

imm16

Adder

4

1

clk

• Let’s pick 2nd option nPC_sel 0 1 1

zero? x 0 1

MUX 0 0 1

Q: What logic gate? Dr Dan Garcia

Branch-on-Equal Instruction

Chapter 4 — The Processor — 44

Putting it All Together (without jump) :A Single Cycle Datapath

RegDst

32

0 5

5

5

Rw Ra Rb

RegFile

busA busB 32

16

Extender

imm16

MemtoReg MemWr

Rs Rt

clk clk

ALUctr

Equal

32

= ALU

busW

PC

PC Ext

Adder

Mux

00

RegWr Adder

4

Rt Rd Imm16

Rd Rt 1

Instruction



nPC_sel

Rs



Adr





Inst Memory

0 32 1

32

Data In clk

32 0 WrEn Adr

Data Memory

1

imm16 ExtOp

ALUSrc

Dr Dan Garcia

Implementing Jumps Jump

 

address

31:26

25:0

Jump uses word address Update PC with concatenation of  





2

Top 4 bits of old PC 26-bit jump address 00

Need an extra control signal decoded from opcode Chapter 4 — The Processor — 46

Single Cycle Datapath during Jump 31

26 25

J-type

0

op

target address

jump

• New PC = { PC[31..28], target address, 00 } Instruction

Jump=

Rd Imm16 TA26 MemtoReg = MemWr =

0

32

Data In 32 Clk



32

Rs

WrEn Adr

32

Mux

1



16

Extender

imm16

Zero

Mux

32 Clk

busA Rw Ra Rb 32 32 x 32-bit Registers busB 0 32

ALU

busW

5

Rt

ALUctr =

Rs Rt 5 5



RegWr =

Clk



RegDst =



Rd Rt 1 Mux 0

Instruction Fetch Unit

nPC_sel=

1

Data Memory

ALUSrc = ExtOp =

Dr Dan Garcia

Single Cycle Datapath during Jump 31

26 25

0

op

J-type

target address

jump

• New PC = { PC[31..28], target address, 00 } Instruction

Jump=1

Clk



Rd Imm16 TA26 MemtoReg = x MemWr = 0

0

WrEn Adr

32

Mux

32

Rs

32

Data In 32



1



16

Extender

imm16

Zero

Mux

32 Clk

busA Rw Ra Rb 32 32 x 32-bit busB Registers 0 32

ALU

busW

5

Rt

ALUctr =x

Rs Rt 5 5



RegWr = 0

Clk



RegDst = x

Rd Rt 1 Mux 0

Instruction Fetch Unit

nPC_sel=?

1

Data Memory

ALUSrc = x ExtOp = x

Dr Dan Garcia

Instruction Fetch Unit at the End of Jump 31

26 25

J-type

0

op

target address

jump

• New PC = { PC[31..28], target address, 00 } Jump

Inst Memory

nPC_sel

Adr

Instruction

Zero nPC_MUX_sel

Adder

00

4 0

Adder

imm16

PC

Mux

How do we modify this to account for jumps?

1 Clk Dr Dan Garcia

Instruction Fetch Unit at the End of Jump 31

26 25

0

op

J-type

target address

jump

• New PC = { PC[31..28], target address, 00 } Inst Memory

Jump nPC_sel

Instruction

Adr

Zero

imm16

00

TA Mux Adder

1

4 (MSBs)

1

PC

Adder

0

26

Mux

4

00

nPC_MUX_sel

0

Clk

Query • Can Zero still get asserted?

• Does nPC_sel need to be 0? • If not, what? Dr Dan Garcia

Datapath With Jumps Added

Chapter 4 — The Processor — 51

Datapath Control Signals • ExtOp: • ALUsrc: • ALUctr:

• • • •

“zero”, “sign” 0  regB; 1  immed “ADD”, “SUB”, “OR”

MemWr: MemtoReg: RegDst: RegWr:

ALUctr MemtoReg MemWr

RegDst Rd Rt 1

Inst Address 4

RegWr

0

Rs Rt

5

5

Rw

busW

5

Ra Rb

busA

RegFile

busB

PC

Mux

32

clk

imm16 16

ExtOp

Extender

PC Ext

Adder

1

32 0

0

32

clk

32 ALU

Adder

0

00

nPC_sel & Equal

1  write memory 0  ALU; 1  Mem 0  “rt”; 1  “rd” 1  write register

32 WrEn Adr 1

Data In

ALUSrc

clk

32

Data Memory

1

Dr Dan Garcia

imm16

Given Datapath: RTL  Control Instruction

Rd



Rs



Rt



Op Fun







Inst Memory Adr

Imm16

Control nPC_sel RegWr RegDst ExtOp ALUSrc ALUctr

MemWr MemtoReg

DATA PATH

Dr Dan Garcia

RTL: The Add Instruction 31

26 op 6 bits

21 rs 5 bits

16 rt 5 bits

11

6

0

rd

shamt

funct

5 bits

5 bits

6 bits

add rd, rs, rt – MEM[PC] Fetch the instruction from memory – R[rd] = R[rs] + R[rt] The actual operation – PC = PC + 4 Calculate the next instruction’s address

Dr Dan Garcia

Instruction Fetch Unit at the Beginning of Add • Fetch the instruction from Instruction memory: Instruction = MEM[PC] – same for all instructions

Inst Memory nPC_sel

Inst Address

00

Adder

4

Instruction

PC

Mux Adder

PC Ext

clk

imm16 Dr Dan Garcia

Single Cycle Datapath during Add 31

26 op

21

16

rs

11

rt

rd

6 shamt

R[rd] = R[rs] + R[rt]

5

5

Rw

busW

5

busA

Ra Rb

busB 32

imm16 16

ExtOp=x

Extender

clk

Rs Rt Rd Imm16 zero ALUctr=ADD MemtoReg=0 MemWr=0 32 =

ALU

RegFile

32



Rs Rt



RegWr=1

0



1



Rd Rt

funct

Instruction

instr fetch unit

nPC_sel=+4 RegDst=1 clk

0

32 0

0 32 1

Data In

32

ALUSrc=0

clk

WrEn Adr

Data Memory

1

Dr Dan Garcia

Instruction Fetch Unit at End of Add • PC = PC + 4 – Same for all instructions except: Branch and Jump

nPC_sel=+4

Inst Address

00

Adder

4

Inst Memory

PC

Mux Adder

PC Ext

clk

imm16 Dr Dan Garcia

Processor Design: Step 5 Step 1: Analyze instruction set to determine datapath requirements

– Meaning of each instruction is given by register transfers – Datapath must include storage element for ISA registers – Datapath must support each register transfer

Step 2: Select set of datapath components & establish clock methodology Step 3: Assemble datapath components that meet the requirements Step 4: Analyze implementation of each instruction to determine setting of control points that realizes the register transfer Step 5: Assemble the control logic Dr Dan Garcia

Summary of the Control Signals (1/2) inst

Register Transfer

add

R[rd]  R[rs] + R[rt]; PC  PC + 4 ALUsrc=RegB, ALUctr=“ADD”, RegDst=rd, RegWr, nPC_sel=“+4”

sub

R[rd]  R[rs] – R[rt]; PC  PC + 4 ALUsrc=RegB, ALUctr=“SUB”, RegDst=rd, RegWr, nPC_sel=“+4”

ori

R[rt]  R[rs] + zero_ext(Imm16); PC  PC + 4 ALUsrc=Im, Extop=“Z”, ALUctr=“OR”, RegDst=rt,RegWr, nPC_sel=“+4”

lw

R[rt]  MEM[ R[rs] + sign_ext(Imm16)]; PC  PC + 4 ALUsrc=Im, Extop=“sn”, ALUctr=“ADD”, MemtoReg, RegDst=rt, RegWr, nPC_sel = “+4”

sw

MEM[ R[rs] + sign_ext(Imm16)]  R[rs]; PC  PC + 4 ALUsrc=Im, Extop=“sn”, ALUctr = “ADD”, MemWr, nPC_sel = “+4”

beq

if (R[rs] == R[rt]) then PC  PC + sign_ext(Imm16)] || 00 else PC  PC + 4 nPC_sel = “br”,

ALUctr = “SUB” Dr Dan Garcia

Summary of the Control Signals (2/2) See Appendix A

func 10 0000 10 0010

(xx…x)[We Don’t Care]

op 00 0000 00 0000 00 1101 10 0011 10 1011 00 0100 00 0010 add

sub

ori

lw

sw

beq

jump

RegDst

1

1

0

0

x

x

x

ALUSrc

0

0

1

1

1

0

x

MemtoReg

0

0

0

1

x

x

x

RegWrite

1

1

1

1

0

0

0

MemWrite

0

0

0

0

1

0

0

nPCsel

0

0

0

0

0

1

?

Jump

0

0

0

0

0

0

1

ExtOp

x

x

0

1

1

x

Add

Subtract

Or

Add

Add

x Subtract

ALUctr 31

26

21

16

R-type

op

rs

rt

I-type

op

rs

rt

J-type

op

11 rd

6 shamt immediate

target address

x 0

funct

add, sub ori, lw, sw, beq jump Dr Dan Garcia

ALU Control 

Assume 2-bit ALUOp derived from opcode 

Combinational logic derives ALU control

opcode

ALUOp

Operation

funct

ALU function

ALU control

lw

00

load word

XXXXXX

add

0010

sw

00

store word

XXXXXX

add

0010

beq

01

branch equal

XXXXXX

subtract

0110

R-type

10

add

100000

add

0010

subtract

100010

subtract

0110

AND

100100

AND

0000

OR

100101

OR

0001

set-on-less-than

101010

set-on-less-than

0111

Chapter 4 — The Processor — 61

Boolean Expressions for Controller RegDst ALUSrc MemtoReg RegWrite MemWrite nPCsel Jump ExtOp ALUctr[0] ALUctr[1]

= = = = = = = = = =

add + sub ori + lw + sw lw add + sub + ori + lw sw beq jump lw + sw sub + beq (assume ALUctr is 00 ADD, 01 SUB, 10 OR) or

Where: rtype ori lw sw beq jump

= = = = = =

~op5 ~op5 op5 op5 ~op5 ~op5

     

~op4 ~op4 ~op4 ~op4 ~op4 ~op4

     

~op3 op3 ~op3 op3 ~op3 ~op3

     

~op2 op2 ~op2 ~op2 op2 ~op2

     

~op1 ~op1 op1 op1 ~op1 op1

 ~op0,  op0  op0  op0  ~op0  ~op0

How do we implement this in gates?

add = rtype  func5  ~func4  ~func3  ~func2  ~func1  ~func0 sub = rtype  func5  ~func4  ~func3  ~func2  func1  ~func0 Dr Dan Garcia

Controller Implementation opcode

func

“AND” logic

add sub ori lw sw beq jump

“OR” logic

RegDst ALUSrc MemtoReg RegWrite MemWrite nPCsel Jump ExtOp ALUctr[0] ALUctr[1]

Dr Dan Garcia

Summary: Single-cycle Processor • Five steps to design a processor: Processor 1. Analyze instruction set  Input datapath requirements Control Memory 2. Select set of datapath components & establish Datapath Output clock methodology 3. Assemble datapath meeting the requirements 4. Analyze implementation of each instruction to determine setting of control points that effects the register transfer. 5. Assemble the control logic

• Formulate Logic Equations • Design Circuits Dr Dan Garcia