Computer Science 237 Lab 6 Due: High noon next Tuesday This week I would like you to design and build a simple 8-bit random number generator using a linear feedback shift register . We review pertinent details, here, for implementing this interesting device in logic. In lab we will learn how to use the power supplies, breadboards, and TTL chips to build our device in hardware. A

B

C

SI

March 1998

Q7 Q6 Q5 Q4 Q3 Q2 Q1 Q0

1

DM74LS164 8-Bit Serial In/Parallel Out Shift Register

DM74LS164 8-Bit Serial In/Parallel Out Shift Register

CLK

Our implementation will make use of a logical device, the serial shift register :

on the low-to-high level transition of the clock input. All inputs General This device contains 8 bits of memory that are Description used to remember the most recent sequence of values that have are diode-clamped to minimize transmission-line effects. These 8-bit shift registers feature gated serial inputs and an appeared on the pin SI (‘shift in’). Each time the clock (CLK) line rises from 0 to 1, the register moves all bits to the asynchronous clear. A low logic level at either input inhibits Features entry of the new data, and resets the first flip-flop to the low left (the value at Q0 moves to Q1, etc.), and the value at SI appears in the register at location Q0. The value once n Gated (enable/disable) serial inputs level at the next clock pulse, thus providing complete control buffered and serial inputs over incoming high logic level oncycles either input8 enables stored in the high bit, Q7, is shifted out and lost. data. AsA the clock timesn aFullybyte ofclock data read serially appears as the other input, which will then determine the state of the first n Asynchronous clear flip-flop. Data at the inputs may be changed while the block the output of the register. Serial shift registers are a serial fundamental building of all devices that communicate by n Typical clock frequency 36 MHz clock is high or low, but only information meeting the setup n Typical power dissipation 80 mW 2 receiving bits one at a time over a wire, through the air, or from a bit-serial store, like a hard disk. and hold time requirements will be entered. Clocking occurs

In our actual circuit we will use a TTL chip, theDiagram 74-164. It has the following pin Table configuration, or pinout: Connection Function Inputs

Dual-In-Line Package

Outputs

Clear

Clock

A

B

QA

QB

...

L

X

X

X

L

L

...

L

H

L

X

X

QA0

QB0

...

QH0

H

!

H

H

H

QAn

...

QGn

H

!

L

X

L

QAn

...

QGn

H

!

X

L

L

QAn

...

QGn

QH

H = High Level (steady state), L = Low Level (steady state) X = Don’t Care (any input, including transitions) ! = Transition from low to high level QA0, QB0, QH0 = The level of QA, QB, or QH, respectively, before the indicated steady-state input conditions were established. QAn, QGn = The level of QA or QG before the most recent ! transition of the clock; indicates a one-bit shift.

3

DS006398-1

Order Number 54LS164DMQB, 54LS164FMQB, 54LS164LMQB, DM54LS164J, DM54LS164W, DM74LS164M or DM74LS164N See Package Number E20A, J14A, M14A, N14A or W14B

As with all integrated circuits, this chip is powered by two pins, Vcc and GND. The pins A and B are typically wired together1 and provide ‘shift in’ bits: every bit that appears on these pins is captured when the clock goes high. Next, the outputs are labeled QA through QH. Diagram The standard for labeling pins in 7400 series of devices is, at best, Logic inconsistent; in general you need to scour the TTL product description pages to learn about these details. Here, the QA pin is the least significant bit in the stored byte. Be careful: some devices do not have Vcc and GND in the corners 4 or take ordered bits out of order. Reading the device documentation will save you time and reduce your sorrow. The CLOCK line works exactly as CLK described above: the A/B lines are strobed into the device on the rising edge of this signal. This edge-based triggering is always indicated by a little triangle at the entrance of the signal. If the TTL picture does not have that triangle, the action happens as long as the clock is high; it is level-triggered . Finally, an appropriate signal on the CLEAR will clear the internal memory to zeros. Because there is an ‘inverter bubble’ on the pin, we say the signal is active low : the clear will happen as long as the CLEAR pin is grounded.2 I leave it to you to determine if the register starts up in a cleared state. DS006398-2

© 1998 Fairchild Semiconductor Corporation

DS006398

www.fairchildsemi.com

The 8-bit Linear Feedback Shift Register. Ideally, our 8-bit number generator would present an orbit of 256 5 random values3 before any value is repeated. The linear feedback approach takes several bits from the serial shift 1 This

is strange. You might read the device documentation to discover other ways the designers imagined this device would be used. you see both a inverter bubble and a edge-trigger triangle, the action occurs during the 1 to 0 or falling edge transition. A C 3 These values are not random, of course (the circuit is deterministic, after all), but for manyB purposes they sufficiently unpredictable. 2 If

register at positions called taps and computes a mod-2 sum (think: XOR) to generate the next bit to be shifted in. (We should begin our worrying now: if the register ever contained a zero, it would could never change. Why? Because there are no 1’s to generate a non-zero value. This configuration is said to lock up the device. Worry on.) It turns out that, starting with a non-zero value, four tap bits will support an orbit of 255 distinct values before the device again returns the first value. The location of the tap bits (as always, 0 is least significant) for registers with 8 or fewer bits is given in the following table:

n 1 5

LFSR taps 0 42

Tap n 2 6

Bits for Maximal Orbits taps n taps n taps 10 3 21 4 32 54 7 65 8 7543

Procedure. I would like you to build an 8-bit linear feedback shift register whose lock up configuration is all 1’s (as opposed to all 0’s). 1. Build a circuit that will allow you to fully control the 74-164 shift register. All inputs should be sourced by power, ground, or switches. All outputs should be visible through the LED’s. 2. Determine, as best you can, whether the device powers up in an all-zero state. If not, your final circuit should probably have a button that allows you to clear the register in case it gets locked up. 3. Clear your register and attempt to shift in a single one. You may observe that the slide switches on your bench are not debounced . Mechanical switching devices frequently make many momentary contacts before they settle into position. This might result in your device strobing in several ones before the clock switch settles. This behavior can be avoided by using debouncing circuitry present in the ‘momentary’ pushbuttons, A and B. 4. Design a network of taps that maximizes the orbit of the generator. I expect you to use one or two more chips from your initial set. If necessary, you can borrow parts from our common supply cabinet but be aware that the 7400-family of devices does not include every kind of gate you might want. It is likely (nay, certain) that the devices I have already given you are sufficient for your purposes. 5. Implement the circuit and verify that it is working correctly. When you are satisfied with your generator draw the logical network (ie. the gates, not the chips) you used, and report the first 16 decimal values your circuit generates. The first should be zero, of course. 6. Consider answering one or more of the extra credit questions, below. 7. After sending a picture of your circuit to your mother (she will be proud), tear down your circuit. 8. Turn in your written answers by noon next Tuesday. Extra credit: 1. Notice that the tap bits always include the most significant bit. For example, bit 7 is needed for an 8 bit LFSR and bit 3 is needed for a 4 bit version. Explain why this must be true. 2. It would be much nicer if we could automate the generation of CLOCK signal. This is easily accomplished by running a wire from the function generator to the CLOCK line of your 74-164. (Try it!) Indeed, the circuit can be driven quite quickly (Try it!). Unfortunately, the slowest square wave generated is 1 Hz (yeah, sure, try it.). Can you, based on a 1 Hz setting of the function generator and one or two additional chips, arrange for your circuit to deliver new random values every 5 seconds? Explain how. 3. Perhaps you want it to run more slowly. Can you generate a new random value every 10 seconds? Keep the square wave frequency at 1 Hz and try to avoid going to the parts cabinet. Explain your logic.

7

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DM74LS00 Quad 2-Input NAND Gates General Description This device contains four independent gates each of which performs the logic NAND function.

Features n Alternate Military/Aerospace device (54LS00) is available. Contact a Fairchild Semiconductor Sales Office/Distributor for specifications.

Connection Diagram Dual-In-Line Package

DS006439-1

Order Number 54LS00DMQB, 54LS00FMQB, 54LS00LMQB, DM54LS00J, DM54LS00W, DM74LS00M or DM74LS00N See Package Number E20A, J14A, M14A, N14A or W14B

Function Table Y = AB Inputs

Output

A

B

Y

L

L

H

L

H

H

H

L

H

H

H

L

H = High Logic Level L = Low Logic Level

© 1998 Fairchild Semiconductor Corporation

DS006439

www.fairchildsemi.com

DM74LS00 Quad 2-Input NAND Gates

March 1998

DM74LS04 Hex Inverting Gates General Description This device contains six independent gates each of which performs the logic INVERT function.

Features n Alternate Military/Aerospace device (54LS04) is available. Contact a Fairchild Semiconductor Sales Office/Distributor for specifications.

Connection Diagram Dual-In-Line Package

DS006345-1

Order Number 54LS04DMQB, 54LS04FMQB, 54LS04LMQB, DM54LS04J, DM54LS04W, DM74LS04M or DM74LS04N See Package Number E20A, J14A, M14A, N14A or W14B

Function Table Y=A Input

Output

A

Y

L

H

H

L

H = High Logic Level L = Low Logic Level

© 1998 Fairchild Semiconductor Corporation

DS006345

www.fairchildsemi.com

DM74LS04 Hex Inverting Gates

March 1998

DM74LS86 Quad 2-Input Exclusive-OR Gates General Description This device contains four independent gates each of which performs the logic exclusive-OR function.

Connection Diagram Dual-In-Line Package

DS006380-1

Order Number DM54LS86J, DM54LS86W, DM74LS86M or DM74LS86N See Package Number J14A, M14A, N14A or W14B

Function Table Y = A % B = A B + AB Inputs

Output

A

B

L

L

Y L

L

H

H

H

L

H

H

H

L

H = High Logic Level L = Low Logic Level

© 1998 Fairchild Semiconductor Corporation

DS006380

www.fairchildsemi.com

DM74LS86 Quad 2-Input Exclusive-OR Gates

March 1998

DM74LS164 8-Bit Serial In/Parallel Out Shift Register General Description These 8-bit shift registers feature gated serial inputs and an asynchronous clear. A low logic level at either input inhibits entry of the new data, and resets the first flip-flop to the low level at the next clock pulse, thus providing complete control over incoming data. A high logic level on either input enables the other input, which will then determine the state of the first flip-flop. Data at the serial inputs may be changed while the clock is high or low, but only information meeting the setup and hold time requirements will be entered. Clocking occurs

Connection Diagram

on the low-to-high level transition of the clock input. All inputs are diode-clamped to minimize transmission-line effects.

Features n n n n n

Gated (enable/disable) serial inputs Fully buffered clock and serial inputs Asynchronous clear Typical clock frequency 36 MHz Typical power dissipation 80 mW

Function Table Inputs

Dual-In-Line Package

Outputs

Clear

Clock

A

B

QA

QB

...

L

X

X

X

L

L

...

L

H

L

X

X

QA0

QB0

...

QH0

H

↑

H

H

H

QAn

...

QGn

H

↑

L

X

L

QAn

...

QGn

H

↑

X

L

L

QAn

...

QGn

QH

H = High Level (steady state), L = Low Level (steady state) X = Don’t Care (any input, including transitions) ↑ = Transition from low to high level QA0, QB0, QH0 = The level of QA, QB, or QH, respectively, before the indicated steady-state input conditions were established. QAn, QGn = The level of QA or QG before the most recent ↑ transition of the clock; indicates a one-bit shift.

DS006398-1

Order Number 54LS164DMQB, 54LS164FMQB, 54LS164LMQB, DM54LS164J, DM54LS164W, DM74LS164M or DM74LS164N See Package Number E20A, J14A, M14A, N14A or W14B

Logic Diagram

DS006398-2

© 1998 Fairchild Semiconductor Corporation

DS006398

www.fairchildsemi.com

DM74LS164 8-Bit Serial In/Parallel Out Shift Register

March 1998