Compensating a PFC Stage
Agenda • Introduction • Deriving a small-signal model – General method – Practical example: NCP1605-driven PFC stages
• Compensating the loop – – – –
Type-2 compensation Influence of the line and power level Computing the compensation Practical example
• Conclusion
Output Voltage Low Frequency Ripple Vout Pin(t)
Pin,avg
+
Iin(t)
Vin(t)
The load power demand is matched in average only A low frequency ripple is inherent to the PFC function
PFC Stages are Slow Systems… The output ripple must be filtered to avoid current distortion. In practice, the loop frequency is selected in the range of 20 Hz, which is very low. Even if the bandwidth is low, the loop must be compensated!
Agenda • Introduction • Deriving a small-signal model – General method – Practical example: NCP1605-driven PFC stages
• Compensating the loop – – – –
Type-2 compensation Influence of the line and power level Computing the compensation Practical example
• Conclusion
A Simple Representation • We will consider the PFC stage as a system delivering a power under an input rms voltage and a control signal Pout
Vin(rms) PFC stage
Vcontrol
• Details of the power processing are ignored: • Operation mode (CrM, CCM, Voltage or Current mode…) • 100% efficiency, only the average power contribution of the sinusoidal signals is considered
A Simple Large Signal Model • Let’s represent the PFC stage as a current source delivering the power to the bulk capacitor and the load:
ID =
Pin ( avg ) Vout
Bulk Capacitor
rC Load
RLOAD Cbulk
• Pin(avg) depends on Vcontrol (always), on Vin(rms) (in the absence of feedforward) and sometimes on Vout • 3 possible sources of perturbations: Vcontrol, Vout and Vin(rms).
NCP1605 • Frequency Clamped Critical Conduction Mode (FCCrM) • Key features for a master PFC: • High voltage current source, Soft-SkipTM during standby mode • “pfcOK” signal, dynamic response enhancer • Bunch of protections for rugged PFC stages
• Markets: high power AC adapters, LCD TVs Rbo1
Rout1
Rout2
Vout STBY control
Rbo2
HV 1
16
2
15
3
14
Vcc
Cbo CVctrl
FB
L1
Rovp1
Vout
OVP Rovp2
D1
13
4
CVref 5
12
6
11
7
10
8
9
Rzcd
Ac line
pfcOK Cin Ct
EMI Filter
LOAD
Vcc
M1 Cbulk
Cosc
pfcOK
Rocp
Rdrv
Icoil
Rcs
Communication signals
NCP1605 – Follower Boost • Voltage mode operation: the circuit adjusts the power level by modulating the MOSFET conduction time • The charge current of the timing capacitor is proportional to the FB square and hence to (Vout)2: Ich arg e
⎛ Vout = It ⋅ ⎜ ⎜ Vout ,nom ⎝
⎞ ⎟ ⎟ ⎠
2
where : Vout,nom is the Vout regulation voltage It is a 370-µA current source
• The on-time is inversely proportional to (Vout)2 allowing the Follower boost function: 2 ton
Ct ⋅Vton = It
⎛ Vout ,nom ⋅ ⎜⎜ ⎝ Vout
⎞ ⎟⎟ ⎠
NCP1605 - Power Expression 200 µA
0.955*Vref FB
+
Error Amplifier Vref
+/-20µA
+
• The control signal is VF offset down and divided by 3 to form VREGUL used in the PWM section
pfcOK
Vou t low detect
OVLflag1
Vcon trol
VF
OFF
2R
VF
VREGUL 3V
R
• Hence due to the follower boost function, the power is inversely dependent on (Vout)2: Pin( avg )
Ct ⋅ Vin( rms )2 ⎛ Vout ,nom = ⋅ ⎜⎜ 2 ⋅ L ⋅ It ⎝ Vout
⎞ (Vcontrol − VF ) ⎟⎟ ⋅ 3 ⎠ 2
NCP1605 - Large Signal Model • Let’s represent the PFC stage as a current source delivering the power to the bulk capacitor and the load:
ID =
Pin ( avg )
Replacing Pin,avg by its expression of slide 10
rC
Vout
2 2⎞ ⎛ ⎛ C ⋅V V ⋅ (Vcontrol − VF ) ⎞ ( ) in rms , t out nom ⎟ ⎟⋅⎜ ID = ⎜ 3 ⎜ 6 ⋅ L ⋅ It ⎟ ⎜ ⎟ Vout ⎝ ⎠ ⎝ ⎠
constants
Time varying terms
RLOAD Cbulk
• 3 sources of perturbations: VCONTROL, Vout and Vin(rms).
Small Signal Model • A large signal model is nonlinear because ID is formed of the multiplication and division of Vcontrol, Vin,rms and Vout. • This model needs to be linearized to assess the AC contribution of each variable • The model is perturbed and linearized around a quiescient operating point (DC point)
Considering Variations Around the DC Value… • Let’s omit the perturbations of the line magnitude (assumed constant) • Let’s consider small variations around the DC values for ∂ID $ Vout and Vcontrol: $i = ∂ID ⋅ v$ + ⋅v D
∂Vcontrol
CONTROL
∂Vout
out
• We then obtain: Vout ,nom + v$ out
rC ID + $i D where : $i D =
∂ID ∂ID $ ⋅ v$ control + ⋅v ∂Vcontrol ∂Vout out
RLOAD Cbulk
Deriving a Small Signal Model… • The DC portion can be eliminated • The partial derivatives are to be computed at the DC point that is for: – Vcontrol that is the control signal DC value for the considered working point – Vout,nom that is the nominal (DC) output voltage
• Replacing the derivations by their expression, we obtain: v$ out rC
I1 =
∂ID $ ⋅ v out ∂Vout
I1 computed for Vcontrol DC point
I2 =
∂ID ⋅ v$ control ∂Vcontrol
I2 computed for Vout DC point that is Vout,nom
RLOAD Cbulk
Contribution of the Vout Perturbations • Depending on the controller scheme ID =
Pin,avg Vout
=
(
f Vin( rms ),Vcontrol
(Vout )
)
• n=0 for NCP1607 • n=1 for NCP1654 (predictive CCM PFC for which • n=2 for NCP1605 (follower boost – see slide 10)
• At the DC point
Vout = Vout ,nom
where n = 0,1 or 2
n +1
and
Pin,avg ∝
Vcontrol ⋅Vin,rms Vout
Pin(avg )
(
Vout ,nom
)
2
=
)
1 RLOAD
• Finally: (
( n + 1) ⋅ f Vin(rms ),Vcontrol ∂ID $ I1 = ⋅ v out = − ∂Vout (V )n + 2 out
)
⋅ v$ out = − Vout =Vout ,nom
( n + 1) ⋅ Pin(avg )
(Vout,nom )
2
⋅ v$ out = −
( n + 1) ⋅ v$
RLOAD
out
2 Resistors… • Hence, the small signal model can be simplified as follows:
I2 =
∂ID ⋅ v$ control ∂Vcontrol
v$ out
rC
RLOAD n +1
RLOAD
Cbulk Vout AC contribution
•
Noting that:
RLOAD n +1
RLOAD =
RLOAD n+2
the model can be further simplified
Load
Finally… The small signal model is:
I2 =
RLOAD ⋅ n+2
1 + s ⋅ rC ⋅ Cbulk ⋅C ⎛R ⎞ 1 + s ⎜ LOAD bulk ⎟ n+2 ⎝ ⎠
v$ out
∂ID ⋅ v$ control ∂Vcontrol
where : ID =
Z (s ) =
rC ⎛ RLOAD ⎞ ⎜ ⎟ ⎝ n+2 ⎠
Pin,avg Vout
Cbulk
The transfer function is: v$ out v$
control
R = LOAD n+2
⎛ ∂ID ⋅ ⎜⎜ ⎝ ∂Vcontrol
⎞ 1 + s ⋅ rC ⋅ Cbulk ⋅ ⎟⎟ ⎠ 1 + s ⎛ RLOAD ⋅ Cbulk ⎞ ⎜ ⎟ n+2 ⎝ ⎠
NCP1605 Example • The large signal model instructed that: ID =
Pin ( avg ) Vout
2 2⎞ ⎛ ⎛ C ⋅V ⋅ (Vcontrol − VF ) ⎞ V ( ) in rms , t out nom ⎟ ⎟⋅⎜ =⎜ 3 ⎜ 6 ⋅ L ⋅ It ⎟ ⎜ ⎟ V out ⎝ ⎠ ⎝ ⎠
• Hence:
(Vout )n +1 n=2
(
)
2
Ct ⋅ Vin ( rms ) ∂ID = ∂Vcontrol 6 ⋅ L ⋅ It ⋅ Vout ,nom
term
NCP1605 - Small Signal Model • Finally:
(
)
v$ out rC
2
Ct ⋅ Vin ( rms ) I2 = ⋅ v$ CONTROL 6 ⋅ L ⋅ It ⋅ Vout ,nom
⎛ RLOAD ⎞ ⎜ ⎟ ⎝ 4 ⎠
Cbulk
• The transfer function is: v$ out v$ CONTROL
(
RLOAD ⋅ Ct ⋅ Vin ( rms ) = 24 ⋅ L ⋅ It ⋅ Vout ,nom
)
2
⋅
1 + s ⋅ rC ⋅ Cbulk ⋅C ⎛R ⎞ 1 + s ⋅ ⎜ LOAD bulk ⎟ 4 ⎝ ⎠
Power Stage Characteristic – Bode Plots ((
))
2 ⎛⎛ 2⎞ ⋅ C ⋅ V ⎜⎜ R LO AD t in rm s ( ) R ⋅ C ⋅ Vin ( rms ) ⎟ 20 ⋅ log ⎜⎜ LOAD t ⎟ 20 ⋅ log⎜ 24 ⋅ L ⋅ I ⋅ V 2 tK out⋅ V ,nom3 ⎟ ⎜ µ ⋅ L ⋅ 1440 ⎜ FB out ⎟ ⎝⎜ ⎝ ⎠
⎞ ⎟ ⎟ ⎟ ⎟ ⎠
Asymptotic representation
-20 dB/dec
Gain (dB)
Frequency (Hz) 0°
0°
Phase (°) -90° Frequency (Hz) fp 0 =
2
π ⋅ RLOAD ⋅ Cbulk
fz 0 =
1 2π ⋅ rC ⋅ Cbulk
Agenda • Introduction • Deriving a small-signal model – General method – Practical example: NCP1605-driven PFC stages
• Compensating the loop – – – –
Type-2 compensation Influence of the line and power level Computing the compensation Practical example
• Conclusion
Compensation Phase Boost • The zero brought by the bulk capacitor ESR is too high to bring some phase margin. It is ignored. • The PFC open loop inherently causes a -360°phase shift: – Power stage pole – Error amplifier inversion – Compensation origin pole
Î -90° Î -180° Î -90°
• The compensation must then provide some phase boost • A type-2 compensation is recommended
Type-2 Compensation • The NCP1605 embeds a transconductance error amplifier (OTA) 1 V CONTROL
VOUT
fz1 =
I CONTROL
2π ⋅ R1 ⋅ C1
R1 C1
C2
1 2π ⋅ R1 ⋅ C2 1 f p1 = 2π ⋅ R0 ⋅ C1 fp 2 =
RfbU OTA FB
to PWM comparator
RfbL
pole at the origin V REF
C2 1) - 20 dB/dec
20 ⋅ log(α )
Static gain Gain (dB)
Unchanged Gain and Phase at the targeted crossover frequency
RLOAD1 RLOAD2
Frequency (Hz)
-0°
Phase (°)
-90° Frequency (Hz) Asymptotic representation
fp 0 2 =
fp 0 1
α
fc
fz0 =
1 2π ⋅ rC ⋅ Cbulk
fc and φm are not affected!
Line Influence on the Open Loop Plots • No feedforward (e.g. NCP1607) and
(Vin(rms)2 = β ⋅Vin(rms)1
)
with β > 1
- 20 dB/dec
40 ⋅ log( β )
Static gain Gain (dB) Vin(rms)1 Vin(rms)2
Unchanged Phase but increased gain (multiplied by β*β )
Frequency (Hz)
-0°
Phase (°)
-90° Asymptotic representation
fp 0 =
n+2 2π ⋅ R LOAD ⋅ C bulk
Frequency (Hz)
fc
fz0
1 = 2π ⋅ rC ⋅ Cbulk
The loop crossover frequency is β 2 increased
Load and Line Considerations • Compensate at full load – Same crossover frequency at lighter loads – The zero frequency is set optimally (not at a too low frequency)
• Compensate at high line – High line is the worst case as in the absence of feedforward, the 2 static gain is proportional to (Vin( rms ) ) – This leads to:
( fc )HL
( (
⎛ V ⎜ in ( rms ) =⎜ ⎜⎜ Vin ( rms ) ⎝
) )
2
HL LL
⎞ ⎟ ⎟ ⋅ ( fc )LL ⎟⎟ ⎠
Where HL stands for Highest Line and LL for Lowest Line
– In universal mains applications, the high-line crossover frequency is 2 9 times higher than the low-line one: ⎛ 265 ⎞
( fc )HL = ⎜
⎟ ⋅ ( fc )LL ≅ 9 ⋅ ( fc )LL ⎝ 90 ⎠
Crossover Frequency Selection • In the absence of feedforward, ( fc )HL ≤ fline is a good option f
• With feedforward, ( fc )HL ≤ line is rather selected for a better 2 attenuation of the low frequency ripple • Get sure that on the line range, the PFC boost pole remains lower than the crossover frequency at full load! fp0 ≤ ( fc )LL
• If not, increase Cbulk
Agenda • Introduction • Deriving a small-signal model – General method – Practical example: NCP1605-driven PFC stages
• Compensating the loop – – – –
Type-2 compensation Influence of the line and power level Computing the compensation Practical example
• Conclusion
Compensation Techniques • Several techniques exist: manual placement, “k factor” (Venable)… + Systematic - The PFC boost gain is to be computed at fc fp 2 - No flexibility in the zero and high pole locations fc = k ⋅ fz1 = k
Pole and zero cancellation: 9 Place the compensation zero so that it cancels the power stage pole: 9 Force the pole at the origin to cancel the PFC boost gain when (f = fc) 9 Adjust the phase margin with the high frequency pole
Pole and Zero Cancellation… K0
-20 dB/dec Gain (dB)
Frequency (Hz)
Power stage Open Loop
ESR of the bulk capacitor
-40 dB/dec
0° -90°
Phase (°)
-180° -270°
φm
-360° fz1 = fp0
Frequency (Hz)
fc
fp 2
2 ⋅ fline
fz 0
The higher fp2, the larger the phase margin The lower fp2, the better the rejection of the low frequency ripple φm = 45° if fp2 = fc .
Poles and Zero Placement • Design the compensation for full load, high line: • Place the origin pole to cancel K0, the static gain at fc:
fp 0 =
fc K0
where :
for v$ out v$ CONTROL
• Place the zero so that it cancels the PFC boost pole ( fz1 = fp0 )
RLOAD = RLOAD(min)
RLOAD = RLOAD(min) = K0 ⋅
1 + s ⋅ rC ⋅ Cbulk ⎛ RLOAD(min) ⋅ Cbulk 1 + s ⋅ ⎜⎜ n+2 ⎝
for
• Place fp2 to obtain the targeted phase margin:
⎞ ⎟⎟ ⎠
RLOAD = RLOAD (min)
fp 2 =
fc tan ( 90° − φm )
Example • A wide mains, 150-W application driven by the NCP1605 • Vout,nom = 390 V R ⋅ C ⋅ (V ( ) ) v$ 1+ s ⋅ r ⋅ C =K ⋅ where : K = ⋅C 24 ⋅ L ⋅ I ⋅V ⎛R ⎞ v$ • (Vin(rms))LL = 90 V 1+ s ⋅ ⎜ ⎟ 4 ⎝ ⎠ • (Vin(rms))HL = 265 V (V ) = 390 ≅ 1 k Ω R • L = 150 µH ( ) = (P ) 150 • Ct = 4.7 nF V 390 R = = = 780 k Ω (OTA) V ⋅G 2.5 ⋅ 200 ⋅ 10 • Cbulk = 100 µF • rC = 500 mΩ (ESR) ⋅ C ⋅ (V ( ) ) R K 10 ⋅ 4.7 ⋅ 10 ⋅ 265 = ≅ 2.59 µF C = = ⋅ f ⋅ R ⋅ ⋅ L ⋅ I ⋅ V ⋅ ⋅ 2 f R 2 24 2 50 780k ⋅ 24 ⋅ 150 µ ⋅ 370 µ ⋅ 390 π π π ⋅ ⋅ • fc = 50 Hz and Φm = 60° R ⋅C 10 ⋅ 100 ⋅ 10 R = = ≅ 11.36 k Ω ==> 12 k Ω n + ⋅ C 2 ( ) ( 2 + 2) ⋅ 2.2 ⋅ 10 @ high line (265 V) 2
out
C
0
bulk
LOAD
CONTROL
2
t
in rms
t
out ,nom
0
bulk
2
out ,nom
LOAD min
LOAD
out max
out ,nom
−6
0
ref
EA
2
LOAD(min)
0(min)
t
in rms
1
c
0
LOAD(min)
c
0
t
1
fp1 =
tan ( 90° − φm ) 2π ⋅ fc ⋅ R1
2
out ,nom
−6
1
C2 =
−9
−6
3
bulk
3
HL
=
tan ( 90° − 60° )
==>
150 nF
1 = 6 Hz 2π ⋅ R1 ⋅ C1
fz1 =
2π ⋅ 50 ⋅ 12 ⋅ 103
1 = 93 mHz 2π ⋅ R0 ⋅ C1
fz1 =
≅ 153 nF
1 = 88 Hz 2π ⋅ R1 ⋅ C2
==>
2.2 µF
Simulation Validation • The simulation circuit is based on the large signal model: Vout Vout B6 Current
R10 50m
{Ct*Vbulk*Vbulk*Vrms*Vrms}*V(control)/(6*{L}*370u*V(Vout)*V(Vout)*V(Vout))
C5 100u IC = {Vrms*1.414}
Rload {Vbulk*Vbulk/Pout}
1
L1 1kH
C6 1kF Vin
Large signal model of the NCP1605driven PFC stage
6
V4 AC = 1
Generation and injection of the ac perturbation
EAout R4 {Rupper}
7
control
B1 Current
R1 12k
B5 Voltage V(EAout)
5
R2 100
EAout
FB
{gm}*(2.5-V(FB)) 4
C3 2.2u
C1 150nF
R3 {Rlower}
Feedback and regulation circuit (including type-2 compensation)
Open Loop Characteristic – Full Load fc= 52 Hz @ Vin(rms) = 265 V fc= 7 Hz @ Vin(rms) = 90 V Vin(rms) = 90 V
0 dB
Gain (dB)
Vin(rms) = 265 V
40 dB
10 mHz
100 mHz
1 Hz
10 Hz
100 Hz
1 kHz
φm = 62°
Phase (°)
10 kHz
6
100 kHz
4
45 °
φm = 87°
0°
Open Loop Characteristic – Mid Load fc= 52 Hz @ Vin(rms) = 265 V fc= 8 Hz @ Vin(rms) = 90 V Vin(rms) = 90 V
0 dB
Gain (dB)
Vin(rms) = 265 V
40 dB 1 2
10 mHz
100 mHz
1 Hz
10 Hz
100 Hz
1 kHz
φm = 58°
Phase (°)
10 kHz
100 kHz
4 3
45 °
φm = 69°
0°
Experimental Results at Full Load • •
A 19 V / 7 A loads the PFC stage The downstream converter swings between 6.3 A and 7.7 A (+/-10%) with a 2 A/µs slope Ac line current (5 A/div)
Vin,rms = 90 V
Bulk Voltage (20 VA/div – 380-V offset)
372 V < Vbulk < 396 V
Load Current (5 A/div)
•
Ac line current (2 A/div)
Vin,rms = 265 V
Bulk Voltage (20 VA/div – 380-V offset)
375 V < Vbulk < 394 V
Load Current (5 A/div)
The high-line, larger bandwidth reduces the Vbulk deviations and speedsup the output voltage recovery
Experimental Results at Medium Load • •
A 19 V / 7 A loads the PFC stage The downstream converter swings between 3.1 A and 3.9 A (+/-10%) with a 2 A/µs slope Ac line current (2 A/div)
Vin,rms = 90 V
Bulk Voltage (20 VA/div – 380-V offset)
376 V < Vbulk < 392 V
Load Current (2 A/div)
•
Ac line current (1 A/div)
Vin,rms = 265 V
Bulk Voltage (20 VA/div – 380-V offset)
379 V < Vbulk < 390 V
Load Current (2 A/div)
The circuit still exhibits a first order response
Abrupt Load Changes • •
A 19 V / 7 A loads the PFC stage The downstream converter swings from 7.0 A to 3.5 A (2 A/µs slope) Ac line current (2 A/div)
Vin,rms = 90 V
OVP 365 V < Vbulk < 411 V
Bulk Voltage (20 VA/div – 380-V offset)
Ac line current (2 A/div)
365 V < Vbulk < 404 V
Bulk Voltage (20 VA/div – 385-V offset) Vcontrol (1 V/div)
Vcontrol (2 V/div)
Load Current (5 A/div)
Vin,rms = 230 V
Load Current (5 A/div)
The dynamic response enhancer speeds-up the loop reaction in case of a large undershoot Implemented in NCP1605 (FCCrM), NCP1654 (CCM) and NCP1631 (Interleaved)
•
The dynamic response enhancer reduces the undershoot at low line
Agenda • Introduction • Deriving a small-signal model – General method – Practical example: NCP1605-driven PFC stages
• Compensating the loop – – – –
Type-2 compensation Influence of the line and power level Computing the compensation Practical example
• Conclusion
Conclusion • General considerations were illustrated by the case of NCP1605-driven PFC stages • A small signal model of PFC boosts can be easily derived • The proposed method is independent of the operating mode • A type-2 compensation is recommended • If no feed-forward is implemented, the loop bandwidth and phase margin vary as a function of the line magnitude • The crossover frequency does not vary as a function of the load • A resistive load can be used for the computation even if the PFC stage feeds a power supply (negative impedance) – See back-up
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•
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•
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