Chapter 3 Scan Architectures and Techniques

1

Chapter 3 Scan Architectures and Techniques

- >1,000,000 gates - >5,000,000 faults - >10,000 flip-flops - > 1,000 sequential depth - < 500 chip pins * > 2,000 gates/pin * > 2M = 21000 A deep sequential circuit Chip under Test without Scan

- >1,000,000 gates - >5,000,000 faults - > no effective flip-flops - > no sequential depth - < 500 + 10,000 chip pins * > 95.23 gates/pin * > 2M = 20 = 1 A combinational circuit Chip under Test with Full-Scan

Figure 3-1 Introduction to Scan-based Testing

Design-for-Test for Digital IC’s and Embedded Core Systems © 1999 Prentice Hall, All Rights Reserved

Alfred L. Crouch

Chapter 3 Scan Architectures and Techniques

2

Combinational & Sequential Logic input1 input2 input3 input4

output1 Q

D

QN clk

D

Q

D

Q

input5

D

input6

1

Q

2

output2

34

Sequential Depth of 4 Combinational Width of 6 26+4 = 1024 Vectors Figure 3-2 An Example Non-Scan Circuit

Design-for-Test for Digital IC’s and Embedded Core Systems © 1999 Prentice Hall, All Rights Reserved

Alfred L. Crouch

Chapter 3 Scan Architectures and Techniques

3

Combinational-Only Logic

input1 input2 input3 input4

output1 D

Q QN D

Q

D

Q

input5

input6

D

Q

output2

TPI1 TPI2 TPI3 TPI4 TPI5

A no-clock, combinational-only circuit with: 6 inputs plus 5 pseudo-inputs and

TPO1 TPO2 TPO3 TPO4

2 outputs plus 4 pseudo-outputs

Figure 3-3 Scan Effective Circuit

Design-for-Test for Digital IC’s and Embedded Core Systems © 1999 Prentice Hall, All Rights Reserved

Alfred L. Crouch

Chapter 3 Scan Architectures and Techniques

D

D

Q

4

Q

QN CLK

clk

Regular D Flip-Flop

SDO

D D

Q

SDI SE

Q SDO

clk

QN

CLK Scannable D Flip-Flop

Figure 3-4 Flip-Flop versus Scan Flip-Flop

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Chapter 3 Scan Architectures and Techniques

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SET D

SDO D

Q

Q

SDI QN SE clk

CLK Set-Scan D Flip-Flop with Set at Higher Priority

D SET

D

Q

SDI SE

SDO Q QN

clk

CLK Set-Scan D Flip-Flop with Scan-Shift at Higher Priority Figure 3-5 Example Set-Scan Flip-Flops

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Alfred L. Crouch

Chapter 3 Scan Architectures and Techniques

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Combinational and Sequential Logic input1 input2

output1

input3 input4 SE

SE

scanin

SDI

clk

Q

D

QN D

SDO

Q

SE

input5

SDI

D

input6

D

Q

SE

SE

SDI

SDI

0

scanout

Q

output2

SDO

SDO

1

SDO

1

1

4-Bit Scan Vector

Figure 3-6 An Example Scan Circuit with a Scan Chain

Design-for-Test for Digital IC’s and Embedded Core Systems © 1999 Prentice Hall, All Rights Reserved

Alfred L. Crouch

Chapter 3 Scan Architectures and Techniques

D

a D

SDI

7

Q

Q

b

QN SE

clk

SDO

CLK Scannable D Flip-Flop

The scan cell provides observability and controllability of the signal path by conducting the four transfer functions of a scan element. Operate: D to Q through port a of the input multiplexer: allows normal transparent operation of the element. Scan Sample: D to SDO through port a of the input multiplexer: gives observability of logic that fans into the scan element. Scan Load/Shift: SDI to SDO through the b port of the multiplexer: used to serially load/shift data into the scan chain while simultaneously unloading the last sample. Scan Data Apply: SDI to Q through the b port of the multiplexer: allows the scan element to control the value of the output, thereby controlling the logic driven by Q.

Figure 3-7 Scan Element Operations

Design-for-Test for Digital IC’s and Embedded Core Systems © 1999 Prentice Hall, All Rights Reserved

Alfred L. Crouch

Chapter 3 Scan Architectures and Techniques

D

From normal operation: D

Q

SDI

SE=0

Q QN

clk

SDO

CLK

Apply clocks for scan length D

Q

SDI SE=1

Q QN

SDO

clk

Scan Shift Load/Unload Mode

D

Q

SDI

Q QN

SE=1

clk

SDO

Scan Apply Mode (Last Shift)

The next rising edge of the clock will sample D

NOTE: unloading is simultaneous with loading the next test D

Q

SDI

SE=0

Normal circuit response will be applied to D

Return to Load/Shift mode to unload circuit response sample

CLK

D

When chain is loaded, the last shift clock will apply scan data While the clock is low, place SE = 0

CLK

D

While the clock is low, apply test data to SDI and Place SE = 1 At the rising edge of the clock, test data will be loaded

Functional Operation Mode

D

8

Q QN

clk

SDO

CLK Scan Sample Mode

Repeat operations until all vectors have been applied NOTE: the chip’s primary inputs must be applied during the scan apply mode (after the last shift)

Figure 3-8 Example Scan Test Sequencing

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Chapter 3 Scan Architectures and Techniques

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The Scan Sample The Last Shift In

The First Shift Out

CLK

SE

Scan Enable Assert

Scan Enable De-assert

The Output Pin Strobe SHIFT DATA

SHIFT DATA

FAULT EXERCISE

SAMPLE DATA

SHIFT DATA

SHIFT DATA

Faults Exercised Interval

Figure 3-9 Example Scan Testing Timing

Design-for-Test for Digital IC’s and Embedded Core Systems © 1999 Prentice Hall, All Rights Reserved

Alfred L. Crouch

Chapter 3 Scan Architectures and Techniques

Gated Clock Nets

10

clock tree distribution

Provide an Enable Signal f_seB force the clock on

Asynchronous or Synchronous Signals with Higher Priority than Scan—or Non-Scan Elements D Q HOLD SET CLR f_seB CLK Provide a Blocking Signal

D Q HOLD SET CLR CLK

Driven Contention During Scan Shifting

D Q

Q D

CLK

CLK

D Q

Q D

CLK

t_seB Provide a Forced Mutual Exclusivity

CLK

Figure 3-10 Safe Scan Shifting

Design-for-Test for Digital IC’s and Embedded Core Systems © 1999 Prentice Hall, All Rights Reserved

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Chapter 3 Scan Architectures and Techniques

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The Scan Sample The Last Shift In

The First Shift Out

CLK

Faults Exercised Interval SE

t_seB

a tristate scan enable may be a separate signal that has slightly different timing than the flip-flop SE

Driven Contention during the Capture Cycle

D Q

Q D

CLK

CLK

D Q

Q D

CLK

t_seB de-asserted

CLK

Figure 3-11 Safe Scan Vectors

Design-for-Test for Digital IC’s and Embedded Core Systems © 1999 Prentice Hall, All Rights Reserved

Alfred L. Crouch

Chapter 3 Scan Architectures and Techniques

12

Combinational-Only Logic

input1 input2 input3 input4

output1 D

Q QN D

Q

D

Q

input5

input6

D

Q

output2

TPI1 TPI2

TPO1

TPI3 TPI5

A clocked, sequential circuit with depth=1: 6 inputs plus 4 pseudo-inputs and 2 outputs plus 3 pseudo-outputs

TPO3 TPO4

Figure 3-12 Partial Scan

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Chapter 3 Scan Architectures and Techniques

13

An Example Using a Chip with 1000 Scan Bits and 5 Scan Vectors Red Space Is Wasted Tester Memory 1000

1000

One Long Scan Chain

1000

Vector Data

One Channel

1000

X’s on all Other Channels not actively used for parallel pin data

Each Vector is 1000 Bits Long So 5 Vectors Are 5000 Bits of Tester Memory

Many Variable Length Scan Chains

120 X 80 XXX 100 XX 110 XX 90 XXX 180 X20 XXXX 100 XX 100 XX 100 XX

120 X 80 XXX 100 XX 110 XX 90 XXX 180 X20 XXXX 100 XX 100 XX 100 XX

Vector Data Vector Data Vector Data Vector Data Vector Data Vector Data Vector Data Vector Data Vector Data Vector Data

120 X 80 XXX 100 XX 110 XX 90 XXX 180 X 20 XXXX 100 XX 100 XX 100 XX

120 X 80 XXX 100 XX 110 XX 90 XXX 180 X 20 XXXX 100 XX 100 XX 100 XX

10 Non-Balanced Channels

Each Vector Is 180 Bits Long—So 900 Bits of Tester Memory Differences from Longest Chain (180) Are Full of X’s—Wasted Memory

Many Balanced Scan Chains

100 100 100 100 100 100 100 100 100 100

100 100 100 100 100 100 100 100 100 100

Vector Data Vector Data Vector Data Vector Data Vector Data Vector Data Vector Data Vector Data Vector Data Vector Data

100 100 100 100 100 100 100 100 100 100

100 100 100 100 100 100 100 100 100 100

10 Balanced Channels

Each Vector Is 100 Bits Long—So 500 Bits of Tester Memory No Wasted Memory Space

Figure 3-13 Multiple Scan Chains

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Chapter 3 Scan Architectures and Techniques

14

Borrowed DC Scan Input on Bidirectional Pin Combinational Logic

Scan Data Input

Output Data Path Blocked during Scan Shift

Output Enable with bus_se Captures through the or scan_mode Combinational Logic during the Sample Operation Combinational Logic

Any Bidir Functional Pin

D S SE

Pad

Captures Directly from the Input Pin During the Shift Operation

Q Input

Parallel Scan Input to Chip Normal Input to Logic

SE

Input Scan Interface—May Resolve to Functional during Sample Interval

Borrowed DC Scan Output on Bidirectional Pin Last Scan Shift Bit from Scan Chain

D Q Input

Normal Output from Logic

D S SE

Q

S SE

Input Data Path Is a Don’t Care during Scan Shift SE on Input Combinational Blocks Data Logic

Combinational Logic

Output

a b s

Added Scan Output Mux with bus_se or scan_mode

Scan Data Output Any Bidir Pin

Pad

Functional Output Enable with bus_se or scan_mode added

Output Scan Interface—May Resolve to Functional during Sample Interval Figure 3-14 The Borrowed Scan Interface

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Chapter 3 Scan Architectures and Techniques

15

• Scan Bypass Clocks • Scan Testing an On-Chip Clock Source

Bypass Clocks

Analog

Digital 1

Digital 2

VCO Raw VCO Clock

Counters & Dividers

On-Chip Clock Generation Logic

Figure 3-15 Clocking and Scan

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Chapter 3 Scan Architectures and Techniques

16

Driven Contention during Scan Shifting

D Q

Q D

CLK

CLK

D Q

Q D

CLK

CLK

t_seB Provide a Forced Mutual Exclusivity

Asynchronous or Synchronous Signals with Higher Priority than Scan—or Non-Scan Elements D Q HOLD SET CLR f_seB CLK Provide a Blocking Signal

D Q HOLD SET CLR CLK

Gated Clock Nets Provide a Blocking Signal f_seB

Figure 3-16 Scan-Based Design Rules

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Chapter 3 Scan Architectures and Techniques

17

Basic Netlist Scan Insertion Element Substitution Ports, Routing & Connection of SE Ports, Routing & Connection of SDI-SDO Extras Tristate “Safe Shift” Logic Asynchronous “Safe Shift” Logic Gated-Clock “Safe Shift” Logic Multiple Scan Chains Scan-Bit Re-Ordering Clock Considerations

All Non-Sampling Clock Domains Inhibit Sample Clock Pulse

Last Shift

All Scan Chains (Clocks) Shift

Only One Clock Domain Conducts a Sample Clock

Figure 3-17 DC Scan Insertion

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Alfred L. Crouch

Chapter 3 Scan Architectures and Techniques

18

1

1

1

1

1

1

1

1

0

0

0

0

0

0

0

0

1

0

1

0

1

0

1

0

1

1

0

0

1

1

0

0

0

1

0

1

0

1

0

1

0

0

1

1

0

0

1

1

0

1

0

1

0

1

0

1

Scan Fail Data Presented at Chip Interface Automatically Implicates the Cone of Logic at One Flip-Flop

1 0

Multiple Fails under the Single Fault Assumption Implicate Gates Common to Both Cones of Logic

0

0 1

1

0 Figure 3-18 Stuck-At Scan Diagnostics

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Chapter 3 Scan Architectures and Techniques

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Basic Purpose • Frequency Assessment • Pin Specifications • Delay Fault Content

Cost Drivers • No Functional Vectors • Fewer Overall Vectors • Deterministic Grade

Figure 3-19 At-Speed Scan Goals

Design-for-Test for Digital IC’s and Embedded Core Systems © 1999 Prentice Hall, All Rights Reserved

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Chapter 3 Scan Architectures and Techniques

20

The Transition Launch The First Shift Out

The Last Shift In

The Transition Capture

CLK

Transition Generation Interval

Faults Exercised Interval

SE

T_SE

F_SE

Bus_SE

Separate Scan Enables for Tristate Drivers, Clock Forcing Functions, Logic Forcing Functions, Scan Interface Forcing Functions, and the Scan Multiplexor Control Because the Different Elements Have Different Timing Requirements

Figure 3-20 At-Speed Scan Testing

Design-for-Test for Digital IC’s and Embedded Core Systems © 1999 Prentice Hall, All Rights Reserved

Alfred L. Crouch

Chapter 3 Scan Architectures and Techniques

21

Borrowed Scan Input with Scan Head Register Output Data Path Blocked during Scan Shift Output Enable with bus_se Combinational Logic

Any Bidir Pin

D Q Input

Pad

Parallel Scan Input to Chip Normal Input to Logic

D S SE

Q Input

At-Speed Scan Interface—Resolves to Functional During Sample Interval

Driven Contention During Scan Shifting

D

Q

Q

CLK

CLK D

D

Q

Q

CLK

D

CLK

t_seB At-Speed Assert and De-Assert

Asynchronous or Synchronous Signals with Higher Priority than Scan or Non-Scan Sequential Elements D

Q

D

HOLD SET CLR CLK

Q

HOLD SET CLR

f_seB

CLK

At-Speed Assert and De-Assert Figure 3-21 At-Speed Scan Architecture

Design-for-Test for Digital IC’s and Embedded Core Systems © 1999 Prentice Hall, All Rights Reserved

Alfred L. Crouch

Chapter 3 Scan Architectures and Techniques

22

Borrowed AC Scan Input on Bidirectional Pin Combinational Logic

Output Data Path Blocked during Scan Shift Output Enable with at-speed bus_se

Scan Data Input

Captures through the Combinational Logic during the Sample Operation Combinational Logic

Any Bidir Functional Pin

S SE

Pad

Parallel Scan Input to Chip Normal Input to Logic

D Q Input

Captures Directly from the Input Pin During the Shift Operation

D Q Input Head

Input Scan Interface—Resolves to Functional during Sample Interval

Borrowed AC Scan Output on Bidirectional Pin Last Scan Shift Bit from Scan Chain

D Q Input

Normal Output from Logic

D S SE

Q Output

S SE

Input Data Path Is a Don’t Care during Scan Shift SE on Input Combinational Blocks Data Logic

Combinational Logic

a

D Q b Output s Tail

Added Scan Output Mux with bus_se

Scan Data Output Any Bidir Pin

Pad

Functional Output Enable with bus_se Added

Output Scan Interface—Resolves to Functional During Sample Interval Figure 3-22 At-Speed Scan Interface

Design-for-Test for Digital IC’s and Embedded Core Systems © 1999 Prentice Hall, All Rights Reserved

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Chapter 3 Scan Architectures and Techniques

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Fast to Slow Transfers

Slow to Fast Transfers

Fast Logic

Slow Logic Fast to Slow Transfers

Fast Scannable System Registers

Slow Scannable System Registers

Clock A Scan Enable A

Clock B Scan Enable B

The Clock Domains and Logic Timing should be crafted so that the very next rising edge after the launch or last shift is the legal capture edge Last Scan Shift Edge

Legal ATPG Transfer

Illegal ATPG Transfer

Applied Fast Clock

Applied Slow Clock

Only Fast-to-Slow Legal ATPG Transfer

Figure 3-23 Multiple Scan and Timing Domains

Design-for-Test for Digital IC’s and Embedded Core Systems © 1999 Prentice Hall, All Rights Reserved

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Chapter 3 Scan Architectures and Techniques

24

Combinational Logic

Combinational Logic

Combinational Logic scanned flip-flop D

Q

D

SDI

Q

D

SDI

Q

SDI 165 ps

CLK

120 ps

SE

150 ps

First Clock Domain — All Elements on Same Clock Tree 300ps+

Cross Domain Clock Skew

Combinational Logic

Combinational Logic

Combinational Logic scanned flip-flop

D

Q

D

SDI

Q

D

SDI

Q

SDI 165 ps

CLK SE

120 ps 150 ps

Second Clock Domain—All Elements on Same Clock Tree Cross Domain Clock Skew must be managed to less than the fastest flip-flop update time in the launching clock domain If it is not, then the receiving flip-flop may receive new-new scan data before the capture clock arrives To prevent this outcome, constrain the ATPG tool to only sample one clock domain at a time during the sample interval

Figure 3-24 Clock Skew and Scan Insertion

Design-for-Test for Digital IC’s and Embedded Core Systems © 1999 Prentice Hall, All Rights Reserved

Alfred L. Crouch

Chapter 3 Scan Architectures and Techniques

25

Specification Development Scan Mode Bus_SE Tristate_SE Logic Force_SE Architecture Development

Simulation Verification

Model

Behavior Synthesis

Scan Shift SE Clock Force_SE Scan Data Connection Insertion

Timing Analysis

Place and Route

Scan Chain Bit Re-Ordering

Specification Determination

Gates Mask

Mask and Fab

Silicon Test

Silicon Design Flow Chart Scan Mode: Fixed “Safe” Logic

Scan Enable (SE): Scan Shift

Force_SE:

Force_SE: Clock Force States

Logic Forced States

Tristate_SE: Internal Tristates

Bus_SE: Scan Interface Control

Figure 3-25 Scan Insertion for At-Speed Scan

Design-for-Test for Digital IC’s and Embedded Core Systems © 1999 Prentice Hall, All Rights Reserved

Alfred L. Crouch

Chapter 3 Scan Architectures and Techniques

D Q R1 D Q R2 In1

0>1

A U35 B 0 X

In2 0

In3

0

In4 0

A U36 B A U39 B

26

Static Timing Analysis Provides Path Description of Identified Critical Path from the Q-Output of R1 to the Device Output Pin—Out1

0>1

1

A U37 B

1>0

A U38 B

1>0

Out1

1 Isolated Combinational Logic All Fan-in to Endpoint Is Accounted at this Endpoint Fanout to other Endpoints is Evaluated atThose Endpoints

Period = 20ns : Output Strobe @ 15ns Path Element Incremental Cumulative Description Delay Delay

Clk R1.Q U35.A U35.Z U37.A U37.Z U38.A U38.Z Out1

2.2ns 0.0ns 2.1ns 0.1ns 3.2ns 0.2ns 2.2ns 0.1ns Dly=10.1

Skew Amb. 0.0ns 2.1ns 2.2ns 5.4ns 5.6ns 7.8ns 7.9ns Slk=4.9ns

Timing Analysis Report Figure 3-26 Critical Paths for At-Speed Testing

Design-for-Test for Digital IC’s and Embedded Core Systems © 1999 Prentice Hall, All Rights Reserved

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Chapter 3 Scan Architectures and Techniques

27

Polynomial: X3 + X +1 = X3 + X1 + X0 = 23 + 21 + 20 = 11

LFSR - PRPG: pseudo-random pattern generation

X3 Seed

DQ 1

X2

DQ 1

X1

DQ 1

CLK

X0

111 011 001 100 010 101 110 111

Chip with Full-Scan and X-Management

DQ

DQ

DQ

CLK LFSR - MISR: multiple input signature register

Figure 3-27 Logic BIST

Design-for-Test for Digital IC’s and Embedded Core Systems © 1999 Prentice Hall, All Rights Reserved

Alfred L. Crouch

Chapter 3 Scan Architectures and Techniques

28

Scan Testing Methodology Advantages Direct Observability of Internal Nodes Direct Controllability of Internal Nodes Enables Combinational ATPG More Efficient Vectors Higher Potential Fault Coverage Deterministic Quality Metric Efficient Diagnostic Capability AC and DC Compliance Concerns Safe Shifting Safe Sampling Power Consumption Clock Skew Design Rule Impact on Budgets Figure 3-28 Scan Test Fundamentals Summary

Design-for-Test for Digital IC’s and Embedded Core Systems © 1999 Prentice Hall, All Rights Reserved

Alfred L. Crouch