Cadence SPB: What's New in 16.6 HotFix 006
Cadence® SPB: What’s New in 16.6 HotFix 006 This document describes the new features and enhancements in Cadence SPB products in 16.6 HotFix 006. The products covered are: ■
Allegro® PCB Editor
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Virtuoso® SiP Architect
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Allegro® Design Entry HDL
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Variant Editor
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Allegro® FPGA System Planner
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OrCAD® Capture
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Cadence SPB: What's New in 16.6 HotFix 006 Allegro® PCB Editor
Allegro® PCB Editor This section describes the new features and enhancements in Allegro PCB Editor 16.6 HotFix. ■
Route Interconnect Optimization
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Productivity Enhancements
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Database & Miscellaneous Enhancements
Route Interconnect Optimization A major effort targeted at improving the productivity and efficiency aspects of the interactive routing environment continues into the post-16.6 HotFix releases. ■
Auto-Interactive Phase Tune (AiPT) – High Speed Product Option
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Timing Vision – High Speed Product Option
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Unsupported Prototype Menu
Auto-Interactive Phase Tune (AiPT) – High Speed Product Option With an ever increasing amount of Differential Pairs associated with current Interface protocols, design tools need to be enhanced to support the requirements related to tuning and matching. Allegro currently supports very good interactive tools (delay tune and phase tune) to perform tuning on selected differential pairs or stand-alone nets. The increase in differential pair quantity has made is necessary to introduce an auto-interactive method to perform tuning across all differential pairs associated with a group or Interface. Auto-interactive Phase Tuning if offered from the Route – Unsupported Prototypes Menu. It works with a set of parameters that allows the user several options for trace lengthening or shortening. Greater detail can be found in the AiDT help doc conveniently located in the Route – Unsupported Prototype menu structure. The following parameters support the AiPT feature:
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Compensation Location (Loc) ■
Any - This option lets the tool place the allowed compensation technique preferably at either end of the differential pair when trying to satisfy static phase constraints. When working with Dynamic Phase constraints it could put phase compensation bumps anywhere along the C-Line paths from “pin-to-pin” when the Allow Uncoupled Bumps techniques is set to Yes.
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High_Pin Comp - Specifies that only the end of the differential pair that connects to the highest pin count component can be modified in the pin/via pad entry area. For example - the tool can modify the BGA end of your memory system.
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Low_Pin Comp - Specifies that only the end of the differential pair that connects to the lowest pin count component can be modified in the pin/via pad entry area. For example - the tool can modify the DIMM end of your memory system.
Compensation Techniques ■
Pad Entry Shortening - This technique enables (Yes) or disables (No) the tools ability to SHORTEN the LONGER half of the pair by making modifications to the existing route pattern ONLY in the region from the gather point to the pin or via as it tries to match the phase imbalance between the two halves of the pair. This technique WILL use the Allow off-angle segs technique if enabled.
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Pad Entry Lengthening - This technique enables (Yes) or disables (No) the tools ability to LENGTHEN the SHORTER half of the pair. It focuses on the region from the gather point to the pin or via as it “wraps around” the pad in order to match the phase imbalance between the two halves of the pair. This technique will use only 45 degree segments in the wrap BUT it WILL use the Allow off-angle segs technique (if enabled). Pad Entry Lengthening WILL NOT wrap more than 180 degrees around the pad.
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Allow off-angle segs - This option allows the tool to try to create “off-angle” (non 45/ 90 degree) pad entry segments ONLY when trying to solve the phase compensation problem. This is frequently done in tight pin fields, or when just slight shortening of one half of the pair is required.
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Allow Gather Move - This option allows the tool to modify the actual differential pair gather point. The use of this option when coupled with the Allow off-angle segs option can be very effective.
Allow Uncoupled Bumps This option and settings tell the tool to put phase compensation “delay” bumps into the CLines to try and bring the pair within tolerance. The values that create the bump(s) are user definable and the tool will try to create as many bumps as needed to meet the constraints. During processing AiPT WILL NOT push existing traces or vias to make space for phase bumps and it WILL NOT create DRC errors with existing traces or vias. In order to define the bumps, you have two options – ❑
Height – this key-in/pull-down value controls the size or distance that the delay bump will spread the pair apart. It is similar to the manual version of phase adjustment found in the Route – Phase Tune command and its values can be specified in either line width or database units.
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Length – this key-in/pull-down value controls the length of each delay bump created. It is similar to the manual version of phase adjustment found in the Route – Phase Tune command and its values can be specified in either line width or database units.
Example – The following graphic outlines a phase tune adjustment using bumps and off-angle segments. Refer to the help document located in Unsupported Prototypes menu for many more illustrations.
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Timing Vision – High Speed Product Option “Timing Vision” is an “environment” that allows user to graphically see real-time Delay and Phase information directly on the routing canvas. Traditionally, evaluating timing/length related issues required numerous trips to Constraint Manager and/or use of the Show Element command to evaluate the DRC condition. The new “Timing Vision” environment uses special graphic techniques such as: custom cline coloring; stipple patterns and customized data tip information to define the delay problem in the simplest terms possible. The user has control over the settings for these techniques, as well as when the graphics changes occur and which nets in the design are affected. When active ‘Timing Vision” does not alter the physical routing, or permanently affect any of the user’s custom color code settings that have been applied to nets, pins, vias, net-groups, etc. “Timing Vision” can provide immediate real time feedback to the user during interactive and it also enhances the user's ability to develop a strategy for resolving timing on large buses or interfaces such as DDRx, PCI-Express, etc. To start “Timing Vision” you can access it from the Route – Unsupported Prototypes – Timing Vision – Timing Mode or Sphase Tol Mode menu selection. This will “override” your existing color scheme in favor of the color/stipple choices you have set in Design Parameter.
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Cadence SPB: What's New in 16.6 HotFix 006 Allegro® PCB Editor Design Parameters for Timing Vision can be found in Setup – Design Parameters – Route – Timing Vision Folder.
Using DRC/Timing mode on an entire interface can quickly point to timing errors that may have been caused by small routing/placement changes, or just fine tuning those final routes. This is best on interfaces/buses that have already gone through some passes of tuning to meet constraints. In this picture the use can quickly find the 6 signals with errors (red/yellow) and correct those without searching through multiple constraints and/or matchgroups to find the problem
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Refer to the help document located in the Unsupported Prototypes menu for details on the Timing Vision environment. Before entering this environment, it is important to understand the data settings of “DRC” and “Smart” and how they may work best for your constrained design.
Unsupported Prototype Menu The Route – Unsupported Prototype menu will always be visible beginning in the 16.6 release; variable is no longer required. Please check this location periodically for prototype applications.
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Productivity Enhancements ■
Highlight/Assign Color to Vias
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Display-Measure support of angle between two objects
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Display Segments over Voids
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DRC marker – Link to Constraint Manager
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Expand/Contract Shape updated to support Voids
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Net assignment to multiple shapes
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Placement Replication support for component level pin properties
Highlight/Assign Color to Vias The Highlight and Assign Color commands now support vias as an element for permanent highlighting. Prior to 16.62, vias could only be temporarily highlighted.
Display-Measure support of angle between two objects The Display – Measure command now lists the angle between two selected objects. This may be helpful when doing offset routing.
Display Segments over Voids A new User Preference variable has been added to control the partial/missing plane coverage checking. When enabled, the SOV application will skip the checking of plane related violations. User Preference Editor – Display – Seg_Over_Void - Sov_skip_plane_check
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DRC marker – Link to Constraint Manager Using General Edit application mode, users will be able to hover over a DRC and from the pop-up menu select a new Display DRC option. The new command will open CM, and highlight the DRC in CM worksheet.
Expand/Contract Shape updated to support Voids The Expand/Contract shape command was introduced in 16.6 and was limited to shape objects. Hover over a shape then use the context sensitive menu to access the command. Based on user feedback, voids are now selectable for expansion and contraction. Qualifying voids must be user defined, not auto-generated. Tip Ensure the boundary subclass is visible when hovering over a user defined void.
Net assignment to multiple shapes Up until now, the assignment of a net was limited to a single selected shape. Using “General Edit” or “Etch Edit” Application Modes, one can now pre-select multiple shapes then use the context sensitive Assign Net command.
Placement Replication support for component level pin properties Currently when applying or updating a placement replication module (.mdd), pin level properties are not updated across the module instances. If you wish to retain pin properties in 16.62, set the User Preference variable plc_rep_copy_attr User Preference Editor – Placement – General – plc_rep_copy_attr
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Database & Miscellaneous Enhancements ■
Database Locks
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Database Tiering – New Open Drawing Message
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Logo Import (Symbol Editor only)
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New Reports
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Slot Notes
Database Locks The Database locking feature found in the File – Properties menu has been enhanced to support: ❑
Expiration Duration (90, 180, 365, no limit)
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Lock Modes ❍
View (no save and export)
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No Export
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No Saving
Database Tiering – New Open Drawing Message When an Allegro database is opened, Allegro compares the current product plus options capability against the fully licensed design. A warning message will be reported to the user informing them of capabilities available in the design that are disabled with the current product plus options selection. For example, if the user opens a design with Micro vias present in “Allegro PCB Designer”, a warning is shown informing the user that Micro vias are present but are disabled. The following capabilities will be checked: ❑
All electrical DRC modes
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Differential pair static and dynamic phase control
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Pin Delay
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Via Z
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Constraint Regions
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Micro via padstacks
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Embedded layers
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Dynamic fillets
If the capabilities of the design are more than current product plus options, a warning message is generated and DRC is set out of date. The message shown is: WARNING: This design has functionality disabled due to the product with options selected. The following features are disabled: . DRC is set out of date.
Logo Import (Symbol Editor only) The Symbol Editor has been enhanced to read in bit map files. The format for bit map files is limited to .bmp. Logo Import can be found in the File – Import menu and by default, the vectorized bitmap will be written to the Board Geometry – Silkscreen_Top Class/ Subclass.
New Reports ■
Film Area – percentage of metal added to this report
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Vias per net – new report lists quantity of vias and via types per net
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Vias per layer per net – new report lists via quantity, type by layer
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Slot Notes A ?SlotNotes directive is now supported in the drill legend template (.dlt) files. If a separate slot hole legend is requested the ?SlotNotes will appear with the legend table for the slot hole legend.
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Product Version 16.6
Cadence SPB: What's New in 16.6 HotFix 006 Virtuoso® SiP Architect
Virtuoso® SiP Architect This section describes the enhancements and new features in Virtuoso SiP Architect 16.6 HotFix. ■
Die Export Enhancements
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Import Model Enhancements
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RDL Export Through Co-Design File
Die Export Enhancements Changes in Default Settings Starting this HotFix, the default behavior of the Die Export command is modified. Now, the Use Virtuoso Floor Plan Setting option is selected by default. As a result of this enhancement, by default, die bumps are transferred as die pins. To enable shape transfer, you need to deselect this option. Note: The change in the default behavior is visible only in new designs. Designs for which die data is already generated by running the Export Die command, are not impacted by this enhancement. Suppressing Confirmation Messages While running exportdie command, you need to answer confirmation messages, to be able to proceed to next step. In this release, a new environment variable, SIP_DIE_AUTO_MODE, has been introduced to suppress these messages and enable running exportdie command in the quiet mode. Depending on the kind of message, and the value assigned to the environment variable, the die export process is either continued or assigned the value that is same as the value of the environment variable. Following table shows some of the confirmation messages displayed
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Product Version 16.6
Cadence SPB: What's New in 16.6 HotFix 006 Virtuoso® SiP Architect during die export process, and also lists the impact if the SIP_DIE_AUTO_MODE variable is set.
SIP_DIE_AUTO_MODE value
Message
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Independent of the value assigned to SIP_DIE_AUTO_MODE
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Message suppressed and die export continues.
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Independent of the value assigned to SIP_DIE_AUTO_MODE
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Message suppressed and die export continues.
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SIP_DIE_AUTO_MODE set to Yes The symbol is created from layout view.
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SIP_DIE_AUTO_MODE set to any value other than Yes The symbol is created from the schematic view.
Caution The values assigned to the SIP_DIE_AUTO_MODE environment variable are case sensitive.
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Cadence SPB: What's New in 16.6 HotFix 006 Virtuoso® SiP Architect
Import Model Enhancements The model import feature in Virtuoso Layout Editor (VLE) is enhanced to support file extensions with uppercase alphabets. For example, S-Parameter models with extension .S4P — generated by Sigrity PowerSI tool — can now be imported in the design library.
RDL Export Through Co-Design File SiP Virtuoso Architect shipped with 16.6 HotFix, is enhanced to export RDL route information. If you run Export Die command on a codesign die in Virtuoso Layout Editor, along with the die data, information about the RDL routes is also exported. This information is written in the die abstract file and the abstract view.
RDL route in Virtuoso Layout Editor
RDL route in abstract view
Tip The RDL route information is for viewing and cannot be edited in SiP Layout.
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Product Version 16.6
Cadence SPB: What's New in 16.6 HotFix 006 Allegro® Design Entry HDL
Allegro® Design Entry HDL This section describes the enhancements in Allegro Design Entry HDL 16.6 HotFix. ■
Enhancements in Variant Editor
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Enhancements in Cross Referencer
Enhancements in Variant Editor The latest 16.6 HotFix release includes significant enhancements in Variant Editor, which facilitate dynamic viewing of variants in the DEHDL schematic editor. For more information, see the Variant Editor section of this document.
Enhancements in Cross Referencer Cross Referencer now supports generation of cross references for nets across all levels of a hierarchical design. As a result, you can view and navigate to the nets from all the levels of a hierarchical design. The cross references generated after selecting the Generate Cross References for all nets option in the Cross Referencer Options dialog, contain data considering nets from all the levels of the hierarchy.
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Product Version 16.6
Cadence SPB: What's New in 16.6 HotFix 006 Variant Editor
Variant Editor This section describes the enhancements in Variant Editor 16.6 HotFix. ■
Enhancements in Variant Editor
Enhancements in Variant Editor The latest 16.6 HotFix release includes significant enhancements in Variant Editor, which facilitate dynamic viewing of variants in the DEHDL schematic editor. Some of the enhancements include: ■
A new dialog box, Variant Details, to create a new, or edit or rename an existing variant. The properties you can specify or modify include variant property, property value, and the Do Not Install (DNI) status.
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A new tool bar in Design Entry HDL allows you to select a variant from a list of available variants. You can switch from the base schematic view to the variant view. When you select a variant, only variant-specific information is displayed on the schematic canvas.
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Variant view is now a complete hierarchical schematic with occurrence -specific data and cross-referencer data. Therefore, you can plot or publish a PDF of the complete hierarchical schematic with the occurrence, cross-reference, and variant data.
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The Design Entry HDL Options dialog, includes a new tab, Variant Overlay Options, where you can specify whether you want to display the DNI property, cross out the DNI components, or show all properties of DNI components on the canvas. You can also specify color options for variant-specific components, variant-specific properties, DNI components, and DNI cross.
For more information, see Design Variance User Guide.
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Product Version 16.6
Cadence SPB: What's New in 16.6 HotFix 006 Allegro® FPGA System Planner
Allegro® FPGA System Planner This section describes the new features and enhancements in Allegro FPGA System Planner16.6 HotFix. ■
New Device Support
New Device Support In 16.6 HotFix, Arria V GX family devices are supported.
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Product Version 16.6
Cadence SPB: What's New in 16.6 HotFix 006 OrCAD® Capture
OrCAD® Capture This section describes the new features in OrCAD Capture 16.6 HotFix. ■
Text Justification in OrCAD Capture
Text Justification in OrCAD Capture
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Product Version 16.6
Cadence SPB: What's New in 16.6 HotFix 006 OrCAD® Capture In OrCAD Capture, you can now justify comment text and the text of displayed properties of any Capture object, such as Part, Off Page Connector, and Port. You can justify text by choosing any of the options: Default, Right, Center, and Left.
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Cadence SPB: What's New in 16.6 HotFix 006 OrCAD® Capture
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Product Version 16.6
