Atmel SMART | SAM D Series Differentiating Features
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48MHz operation ±2% int RC oscillator 1.62V-3.63V 16KB to 256KB Flash 32-, 48- and 64-pin versions
• Event system • SERCOM modules configurable as I2C, • • • •
USART or SPI Capacitive Touch HW engine 12-bit 300ksps ADC with gain stage 10-bit 300ksps DAC Full Speed USB • Device from int RC oscillator • Embedded host
Easy Code Migration Within Atmel SMART | SAM D Series (HEX compatible) Easy Migration to Atmel SAM4L Family Easy Migration Between Pinouts Easy Migration to Future Atmel SMART | SAM devices
• External 32k oscillator • 32.438kHz crystal or external clock
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DFLL48M
• 48MHz internal Digital Frequency Locked Loop • Operates in closed or open loop modes • Any clock generator can be used as a source • Best results with a slow clock source (32k) • No arbitrary frequency, designed for 48MHz
• Drift compensation
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17
SYSCTRL also controls Brown-out detectors, voltage regulator and voltage reference
Clock & System Management Enable a peripheral clock
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Done in 4 steps:
• Enable the source clock (SYSCTRL) • Enable and configure a Generic Clock Generator (GCLK) • Enable and configure the appropriate Generic Clock Multiplexer to •
generate the generic clock (GCLK) Unmask the peripheral interface clock (PM)
• APB clock coming from Power Manager, which is synchronous • Core clock coming from GCLK, which is asynchronous • Allows to clock a peripheral externally and keep it enabled in idle/standby mode
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CPU accesses to asynchronous peripheral, registers need to be synchronized
• Registers in the bus interface doesn’t need synchronization • Registers in the generic clock need synchronization
Synchronization Status provided by SYNCBUSY flag in Status Register
• User has to check the flag before reading/writing a register
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Several actions require synchronization
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Some Some Some When When
registers need synchronization when read registers need synchronization when written registers need synchronization when written and read enabling the peripheral executing a software reset of the module
Synchronization delay formula: 5 ⋅ PGCLK + 2 ⋅ PAPB < D < 6 ⋅ PGCLK + 3 ⋅ PAPB D: Delay PGCLK: Generic clock period PAPB: Bus Interface period
Powers IO lines, OSC8M and XOSC Powers IO lines, analog peripherals, POR, BODs and 32K oscillators Internal voltage regulator output. Powers the core, memories and peripherals
Power Management Designed for energy efficiency
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Advanced clock management features
• SleepWalking peripherals • On-demand clock request to minimize power consumption on both active and low power modes
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Ultra-low power oscillator
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Low power figures
• More flexibility at application Level
• More flexibility in MCU selection • More Flexibility in PCB layout
• Main user interface • Allows to configure SERCOM and control the IP • Available Bit field in control/status register will depend on the selected Communication mode
